Integrated Circuits

ECE481
Fall 2021
M1: IC Technology
Lecture 2
ICs Cost & Scaling
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE481 – M1 Lecture 2 1

Outline

• Cost of Integrated Circuits

– Variable Cost
– Dies per Wafer
– Die Yield
• CMOS Scaling
• CMOS Scaling Limits & Future Trends

D. Khalil ECE481 – M1 Lecture 2 2

Fall 2021 1
 Cost of Integrated Circuits

NRE (non-recurring engineering) costs – fixed

– Examples:
• design time and effort  complexity, designer productivity
• mask generation, slow and expensive process
• research and development (R&D)
• manufacturing equipment, building infrastructure, …
– increases as we move to complex process generations
– one-time cost factor, independent of the number of products sold
– penalize small-volume products
Recurring costs – variable
– Examples:
• fabrication, packaging, test
– proportional to volume
– proportional to chip area

D. Khalil ECE481 – M1 Lecture 2 3

Individual die
Variable Cost
Total Cost  Fixed Cost  Variable Cost
Fixed Cost  Variable Cost
Chip Total Cost 
Volume
Fixed Cost
  Chip Variable Cost
Volume Wafer
Die Cost  Chip Packaging Cost  Chip Testing Cost
Chip Variable Cost 
Final Test Yield
Wafer Cost Good Dies per Wafer
Die Cost  Die Yield  100%
Dies per Wafer  Die Yield Dies per Wafer
Good Chips after Packaging & Testing
Final Test Yield  100%
Good Dies before Packaging & Testing
Wafer cost is fixed per fabrication technology
 Die cost depends on the number of dies on a wafer.
 Increasing die area means fewer dies per wafer and higher cost.
D. Khalil ECE481 – M1 Lecture 2 4

Fall 2021 2
 Dies per Wafer

• Wafers are round  incomplete dies at the perimeter are lost.

  wafer diameter/22   wafer diameter

Dies per Wafer  
die area 2  die area

wafer wafer
large die area small die area

• Two ways to increase dies per wafer:

– Increase wafer size: Difficult. Wafers now reached 45cm diameter.
Fabs with larger wafer diameter offer lower cost.
– Decrease die area: Easier. Use smaller technology (cost tradeoff).
Design more area efficient circuits.
• While fab controls wafer diameter & transistor size,
designer controls die area.

D. Khalil ECE481 – M1 Lecture 2 5

Yield & Defects

Which is better? Let’s calculate die cost.


 defects per unit area  die area 
Statistical Equation Die Yield  1  
  
a is “cluster factor” related to defects distribution (typically ranges from 0.5
for extreme process control to 4.2 for bad process control, and the value
2.6 is commonly used as average).

Wafer Cost
Overall die area dependence Die Cost 
Dies per Wafer  Die Yield
die cost  (die area)3.6  area 1  area 
2.6

D. Khalil ECE481 – M1 Lecture 2 6

Fall 2021 3
 Outline

• Cost of Integrated Circuits

• CMOS Scaling
– Scaling Techniques
– Moore’s Law
– Examples
• CMOS Scaling Limits & Future Trends

D. Khalil ECE481 – M1 Lecture 2 7

CMOS Technology Scaling

• Feature length: drawn gate length

Feature Length
• Gate Pitch: min. repeat distance
L
• 32 nm fabrication technology
 feature length is 32 nm

• What happens as feature length & gate pitch

get smaller? W
– Transistors can be made smaller
– Transistors can be made faster
– Transistors can use less power
• Let’s see how.

Metal1 Pitch
Gate Pitch

D. Khalil ECE481 – M1 Lecture 2 8

Fall 2021 4
 Full Scaling – Constant Electric Field
All dimensions & supply/threshold voltages are scaled equally.
Keeping E constant avoids breakdown and other secondary effects.
• Lateral and vertical dimensions (W, L, Tox): 0.7
• Power supply VDD (constant electric field = VDD/Tox): 0.7

• Area: WL = 0.5 (Area scales down quadratically)

• :  W/(LTox) = 1.43
• Saturation Current (long-channel) IDS (VDD-VT)2 = 0.7
• Saturation Current (short-channel) IDS:  (W/Tox )(VDD-VT) = 0.7
• Driving Resistance RDRV:  VDD/IDS = 1
• Gate Capacitance CG : WL/Tox= 0.7
• Delay :  RDRVCG = 0.7 (Delay scales down linearly)

• Frequency f: 1/ = 1.43

• Power Dissipation P: CVDD²f = 0.5 (Power scales down quadratically)
• Power Density: P/A = 1
D. Khalil ECE481 – M1 Lecture 2 9

Other Techniques of Scaling

• “Constant electric field scaling” is not usually applicable.

Example, it may be desired to keep new chips compatible with
older ones, so supply voltage must not change.
• Historically, Supply was kept constant at 5V till early 90s, then
reduced in steps: 5V  3.3V  2.5V  1.8V … 0.8V.
• “Constant voltage scaling” was used at some points.
• Another example, it is technically difficult to reduce supply voltage
below some limits imposed by fixed internal voltages, like silicon
bandgap and built-in junction potential, and threshold voltage limits
to avoid high leakage when it is too low.
• A “general scaling” technique is now being used where voltages
are scaled but at a slower rate than feature size.
• Exercise problem will discuss these techniques in more details.

D. Khalil ECE481 – M1 Lecture 2 10

10

Fall 2021 5
 Moore’s Law
16
Electronics (1965)
• In 1965, Gordon Moore,

COMPONENTS PER INTEGRATED FUNCTION

15
14
cofounder of Fairchild SC & Intel, 13

LOG2 OF THE NUMBER OF

12
made an observation that the 11
10
number of transistors in a chip 9
8
doubles every year and predicted 7
6
that this trend will continue. 5
4
3
• This was generally made possible 2
1
by 0.7x scaling every year. 0

1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
• Now 0.7x scaling is faced by
more challenges to create a
transistor with good performance.
• Hence, Moore’s law slowed down
to every 1.5 or 2 years.

Intel Press Release (2012)

D. Khalil ECE481 – M1 Lecture 2 11

11

Moore’s Law

• The benefit of scaling is great:

– Transistors get smaller  More functionality and complexity
– Transistors get cheaper  Chip cost will reduce or stay constant
– Transistors get faster  Better performance
– Transistors use less power  more energy efficiency

• Hence, ICs become more powerful and efficient as they get scaled.
This isn’t true for other industries.
This unusual mixture: smaller = faster = more powerful = cheaper,
is what sets ICs apart from any revolutionary technology in the
history of the world.

• Moore’s law was a driving force to the ICs industry. All efforts
collaborated to keep up the trend and benefits.

D. Khalil ECE481 – M1 Lecture 2 12

12

Fall 2021 6
 Moore’s Law & Chip Cost
• Wafer cost is growing due to fabrication complexity.
However, Scaling causes cost per transistor/gate/function to drop
exponentially.
• Die area/cost can correspondingly drop exponentially.
However, market demands add more functionality and complexity
in an exponential trend such that die area remains almost constant
and die cost slightly increases.

D. Khalil ECE481 – M1 Lecture 2 13

13

Moore’s Law & Chip Cost

• Designer productivity improves with time, design reuse, and
automation. However, it does not increase at the same rate as the
complexity.
• Die area is almost constant as the number of transistor/gate/function
increases exponentially. Hence, the total design cost increases
exponentially as the circuit complexity.
• Productivity gap exists as the design teams do not expand that fast!

D. Khalil ECE481 – M1 Lecture 2 14

14

Fall 2021 7
 Moore’s Law Example
,

D. Khalil ECE481 – M1 Lecture 2 15

15

Scaling Example

Porting Technology shrinks by ~0.7x

per generation (~2 years)
Re-design

Porting: Moving same design to new technology

D. Khalil ECE481 – M1 Lecture 2 16

16

Fall 2021 8
 Scaling Example

• Evolution of Sony PS2 Chips

D. Khalil ECE481 – M1 Lecture 2 17

17

Outline

• Cost of Integrated Circuits

• CMOS Scaling
• CMOS Scaling Limits & Future Trends
– Optical Scaling Limits
– Transistor Scaling Limits
– Wire Scaling Limits
– Power & Power Density Limits
– Design Productivity Limits

D. Khalil ECE481 – M1 Lecture 2 18

18

Fall 2021 9
 CMOS Scaling Limits & Future Trends
• CMOS scaling in deep-submicron dimensions have always faced
issues related to optical limitations, transistor limitations, wire
limitations, power limitations, …
• However, innovation and creative thinking had always helped
overcome the issues and limitations.
• Scientists predicted for several times that scaling will come to an
end. However, CMOS scaling continues!
• Latest prediction is that CMOS scaling will hit a fundamental
quantum mechanics limit at 3.8nm by Nikonov & Bourianoff 2008.
• Huge research is done to explore ways to go beyond CMOS
scaling limits, as well as, alternative devices, wires, and
technologies.
• However, even when scaling stops, CMOS technology and ICs
industry will never stop, as innovation will shift more to circuit
design, automation, applications, and services.

D. Khalil ECE481 – M1 Lecture 2 19

19

Optical Scaling Limits

• Transistor dimensions keep scaling down.

UV light
• Wavelength of UV light source does not.

• Can we create shapes smaller than

wavelength?! Yes.
– OPC (Optical Proximity Correction)
– Double-patterning
Mask with 4 dies
per exposure

Wafer
D. Khalil ECE481 – M1 Lecture 2 20

20

Fall 2021 10
 Optical Scaling Limits

Target

350nm

Without OPC
D. Khalil ECE481 – M1 Lecture 2 21

21

Optical Scaling Limits

Target

90nm

Without OPC
D. Khalil ECE481 – M1 Lecture 2 22

22

Fall 2021 11
 Optical Proximity Correction (OPC)

OPC is a mask enhancement technique to

compensate for fabrication errors due to
diffraction and other fabrication processes.

D. Khalil ECE481 – M1 Lecture 2 23

23

Phase-Shift Masks

• Phase-shift masks deliberately introduces phase shift to light and

use interference to improve the printed image in photolithography.

• Alternating phase-shift masks make

certain transmitting regions of the
mask thinner or thicker, introducing
a phase-shift in the light traveling
through those regions.

• Attenuated phase-shift masks make

certain blocking regions of the mask
partially transmitting to allow small
amount of light to pass and interfere
with light from the transmitting regions.

D. Khalil ECE481 – M1 Lecture 2 24

24

Fall 2021 12
 Multiple Patterning
• At some point, no way close & thin lines can be created due to
light diffraction. A solution is to split mask into two masks, each
with double pitch density (Pitch-splitting or Double-patterning).

One Mask Mask 1 (red) Mask 2 (green)

• Can be extended to multiple splittings / patterns. (Expensive).

• Better solution is self-alligned multiple patterning.
D. Khalil ECE481 – M1 Lecture 2 25

25

Transistor Scaling Limits

• Short channel effects get more
severe as transistor is scaled.
• Also process variations get more
severe as transistor is scaled.
• At deep-submicron channel lengths,
the gate is losing control on current
and, ultimately, cannot turn it off.

• A solution is to create new transistor

with multiple-gates, to make sure
gate potential is applied effectively.
Channel 2
• Intel started production of a fin-FET
at 22nm. Note that, in a fin-FET,
transistor width is discrete. Channel 1

D. Khalil ECE481 – M1 Lecture 2 26

26

Fall 2021 13
 Transistor Scaling Limits
• The smallest transistor demonstrated in a lab so far is 3nm all-
around-gate fin-FET.
• Smaller Fin-FET is reaching atomic quantum mechanics limits.
• Significant research is conducted in CMOS compatible carbon-
nanotubes and graphene based transistors, as well as, non-
CMOS compatible molecular transistors.

Carbon-nanotube FET (IBM) Graphene FET (IBM)

D. Khalil ECE481 – M1 Lecture 2 27

27

Wire Scaling Limits

• Wires also need to scale along with transistors to improve
integration density.
• Ideal scaling will reduce width and height. As transistors also
scales, wire lengths scales at same rate. Delay will actually remain
constant in this case. So, while transistor delay improves, wire
delay does not!! Not acceptable.
• Hence, “constant resistance scaling” technique is used.
• An important issue is that die area does not scale and hence there
are long “intermediate & global” wires where length does not scale.
• Will study wire scaling after wire parasitics in Module 2.
• Intermediate & global wires delay presents a serious bottleneck
that affects performance and power and limits the scaling.
• Significant research is conducted in low-k dielectrics, carbon-
nanotubes as wires, and 3D-integration.

D. Khalil ECE481 – M1 Lecture 2 28

28

Fall 2021 14
 Power & Power Density Limits
• Power is a key limit for any device. It affects temperature, heat
dissipation solution, battery life and size.
• It is until Intel’s Pentium 4 (P7) that power started to be a key
performance parameter. With the spread of mobile devices, power
is now the most important performance parameter.
• As transistors scales,
Pentium 4
power increases (non- Pentium 2,3
ideal scaling). In addition,
leakage increases
exponentially.
• Great effort is done
to improve transistor
to use less power and
have less leakage,
most important is SOI
and high-K metal gate.
D. Khalil ECE481 – M1 Lecture 2 29

29

Power & Power Density Limits

Power density also
Nuclear Reactor
presents an important
limit. It affects junction
temperature, leakage
power, heat dissipation
solution, and reliability.
High power density
dramatically increases
junction temperature, Hot Plate
which exponentially
increases leakage and
affects chip lifetime.
Expensive cooling
might be a solution.
Redesign for lower
density is cheaper.

D. Khalil ECE481 – M1 Lecture 2 30

30

Fall 2021 15
 Design Productivity Limits

• Market demands add more functionality and complexity in an

exponential trend. While transistors are scaling exponentially,
chip area is even growing.
• How are we going to design and verify and test chips with
several millions to a billion of transistors?! Extremely hard!
• Recent trends:
– Design reuse & porting
– Multi-cores
– IP vendors
– System-on-chip
– Co-simulation

D. Khalil ECE481 – M1 Lecture 2 31

31

References

• Rabaey, sections 1.1, 1.3.1, 3.5, 4.5.3 & 5.6

D. Khalil ECE481 – M1 Lecture 2 32

32

Fall 2021 16