Integrated Circuits

ECE481
Fall 2021
M3: Digital IC Design
Lecture 1
Implementation Approaches
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE481 – M3 Lecture 1 1

Outline

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-Based Array-Based

Standard Macro Pre-Diffused Pre-Wired Arrays

Cells Cells Arrays (FPGA's)

D. Khalil ECE481 – M3 Lecture 1 2

Fall 2021 1
 Custom Approach

• Handcrafting circuit and layout at the transistor level

• Difficult implementation due to minimal design automation
• Time consuming, high design cost, and long time-to-market
• Speed / power / area can be highly optimized
• Rare to use, typical cases are:
– Block reused many times (eg. library cells)
– Cost divided by a large volume (eg. Critical blocks in processor)
– Cost is not the prime criterion (eg. space applications)

D. Khalil ECE481 – M3 Lecture 1 3

Outline

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-Based Array-Based

Standard Macro Pre-Diffused Pre-Wired Arrays

Cells Cells Arrays (FPGA's)

D. Khalil ECE481 – M3 Lecture 1 4

Fall 2021 2
 Cell-Based Approach

• Design uses a library of predesigned cells

• Easy implementation due to the use of design automation
• Library development is expensive and time-consuming
(provided by the fab)
• Less design time, less cost, and shorter time-to-market
• Limited speed / power / area optimization
• Most popular implementation approach

D. Khalil ECE481 – M3 Lecture 1 5

Standard Cells

• Library of standard cells:

– All logic gates of different fan-in and fan-out
– Flip-flops and latches
– Can have more complex functions: decoders, encoders, comparators…
• Each cell must have:
– Circuit schematic, symbol, and physical layout
– Models: behavioral, Verilog/VHDL, detailed timing, power, routing
• Typically available from fabs and library vendors
• Standard cells are redesigned for every technology generation
• Complex cells can be created by compilers to enable design
flexibility and generates layout at compilation (easier to use and
more adaptive to technology changes)

D. Khalil ECE481 – M3 Lecture 1 6

Fall 2021 3
 Standard Cell Example

D. Khalil ECE481 – M3 Lecture 1 7

Macro Cells

• Cells of more complex circuits:

– Multiplier, memories, data-path, embedded processor, …
• Macro reuse should offset initial design cost
• Increasing popularity

• Hard Macro
– Given functionality and defined layout
– Can be parameterized (the generator is called module compiler)
– Can achieve dense layout
– Optimized and predictable timing, power and area performance
– Cannot export to other technologies
– Typically used for embedded memories and microprocessors

D. Khalil ECE481 – M3 Lecture 1 8

Fall 2021 4
 Macro Cells

• Soft Macro
– Given functionality but without specific layout
– Needs synthesis, placement, and routing
– Final layout can differ each time it is instantiated
– Timing, power, and area are only determined after generation
– Typically uses structural generators
– Generators also provide timing constraints for placement & routing
– Easily exported to other technologies
– More popular than hard macros

• IP (Intellectual Property) Macro

– Macros bought from IP provider
– Buyer typically cannot reverse engineer the IP (black-box)

D. Khalil ECE481 – M3 Lecture 1 9

Example: Hard Macro

• 25632 (or 8192 bit) SRAM

• Generated by a hard-macro module compiler
• Provides fixed layout and accurate timing and power

D. Khalil ECE481 – M3 Lecture 1 10

10

Fall 2021 5
 Example: Soft Macro

• 8x8 booth Multipliers By

Synopsys ModuleCompiler
• Standard-cell methodology
• Different aspect ratios, timing,
power with different synthesis
and layout

D. Khalil ECE481 – M3 Lecture 1 11

11

Outline

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-Based Array-Based

Standard Macro Pre-Diffused Pre-Wired Arrays

Cells Cells Arrays (FPGA's)

D. Khalil ECE481 – M3 Lecture 1 12

12

Fall 2021 6
 Pre-Diffused Array

• Also called “mask-programmable” gate arrays

• Wafers contain arrays of primitive cells with all fabrication steps
done except metal/via layers to achieve programmability
through metal/via masks
• Fast fabrication turnaround time (only metal/via layers)
• Low cost since high cost fabrication steps are shared
• One-time programmability only
• Less design time, less cost, and shorter time-to-market
• Limited speed / power / area optimization

D. Khalil ECE481 – M3 Lecture 1 13

13

Pre-Wired Arrays
• Early versions: PROM, PAL, and PLA
• Modern version: FPGA “field-programmable gate arrays”
• Chips are built with programmable logic and programmable
interconnects and achieve full programmability in the field
• No manufacturing steps after design at all
• Lower cost since all fabrication steps are shared
• Configuration (program) can be stored using different techniques:
– Fuse (one-time programmability only)
– Non-volatile EPROM (can be reprogrammed, keeps program indefinitely)
– Volatile RAM (can be reprogrammed, only keeps program while powered)
• Even less design time, less cost, and much shorter time-to-market
• Limited speed / power / area optimization

D. Khalil ECE481 – M3 Lecture 1 14

14

Fall 2021 7
 Programmable Logic
Cell-Based Look-up-table (LUT) Based
Programmable Logic Programmable Logic

Configuration
A B S F=
0 0 0 0
A 0 0 X 1 X Out
F 0 Y 1 Y
0 Y X XY Memory
B 1 X 0 Y XY
Y 0 X XY
Y 1 X X1 Y
S 1 0 X X
1 0 Y Y ln1 ln2
1 1 1 1
2-input LUT
2x1 MUX cell

D. Khalil ECE481 – M3 Lecture 1 15

15

Programmable Wiring

Mesh-Based Programmable Wiring

Switch Box

Connect Box

D. Khalil ECE481 – M3 Lecture 1 16

16

Fall 2021 8
 Modern FPGAs
• Modern FPGAs use high speed EG: Xilinx Virtex II Pro
FPGA fabric and embed important
hardware to offer competitive
performance/price to cell-based
implementation.
• Attractive for small volume and
low/medium performance:
– Off-the-shelf
– Low development cost/time
– Shortest time-to-market FPGA Fabric
– Ease of upgrade (reprogrammability) High-speed I/O
– Competitive performance Embedded memories
Embedded PowerPC

D. Khalil ECE481 – M3 Lecture 1 17

17

References

• Rabaey, chapter 8

D. Khalil ECE481 – M3 Lecture 1 18

18

Fall 2021 9