Integrated Circuits

ECE481
Fall 2021
M3: Digital IC Design
Lecture 3
VHDL Overview
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

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Outline
• Entity & Architecture
• Types & Objects
• Special Statements
• Examples

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 Entity
• Reflects external view of design.
• Associates a name to the design.
• Defines the I/O ports (external interface).
• Specifies mode of each port (i.e., direction of data flow).
• Specifies type of data moving through the ports.
• Specifies generics (parameters) of entity such as bus width,
delay, clock speed, etc. (not shown in example).
• Does not explain how the entity works.

Example: Entity of 1-bit latch

ENTITY latch IS
d q
PORT( d, clk: IN bit;
clk latch nq
q, nq: OUT bit);
END ENTITY latch;
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Architecture
• Architecture reflects internal view of design.
• Architecture explains how the design works or how it is constructed.
• Each entity could have one or more architecture, but each
architecture is associated with only one entity.
• Four different design representations:
– Behavioral (how design works).
– Structural (how design is constructed).
– Dataflow/RTL (register transfer level description).
– Mixed.

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 Behavioral Architecture
• Explains how design works.
‒ Contains CONCURRENT statements.
‒ Contains PROCESS statements.
‒ Statements inside a process are executed sequentially.
‒ Several processes in an architecture all run simultaneously.

Example: Behavioral architecture of 1-bit latch

ARCHITECTURE behav OF latch IS
BEGIN d q
p1: PROCESS (d, clk) IS clk latch nq
BEGIN
IF clk = ’1’ THEN
q <= d; nq <= NOT(d);
END IF;
END PROCESS p1;
END ARCHITECTURE behav;

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Structural Architecture
d[3] q[3]
latch
• Explains how design is built. (bit3)
nq[3]

‒ Use COMPONENTS and SIGNALS.

d[2] q[2]
Example: Structural architecture of 4-bit latch latch
nq[2]
ARCHITECTURE struct OF latch4 IS (bit2)
q[3:0]
COMPONENT latch IS d[3:0]
nq[3:0]
PORT(d, clk: IN bit; q, nq: OUT bit); d[1] q[1]
latch
END COMPONENT latch; nq[1]
(bit1)
COMPONENT and2 IS
PORT(a, b: IN bit; c: OUT bit); q[0]
d[0]
END COMPONENT and2; latch
clk and2 nq[0]
SIGNAL int_clk: bit; (bit0)
en (gate) int_clk
BEGIN
Bit3: latch PORT MAP (d(3), int_clk, q(3), nq(3));
Bit2: latch PORT MAP (d(2), int_clk, q(2), nq(2));
Bit1: latch PORT MAP (d(1), int_clk, q(1), nq(1));
Bit0: latch PORT MAP (d(0), int_clk, q(0), nq(0));
Gate: and2 PORT MAP (en, clk, int_clk);
END ARCHITECTURE struct;

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 Dataflow Architecture
• Explains how data stored in registers are calculated.
‒ Contains ASSIGNMENT statements.
‒ All assignments are performed concurrently.
‒ Operations at each clock cycle are explicitly defined.

Example: Dataflow architecture of half adder

ENTITY half_adder IS
PORT( a, b: IN bit;
s, c: OUT bit);
END ENTITY Half_adder;

ARCHITECTURE dataflow OF half_adder IS

BEGIN
s <= a XOR b;
c <= a AND b;
END ARCHITECTURE dataflow;
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Mixed Architecture
• Combine the previous three methods in one architecture.
Example: Mixed architecture of logic circuit
ENTITY circuit IS
PORT( a, b, x, y: IN bit; d: OUT bit);
END ENTITY circuit;
ARCHITECTURE mixed OF circuit IS
COMPONENT and2 IS
PORT( a, b: IN bit; c: OUT bit);
END COMPONENT and2;
SIGNAL c, z: bit;
BEGIN
gate: and2 PORT MAP (a, b, c);
d <= c XOR z;
op: PROCESS (x, y) IS
BEGIN
z <= x OR y;
END PROCESS op;
END ARCHITECTURE mixed;

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 Outline
• Entity & Architecture
• Types & Objects
• Special Statements
• Examples

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Types
• Scalar data types
– Number (integer & real)
For simulation only, converted to bits at synthesis.
– Character and String
– Enumeration (bit, three level, boolean)
• Composite data types
– Array
– Record

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 Numbers
• Integer does not have a decimal point.
• Real has a decimal point
• Can use other bases in the range 2–16.
2#111010# -- Base 2 integer
16#FD# -- Base 16 integer
2#0.10# -- Base 2 real (0.5)
8#0.4# -- Base 8 real (0.5)
12#0.6# -- Base 12 real (0.5)
2#1#E10 -- Base 2 integer
16#4#E2 -- Base 16 integer

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Characters & Strings

• Character is specified using single quotes, like ’0’, ’A’, and ’9’.
• String is specified using double quotes.
• Character string represents sequence of characters, like “string”.
• Bit string represents register value, like “00111001”.
• Bit string can use different base:
– b: binary (default)
– o: octal
– x: hexadecimal
For example, b “1111 0010 0001” ≡ x “F21”

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 Enumeration Types
• A type that only takes a value from a set of valid ones.
• Very useful in describing hardware.
TYPE bit IS (’0’ Forcing 0, ’1’ Forcing 1);
TYPE three_level IS (’0’ Forcing 0, ’1’ Forcing 1,’Z’ High Impedance);
TYPE boolean IS (false,true);
TYPE std_ulogic IS ( 'U‘ Uninitialized, 'X‘ Forcing Unknown, '0’ Forcing 0,
'1’ Forcing 1, 'Z’ High Impedance, 'W’ Weak Unknown, 'L’ Weak 0, 'H’ Weak 1,
'-’ Don't care);
TYPE unresolved_unsigned IS ARRAY (natural RANGE <>) OF std_ulogic;
Unsigned treats vector as positive binary number for arithmetic operations
TYPE unresolved_signed IS ARRAY (natural RANGE <>) OF std_ulogic;
Signed treats vector as positive/negative 2’s compliment binary number for
arithmetic operations
SUBTYPE std_logic IS RESOLVED std_ulogic;
SUBTYPE unsigned IS RESOLVED unresolved_unsigned; Best for hardware
representation
SUBTYPE signed IS RESOLVED unresolved_signed;
Function RESOLVED uses a resolution table to determine value in case of
multiple drivers

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Arrays
• Arrays consist of a collection of similar elements.
• Must be declared first.
TYPE var IS ARRAY (0 TO 7) OF integer;
• Then create objects.
CONSTANT settings: var :=(2,4,6,8,10,12,14,16);
• Arrays can be multidimensional.
TYPE mat4x2 IS ARRAY (1 TO 4, 1 TO 2) OF integer;
VARIABLE m4x2: mat4x2 := ((0,2), (1,3), (4,6), (5,7));
• Unconstrained array does not have size at declaration. It is specified
when each object is created.
TYPE vector IS ARRAY (integer RANGE <>) OF integer;
VARIABLE vec6: vector (2 DOWNTO -3) := (3,5,1,4,7,6);

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 Records
• Records consist of a collection of elements that are of different types.
• Must be declared first.
TYPE complex IS RECORD
r_part: real;
i_part: real;
END RECORD;
• Then create objects.
SIGNAL a, b, c: complex;
• Can read and assign elements inside the records
c.r_part <= a.r_part*b.r_part - a.i_part*b.i_part;
c.i_part <= a.r_part*b.i_part + a.i_part*b.r_part;

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Objects
• An object is something that can hold a value.
• Three types of objects in VHDL:
– Signals
– Variables
– Constants
• Each object has a type associated with the value it is holding.

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 Signals
• Signals cannot be declared inside processes.
• Only signals are used to transfer data across modules or processes.
• Two types:
– Port: pins of design declared in entity. Have directions (modes).
Initial values can be given to inputs, but they are ignored at synthesis.
– Internal: wires inside design declared in architecture. Have no direction.
• At start of simulation, signals get their initial values, if declared.
Otherwise, they get default value of their types.
• Signal assignment is not immediate and uses the operator <=
• Signal assignments take effect after specified amount of delay
representing the charge/discharge of parasitic capacitance.

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Port Modes
• Port modes are: IN, OUT, INOUT, and BUFFER.
• IN: Carries data in. Cannot be assigned.
• OUT: Carries data out. Cannot be read (used in RHS of <=).
• INOUT: Carries data in and out. Can be read and assigned.
• BUFFER: Carries data out. Can also be read within design (internal
feedback). They are not real and are not supported in synthesis.

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 Variables
• Can only be inside sequential bodies, like processes.
• Cannot be used for carrying information between processes.
• Declare as follows: VARIABLE memory size: integer;
VARIABLE delay: time := 5 ns;
VARIABLE temp: real;
VARIABLE reset: boolean := false;

• At start of simulation, variables get Example: Variables inside process

SIGNAL s: integer;
their initial values, if declared. p1: PROCESS IS
Otherwise, they get default value VARIABLE a,b,c,d: integer;
of their types. BEGIN
a := 2; b := 5; c := 3;
• Variable assignment is immediate
c := a * b;
and uses the operator := d := c + 2;
s <= d;
wait;
END PROCESS p1;

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Constants
• Use to:
– Specify size of complex objects (e.g., arrays or buses)
– Control loop counters
– Define timing parameters: delays, setup/hold times, switching times, etc.
• Declare as follows:
CONSTANT memory size: integer := 7;
CONSTANT delay: time := 5 ns;

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 Generics
• Special type of constants.
• Pass parameter values from the environment to a block (an
instance of an entity), such as: signal delay, load capacitance,
number of bits of a bus, number of bits of a register, etc.
• Must be declared in the system entity.
• Main difference between generics and constants is that generics
are used dynamically while constants are purely static. (Generic
can change without changing code. But, constant cannot change
without changing code.)
GENERIC(delay: time := 1 ns);
GENERIC(width: positive := 8);

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Objects Visibility
• Visibility of each object is determined by the place of declaration.
• A signal, a constant, a type, or a subtype declared or defined in a
package are visible in all design units which use this package.
• A port signal, a constant, a type, or a subtype declared or defined in
an entity are visible in all architectures assigned to this entity.
• A signal, a constant, a type, or a subtype declared or defined in an
architecture are visible only inside this architecture.
• A variable, a constant, a type, or a subtype declared or defined in a
process are visible only inside this process.

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 Identifiers
• Contain letters, decimals, and the underscore.
• Case insensitive.
• Start with a letter and fit in a single line.
• Cannot have underscore at the beginning or the end or two
successive underscores.
• A reserved keyword cannot be used as an identifier.

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Reserved Keywords
abs access after alias all and
architecture array assert attribute begin block
body buffer bus case component configuration
constant disconnect downto else elsif end
entity exit file for function generate
generic group guarded if impure in
inertial inout is label library linkage
literal loop map mod nand new
next nor not null of on
open or others out package port
postponed procedure process pure range record
register reject rem report return rol
ror select severity signal shared sla
sll sra srl subtype then to
transport type unaffected units until use
variable wait when while with xnor
xor

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 Comments
• Only line commenting is possible.
• Starts with double dashes (--) and terminates at end of line.
• Example: a <= b; -- Assign b to a

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Outline
• Entity & Architecture
• Types & Objects
• Special Statements
• Examples

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 Assignment Statements
• Logic can be described using concurrent & sequential statements
• Assignment statements are all concurrent (executed at the same
time) except inside a process.
• Not executed until any of its right hand side signals changes.

• Simple assignment
c <= a and b;
• Conditional assignment
d <= a XOR b WHEN c = ’0’ ELSE a OR b;
• Selection assignment
WITH state SELECT
d <= a WHEN reset,
b WHEN hold,
c WHEN OTHERS;

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WAIT Statements
• Three forms of WAIT statements:
– WAIT FOR time
Suspends process for specified amount of time.
Time can be specified explicitly or as an expression.
WAIT FOR 20 ns;
– WAIT UNTIL condition
Suspends process until a condition becomes true.
WAIT UNTIL clk = ‘1’;
– WAIT ON signal list
Suspends process until an event is detected on any of the signals.
WAIT ON a, b;
• Complex wait statement can contains a combination of the
different forms above.
WAIT ON a UNTIL clk = ‘1’;
WAIT UNTIL clk = ‘1’ FOR 20 ns;
• WAIT without an argument suspends process forever.

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 IF Statements
• Three forms of IF statements:
– Simple IF
IF a = b THEN c <= ‘1’;
– IF / ELSE
IF a = b THEN c <= ‘1’;
ELSE c <= ‘0’;
END IF;
– Nested IF
IF s = “00” THEN z <= a;
ELSIF s = “01” THEN z <= b;
ELSIF s = “10” THEN z <= c;
ELSE z <= d;
END IF;

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CASE Statements
• Better than nested IF statements

CASE address IS
WHEN 0 to 7 => decode <= "10";
WHEN 8 to 15 => decode <= "01";
WHEN 16 | 20 | 24 | 28 => decode <= "11";
WHEN OTHERS => NULL;
END CASE;

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 LOOP Statements
• Keeps looping until broken by EXIT
LOOP
WAIT UNTIL clk = ’1’;
count value := (count value + 1) MOD 16;
count <= count value;
END LOOP;
outer: LOOP
Inner: LOOP
WAIT UNTIL clk = ‘1’ or stop = ‘1’ or reset = ‘1’;
EXIT outer WHEN stop = ‘1’;
EXIT WHEN reset = ‘1’;
count_value := (count_value + 1) MOD 16;
count <= count_value;
END LOOP inner;
count_value := 0;
count <= count_value;
WAIT UNTIL reset = ‘0’;
END LOOP outer;
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FOR Statements
• Loops through specified values unless broken by EXIT

FOR i IN a’range LOOP

v := v XOR a(i);
END LOOP;

• Variable (i) does not need declaration and is undefined outside loop

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 WHILE Statements
• Loops until a condition is not true unless broken by EXIT

WHILE n <= a’high LOOP

x := a(n);
n := n + 1;
NEXT WHEN x = ’0’;
v := v + 1;
END LOOP;

• NEXT can be used with LOOP/FOR/WHILE statements to skip to

next iteration WHEN a condition is true

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Outline
• Entity & Architecture
• Types & Objects
• Special Statements
• Examples

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 Flip-Flop
• Positive edge-triggered D flip-flop with asynchronous clear and set.

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Counter
• n-bit binary up/down counter with synchronous clear and preset.

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 Finite State Machine (FSM)
0/0 0/1
• FSM for an odd parity checker. 1/1

even odd

reset 1/0 MEALY

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Finite State Machine (FSM)

0/0 0/1
• FSM for an odd parity checker. 1/1

even odd

reset 1/0 MEALY

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 ROM
• Squaring circuit using ROM.

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ROM
• Squaring circuit using ROM.

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 RAM
• Single-port RAM with n-bit address and m-bit word.

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RAM
• Single-port RAM with n-bit address and m-bit word.

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