SPURTHI B A

PHYSICAL DESIGN
-SPURTHI B A
spurthiba22@gmail.com

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WHAT IS PHYSICAL DESIGN?

• Physical Design[PD] is the process of converting RTL netlist into a
Layout i.e. manufacturable geometries [GDS].

• PD begins with a netlist, which is synthesized from RTL. The netlist

consists of gate-level specification like the cells, their
interconnections, locations etc. are all listed.

• GDS [Graphic Data Stream] is a binary format file which is the final
output of back end design. It contains labels, shapes ,layer
information, 2D and 3D layout geometric data. Fig. Physical design

• Physical Design aims at minimizing the area consumption, improving the performance by reducing
delays and making routing easier, reducing the power consumption of an IC.

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STEPS IN PHYSICAL DESIGN

i. IMPORT DESIGN OR NETLIST
• This step involves import of all libraries (Tech and Cell Library) , design constraints files (SDC,
UPF etc.), netlist and push-down Floorplan [provided by top-level PD].

• Sanity checks are performed to ensure inputs received from various team such as synthesis
team, library team etc. are correct. If this step is missed it can create problems at later stage.
ii. FLOORPLAN
• Floor planning is the process of placing Macros in
the core area, thereby determining the routing
areas between them. The objective of Floorplan is
to minimize the delay and area.

• Floorplan determines the size of die and creates

wire tracks for placement of standard cells. It
creates power straps and specifies Power
Ground(PG) connections. It also determines the
I/O pin/pad placement information.

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iii. PLACEMENT
• The process of placing the standard cells in
the Core area. Placement does not just place
the standard cell available in the synthesized
netlist, it also optimizes the design to achieve
timing, congestion, power.
Fig. Placement of Standard cells
iv. CLOCK TREE SYNTHESIS [CTS]
• The process of distributing clock signals to clock pins based on
physical information.
• CTS will ensure clock reaches various flip-flops at the same
time i.e. Clock tree is built to minimize Skew and Insertion
delay.
v. ROUTING
• The process of ctreating physical connections based on logical
connectivity.
• Signal pins are routed using metal layers and aims at meeting
the timing , clock skew, physical and timing DRC.
• Filler cells are added during this stage.
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vi. STATIC TIMING ANALYSIS [STA]

• STA checks for all the possible paths in the design for any
timing violations. Setup and Hold timing violations are being
checked.
• STA can be done only for RTL (Register Transfer Logic) designs.
• STA tool analyzes all paths from each and every start point to
end point, compares it against the timing specification that
exists for that path.
vii. PHYSICAL VERIFICATION AND SIGNOFF
• This stage consists of Signoff checks such as Design Rule Checks [DRC], Layout versus Schematic
[LVS], Electric Rule Checks [ERC], Resistance checks.All the above checks should be clean and send IP
for tapeout.
• DRC verifies spacing rules between metals, minimum width, via etc. LVS involves verifying the
schematic with Layout for functionality match. Once all these steps are done in final we stream out
the layout in the form of gds or OASIS file which is called tapeout.
CONCLUSION - In RTL to GDS flow, Physical Design is an important stage of converting Netlist to Layout that is
sent to the foundry for the fabrication of a chip.
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