Introduction to VLSI Design Flow

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design

System Specification:
• First step to Decide the specifications of the system.
• System specification  high level representation of the system.
• Specification factors Performance, functionality, and
Physical dimensions (size of the chip die),
Specification sheet
Fabrication technology. with
• Specification a collective data from market requirements, technology and finer technical details
economical viability.
• Feedback and expectation from potential customers
• End results  Specifications for the size, speed, power, and functionality of
the VLSI system.
• Once this done, the specification sheet along with finer technical details are
shared to next team.
System Level Design (Architectural Design)
• Overall specifications  Specifications of constituent
blocks + their intercommunication.
• How many blocks of what functionality and speed.
• Medium of Communicating of blocks.
• Exploration of the architectural alternatives (Low Power,
parallelism and pipelining).
• Rough estimation of speed throughput , area and power
for each architectural alternative
• Selection of an optimal architecture best suited for
application.
System Level Design
Architectural Design Algorithmic Design

Behavioral Hardware Behavioral Software

RTL, Gate Level Software Coding
Transistors, Layout Driver Design
 Behavioral Level Design (RTL)
• Main functional units identified.
• Area, power, and other parameters of each unit are estimated.
• The outcome of functional design is usually a timing diagram or
other relationships between units.
Complex processing design realized by
 Simple processing element and
Storing the intermediate results that can be used in subsequent
steps.
• RTL is expressed in a Hardware Description Language (HDL), such
as VHDL or Verilog.
• RTL can be used in simulation and verification.
• RTL can implement Boolean expressions, structure, behavior and
timing information.
Behavioral Level Design (RTL)
Logic Synthesis:
• Logic synthesis Converts RTL design to Gate level netlists.
With design Constraints by designer.(Area, timing and power).
• It produce an optimal network of hardware from a given library.

Logic Synthesis=Translation + Optimization +Mapping

HDL Source
Translate
Gate-level Simulation: Optimize and Map
Checks included are: functionality check, timing check and power analysis check.
Testability and Test Generation
• Testability is checked after Logic synthesis is over.
• Testability hardware is added to the design by DFT
tools.
• Automatic Test Pattern Generation (ATPG) for the design
is done
• It generates test data for testing fabricated chips for
• Testing is done post-manufacturing of IC.
Circuit Level Design:
• The purpose of circuit design is to develop a circuit
representation based on the logic design.
• The Boolean expressions are converted into a circuit
representation by taking into consideration the speed and
power requirements of the original design.
• Circuit Simulation is used to verify the correctness and
timing of each component.
• The circuit design is usually expressed in a detailed circuit
diagram. This diagram shows the circuit elements (cells,
macros, gates, transistors) and interconnection between
these elements.
• Tools used to manually enter such description are
called schematic capture tools.
• In many cases, a netlist can be created automatically from
logic (RTL) description by using logic synthesis tools.
Stick Level Design
• Transistor diagrams are translated to layout by using Stick diagram
• Stick diagram captures the layer information.
• Metric free notation provides platforms to design optimal layout.
• Layout are derived from stick diagram after applying Design Rules.
Physical Design
Floor Planning and Partitioning:
• It partitions the chip area into area segments.
• It allocates the logic blocks to be placed in each area segment.
Placement:
• Layouts are optimally spaced in each area.
• It minimizes the length of the interconnect.
• Designer can change the aspect ratio as per the area requirement.
Routing:
• Once placement has been routing is done.
• Interconnecting the blocks.
Parasitic Extraction:
• Interconnect capacitances are extracted from the layout.
• Influence on circuit delays are observed.
Placement Routing Tape-out Ready
Fabrication an Packaging
Fabrication:
• After layout and verification, the design is ready for fabrication--Tape Out.
• Layout data is converted into photo-lithographic masks, one for each layer.
• Masks identify spaces on the wafer, where certain materials need to be deposited, diffused or
even removed.
• Silicon crystals are grown and sliced to produce wafers.
• Several dozen masks may be used to complete the fabrication process.
Packaging, Testing and Debugging:
• Finally, the wafer is fabricated and diced into individual chips in a fabrication facility.
• Each chip is then packaged and tested to ensure that it meets all the design specifications and
that it functions properly.
• Chips used in Printed Circuit Boards (PCBs) are packaged in Dual In-line Package (DIP), Pin Grid
Array (PGA), Ball Grid Array (BGA), and Quad Flat Package (QFP).