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Floor Planning Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. [1]. It is also a process of positioning blocks or macros on the die.

Floor planning control parameters like aspect ratio, core utilization are defined as follows: Aspect Ratio= Horizontal Routing Resources / Vertical Routing Resources Core Utilization= Standard Cell Area / (Row Area + Channel Area) Total 4 metal layers are available for routing in used version of Astro. M0 and M3 are horizontal and M2 and M4 are vertical layers. Hence aspect ratio for SAMM is 1. Total number of cells =1645; total number of nets=1837 and number of ports (excluding 16 power pads) = 60. The figure depicting floor plan-die size (µm) of SAMM is shown beside.

Top Design Format (TDF) files provide Astro with special instructions for planning, placing, and routing the design. TDF files generally include pin and port information. Astro particularly uses the I/O definitions from the TDF file in the starting phase of the design flow. [1]. Corner cells are simply dummy cells which have ground and power layers. The TDF file used for SAMM is given below. The SAMM IC has total 80 I/O pads out of which 4 are dummy pads. Each side of the chip has 20 pads including 2 sets of power pads. Number of power pads required for SAMM is calculated in power planning section. Design is pad limited (pad area is more than cell area) and inline bonding (same I/O pad height) is used. Physical design (electronics) From Wikipedia, the free encyclopedia Jump to: navigation, search

will ensure the required functioning of the components.[1] Modern day Integrated Circuit (IC) design is split up into Front-end design using HDL's. Each of the phases mentioned above have Design Flows associated with them. At this step. Verification and Back-end Design or Physical Design. when manufactured in the corresponding layers of materials. This geometric representation is called integrated circuit layout. which include both design and verification and validation of the layout. physical design is a step in the standard design cycle which follows after the circuit design. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Physical Design flow uses the technology libraries that are provided by the . This step is usually split into several sub-steps. These Design Flows lay down the process and guide-lines/framework for that phase.Physical design steps within the IC design flow In integrated circuit design. circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which.

45nm. twin-well process. 22nm. 1μm .. 0. 65nm. the standard-cells used.35μm. are 2μm. 180nm.fabrication houses. 0. etc. 18nm. Technologies are commonly classified according to minimal feature size. etc..25μm. SOI process. Contents [hide]           1 Physical Design Flow 2 Design Netlist 3 Floorplanning 4 Partitioning 5 Placement 6 Clock tree synthesis 7 Routing 8 Physical Verification 9 GDSII Generation 10 References . 28nm. Standard sizes. 90nm. They may be also classified according to major manufacturing approaches: n-Well process.5μm . These technology files provide information regarding the type of Silicon wafer used. 130nm. in the order of miniaturization. the layout rules. 0.

VoltageStorm. Calibre) A more detailed Physical Design Flow is shown below. IC-Station. Some of the tools/software used in the back-end design are :     Cadence (SOC Encounter. There are detailed PD Flows that are used depending on the Tools used and the methodology/technology.Physical Design Flow A typical Back-end Flow is shown below The main steps in the flow are:         Design Netlist (after synthesis) Floorplanning Partitioning Placement Clock-tree Synthesis (CTS) Routing Physical Verification GDS II Generation These steps are just the basic. NanoRoute) Synopsys (Design Compiler) Magma (BlastFusion. Here you can see the exact steps and the tools used in each step outlined. . etc) Mentor Graphics (Olympus SoC.

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Done correctly . Synthesis converts the RTL design usually coded in VHDL or Verilog HDL to gate-level descriptions which the next set of tools can read/understand. Only after the netlist is verified for functionality and timing is it sent for the Physical Design flow. Floorplanning also decides the IO structure. memory. but also allows the sections of the design to be closer together. and the more routing resources that are used. less routing resources to be used. [edit] Floorplanning The first step in the Physical Design flow is Floorplanning. Floorplanning is the process of identifying structures that should be placed close together. required performance. This netlist contains information on the cells used. Floorplanning takes into account the macro's used in the design. Based on the area of the design and the hierarchy. A bad floorplan will lead to waste-age of die area and routing congestion. the slower the design will operate. and even faster and more consistent place and route times. area used. their interconnections. . and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip). aspect ratio of the design. a suitable floorplan is decided upon. Area and Speed are considered to be things that should be traded off against each other. faster end-to-end signal paths. In many design methodologies. The reason this is so is probably because there are limited routing resources. other IP cores and their placement needs. the routing possibilities and also the area of the entire design. This leads to shorter interconnect distances.[edit] Design Netlist A Netlist/Gate-level netlist is the end result of the Synthesis process. there are no negatives to floorplanning. Typical synthesis tools are:   Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS) Synopsys Design Compiler During the synthesis process. Optimizing for minimum area allows the design to use fewer resources. and the desire to have everything close to everything else. and other details. constraints are applied to ensure that the design meets the required functionality and speed (specifications).

Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Placement is performed in four optimization phases: 1. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. gate duplication. data-path sections benefit most from floorplanning. Subtractors. 2. cell moving.  Pre-placement optimization In placement optimization Post Placement Optimization (PPO) before clock tree synthesis (CTS) PPO after CTS. Optimization performs  . area recovery. and other non-structured logic can safely be left to the placer section of the place and route software. state machines. buffer insertion. This is done mainly to separate different functional blocks and also to make placement and routing easier. VR is the shortest Manhattan distance between two pins. Example structures that make up data paths are Adders. Placement uses RC values from Virtual Route (VR) to calculate timing. and Muxes. These modules are linked together in the main module called the TOP LEVEL module. [edit] Placement Before the start of placement optimization all Wire Load Models (WLM) are removed. Registers. This kind of partitioning is commonly referred to as Logical Partitioning. net splitting. Pre-placement Optimization optimizes the netlist before placement. 3. [edit] Partitioning Partitioning is a process of dividing the chip into small blocks. and random logic. cell bypassing. This can perform cell sizing.As a general rule. HFNs are collapsed. It can also downsize the cells. VR RCs are more accurate than WLM RCs. Counters. In-placement optimization re-optimizes the logic based on VR. 4.

Local skew achieves zero skew between two synchronous pins while considering logic relationship. Clock is not propagated before CTS as shown in the picture. There are two types of stop pins known as ignore pins and sync pins. Post placement optimization after CTS optimizes timing with propagated clock.  [edit] Clock tree synthesis Ideal clock before CTS The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. ‘Ignore’ pins are ignored for timing analysis. It can fix setup.sdc defined clock source and ends at stop pins of flop. It re does HFN synthesis. incremental timing and congestion driven placement. hold. . max trans/cap violations. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). If clock is divided then separate skew analysis is necessary. It tries to preserve clock skew.   Global skew achieves zero skew between two synchronous pins without considering logic relationship. After CTS hold slack should improve.iteration of setup fixing.  Post placement optimization before CTS performs netlist optimization with ideal clocks. It can do placement optimization based on global routing. Clock tree begins at .

. Global routing allocates routing resources that are used for connections. Detailed routing assigns routes to specific metal layers and routing tracks within the global routing resources. Rigidity is the term coined in Astro to indicate the relaxation of constraints. In post placement optimization after CTS hold slack is improved. Generally for 100k gates around 650 buffers are added. in placement and post placement optimization before CTS stages while neglecting hold slack. Clock After CTS In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. buffer relocation. CTO is achieved by buffer sizing. level adjustment and HFN synthesis. If clock is skewed intentionally to improve setup slack then it is known as useful skew. As a result of CTS lot of buffers are added. Higher the rigidity tighter is the constraints. global routing and detailed routing. We try to improve setup slack in preplacement. But shielding increases area by 12 to 15%. [edit] Routing There are two types of routing in the physical design process. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also. gate sizing.

Computers are used extensively to verify the correctness of a circuit design. and to generate the patterns used to test circuits once they have been fabricated. p. 2. ISBN 978-079238393 2. Kahng. Lienig. "Algorithms for VLSI Physical Design Automation". Sherwani. Springer (2011). J. J. 27. to lay out a circuit in a two-dimensional area. [edit] References 1.7. Kluwer (1998). 2. symbolic problem. I. Schematic (LVS) Has no antenna effects – Antenna Rule Checking Complies with all electrical requirements – Electrical Rule Checking (ERC). This includes verifying that the layout     Complies with all technology requirements – Design Rule Checking (DRC) Is consistent with the original netlist – Layout vs. Many of these problems involve either an exhaustive or a . Markov. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure". The solution that we develop incorporates a task scheduling algorithm. ^ A.1 Floorplan Background VLSI is a process used to build electronic components such as microprocessors and memory chips comprising millions of transistors. The layout is represented in the GDSII stream format that is sent to a semiconductor fabrication plant (fab). ^ N. ISBN 978-90-481-9590-9.7 Case Study: Floorplan Optimization Our second case study is an example of a highly irregular.[edit] Physical Verification Physical verification checks the correctness of the layout design.[2] [edit] GDSII Generation Once the design has been physically verified. optical-lithography masks are generated for manufacturing. The design of VLSI components is a computationally demanding process.

If we have N cells. The first stage of the VLSI design process typically produces a set of indivisible rectangular blocks called cells. Figure 2. Here. respectively. Although a cell has a fixed area. implementations are selected for the various cells with the goal of optimizing the total area. and acyclic means that there are no cycles. .) These graphs specify which cells are adjacent in the vertical and horizontal directions. we may wish to have a stove. and sink and may require that the stove be next to the refrigerator and the table next to the sink. (A polar graph is a directed acyclic graph with a single source and a single sink. then the total number of possible floorplan configurations is For example. interconnection information is used to determine the relative placements of these cells. In a third stage. This is an important part of the design process. refrigerator.27 shows a floorplan optimization problem with three cells and six possible configurations. In a second stage. we consider a layout problem. It is the third stage. VLSI floorplan optimization can be explained by analogy with the problem of designing a kitchen. In VLSI. and if cell has implementations. For example. conventionally called the and graphs.heuristically guided search of a large space of possible solutions. The term directed means that edges have a direction. table. Assume that we have decided on the components the kitchen is to contain (this action is stage 1 of the VLSI design process) and how these components are to be arranged (stage 2). with different models having different shapes but occupying the same floor area. and nodes (other than the source and sink) link cells that must have touching edges. for which we shall develop a parallel algorithm. it may have several possible implementations with different aspect ratios. Assume also that we can choose among several possible models for each of these components. floorplan optimization. Each arc denotes a cell. we select models so as make the best use of available floorspace. since the cost of a chip is usually dominated by its area. a floorplan is represented as a pair of polar graphs. In the floorplan optimization phase of our kitchen design.

have 1. In (a) are the alternative implementations. . and 2 implementations each. In (c) are the alternative floorplans that satisfy the constraints. respectively. and C1 and has an area of 130. In (b) are the and graphs. which state that B must be above C. The three cells A. B. and C. respectively. The lowest area floorplan is constructed from A. and that A must be to the left of B and C.Figure 2.27: A floorplan optimization problem. 3. each is labeled with its area. B0.

We can explore this search tree by using Algorithm 1. an implementation has been chosen for A. where area is defined as the product of the maximum horizontal and vertical extents. For example. this strategy is computationally infeasible for any but the smallest problems. This identification can be achieved by using a search algorithm to explore a search tree representing all possible configurations. This is the search tree corresponding to the problem illustrated in Figure 2.1 implements an exhaustive search that visits all nodes of the search tree. As shown in Figure 2. If so. Algorithm 1.1. we check whether the area of the partial configuration represented by that node is already greater than that of the best known solution. Before ``expanding'' a node (that is. At level 1. level i of this tree corresponds to the situation in which implementations have been chosen for i cells. The basic idea is to keep track of the best (lowest area) solution found so far. a problem with just 20 cells and 6 implementations per cell has a search space of nodes. The number in each tree node represents the area of the associated (partial) solution. The optimal configuration is (A.C1) and has area 130.B0. the three level 2 subtrees represent the choices for B and the level 3 leaves the choices for C. The problem then is to identify the configuration with the lowest area. with the path used to get to each leaf node reported as a solution. Level 0 is the root. the number of nodes explored can be reduced considerably by using a technique called branch-and-bound search. looking at its subtrees). Fortunately. we know that this node .28.Figure 2. An initial call search(root) causes the entire tree to be visited.28: Solving a floorplan optimization problem.27. Unfortunately.

and the subtree rooted at that node can be abandoned. assuming a depth-first and left-to-right search strategy.cannot yield a better solution.29: Branch-and-bound search. . or pruned (Figure 2. with the global variable A used to maintain a record of the best solution. Figure 2.29). This approach is specified as Algorithm 2. The subtree rooted at the second node on level 2 is pruned because the cost of this node (170) is greater than that of the cheapest solution already found (130).2. This figure shows the nodes actually explored in the example problem.

This is an interesting algorithm from a parallel computing perspective because of its irregular computational structure: the size and shape of the search tree that must be explored are not known ahead of time. the foreach in Algorithm 2. determines the structure of our parallel algorithm. the number of nodes explored in a typical 20-cell problem was reduced from to . efficient pruning is a difficult problem in a parallel environment and. Also.On a sequential computer. In this case. thereby giving a depth-first search algorithm that explores the tree depth-first and left-to-right. to a large extent. the fundamental operation to be performed in the floorplan optimization problem is branch-and-bound search. the need for pruning introduces a need both to manage the order in which the tree is explored and to acquire and propagate global knowledge . In one experiment reported in the literature.2 can examine each subtree in turn. In summary. As we shall see. pruning can reduce the number of nodes explored enormously.

branchand-bound search requires communication during execution in order to obtain and update the search bound A . However. and the number of processors is not too large. As noted earlier. Hence. In designing a communication structure to achieve this goal. The breadth-first exploration strategy is likely to decrease performance dramatically by delaying discovery of solution nodes and hence reducing the amount of pruning that occurs. In a parallel implementation of simple search (Algorithm 1. this means that new tasks will be created in a wavefront as the search progresses down the search tree. we use a fine-grained functional decomposition in which each search tree node is explored by a separate task. like Algorithm 1. This approach is simple and may even be efficient if communication is cheap. with which each task communicates when a solution is produced or a bound is required. the centralized approach is inherently nonscalable. We also need to address the issue of how to manage the A value. A quick review using the design checklist of Section 2.2. we need to trade off the benefits of frequent accesses to a centralized A value (which tends to reduce the amount of the search tree that must be explored) against communication costs. thereby leading to considerable redundant computation.1). Communication. One approach is to encapsulate responsibility for maintaining A in a centralized task. the maximum . Algorithm 2.3 reveals one deficiency in this design. In contrast.of computation state. has no obvious data structure to which we can apply domain decomposition techniques. 2. which must be accessed by all tasks. We must bear this issue in mind in subsequent design phases. evaluating a node is expensive.7.1. tasks can execute independently and need communicate only to report solutions.2 Floorplan Algorithm Design Partition. In these respects this problem is typical of many algorithms in symbolic (nonnumeric) computing. we assume that it is encapsulated in a single task with which other tasks will communicate. Notice that only tasks on the wavefront can execute concurrently. Since the manager must take a certain amount of time to process a request.2. For now. which will tend to be explored in a breadth-first fashion.

For example.30: Increasing granularity in a search problem. thereby creating a single task that evaluates search calls in sequence (Figure 2. Figure 2. then in the absence of pruning this technique creates tasks. This can be addressed using agglomeration. In the agglomeration phase of the design process we start to address practical issues relating to performance on target computers. and organize periodic exchanges of information between these submanagers. . we can partition the tree into subtrees. In the floorplan optimization problem.2 until we reach a specified depth in the tree. we agglomerate by switching to a sequential search at level two in the search tree. Agglomeration. In this figure. each with its own A submanager. and hence the maximum number of tasks that can execute concurrently. for example when a depth counter incremented on each recursive call is an integer multiple of a specified frequency parameter.30).2 to check A only periodically. Various refinements to this centralized scheme can be imagined.rate at which it can service requests. unless we believe that node evaluation is sufficiently expensive and task creation sufficiently cheap for the fine-grained algorithm to be efficient. the cost of creating a large number of fine-grained tasks. The first will be familiar from earlier problems. For example. If the switch to depth-first search is performed at depth D and cell has implementations. is bounded. we can create one task for each search call in the foreach statement of Algorithm 2. this means we must address two potential deficiencies of the finegrained algorithm that we have developed. that is. A task is created for each subtree rooted at level two. Or. We can modify Algorithm 2. submanagers can perform broadcast operations when they discover significantly better solutions. and then switch to a depth-first strategy.

Workers generate new search problems as they expand nodes. is initially to allocate the root node to a single worker. We can imagine a variety of alternative task-scheduling schemes for the floorplan optimization problem.The second potential deficiency is more subtle and relates to the scheduling of tasks rather than to their creation. An interesting variant of this approach combines elements of both redundant work and cyclic mapping to avoid the need for a central manager. we can assume that the tasks created to evaluate search tree nodes will execute either in the order that they are created or perhaps in a random order. each worker takes responsibility for a disjoint subset of the tasks generated. the data movement costs associated with this scheme are not high. Each worker can then enforce a local depth-first search strategy. Every worker expands the tree to depth D . and hence increase the amount of . more complex but also more general. we must implement a task-scheduling algorithm.'' Mapping. (This subset could be identified using a cyclic allocation strategy. Because this is really a mapping issue. pruning is effective. the search tree tends to be explored in a breadth-first fashion. One approach works in conjunction with the agglomeration scheme of Figure 2. for example. Furthermore. The solution to this problem is to control the order in which search tree nodes are explored. In the absence of explicit programmer control.30. Recall that when we use a task-scheduling strategy. A third strategy. This is undesirable because it tends to reduce the effectiveness of pruning and hence cause redundant computation. by exploring the search tree to depth D .) Only if a worker becomes idle does it ask other workers for tasks. we discuss it under ``Mapping. tasks (search tree nodes) become ``problems'' to be executed by one of a smaller number of ``worker'' tasks. Requests can be handled using a centralized or decentralized strategy. Load balancing is then achieved by causing workers with empty queues to request problems from other workers. A central manager first constructs a number of coarsegrained tasks. These tasks are then assigned to idle workers in a demand-driven manner. Then. because each processor executes one subtree at a time in a depth-first fashion. Because each task can be represented by a short vector representing the path taken to its position in the tree. and request new search problems each time they complete previously assigned problems. That is. typically one per processor. In either case.

For example. In particular.7. However. . that responsibility for maintaining A should be isolated from the rest of the computation. and that we can increase task granularity by switching from a parallel to a sequential evaluation strategy at a specified depth in the search tree. If we were concerned with parallelizing simple search. and perhaps less obvious. This method allows the worker to select problems far from the root for local execution and problems nearer to the root to hand to other workers.3 Floorplan Summary The parallel algorithm designed in this case study is certainly more complex. we introduce a task-scheduling algorithm so that we can pursue depth-first search on each processor while exposing higher-level search tree nodes for idle workers. Our choice of task scheduling strategy will depend on characteristics of our problem and target computer and can be determined by analysis and experiment. a central manager used for task scheduling can also maintain and distribute an up-todate search bound with each task. than that developed for the atmosphere model. Notice that the communication structures used for task scheduling can be integrated with those proposed earlier for maintaining A . In decentralized schemes. the need to support pruning requires that we proceed with further refinements. the design might be complete at this stage.pruning. the worker tasks that execute search problems can broadcast improved search bound values to other workers. It is clear from the start that functional decomposition techniques should be used to define tasks. by ordering its queue of search problems according to their depth in the tree. 2.

[1] Modern day Integrated Circuit (IC) design is split up into Front-end design using HDL's. the layout rules. These technology files provide information regarding the type of Silicon wafer used. These Design Flows lay down the process and guide-lines/framework for that phase. when manufactured in the corresponding layers of materials. which include both design and verification and validation of the layout. Physical Design flow uses the technology libraries that are provided by the fabrication houses. will ensure the required functioning of the components. the standard-cells used. circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which. the free encyclopedia Jump to: navigation. physical design is a step in the standard design cycle which follows after the circuit design. This geometric representation is called integrated circuit layout.Physical design (electronics) From Wikipedia. search Physical design steps within the IC design flow In integrated circuit design. Fabhouses fabricate designs onto silicon dies which are then packaged into ICs. Verification and Back-end Design or Physical Design. At this step. . This step is usually split into several sub-steps. etc. Each of the phases mentioned above have Design Flows associated with them. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses.

90nm.25μm. 0.. 130nm. 1μm . twin-well process. 0. 28nm. 65nm. are 2μm.. 180nm. 18nm. in the order of miniaturization. Contents [hide]           1 Physical Design Flow 2 Design Netlist 3 Floorplanning 4 Partitioning 5 Placement 6 Clock tree synthesis 7 Routing 8 Physical Verification 9 GDSII Generation 10 References [edit] Physical Design Flow A typical Back-end Flow is shown below The main steps in the flow are:    Design Netlist (after synthesis) Floorplanning Partitioning . They may be also classified according to major manufacturing approaches: n-Well process. 22nm.Technologies are commonly classified according to minimal feature size. 0. 45nm. SOI process. etc. Standard sizes.35μm.5μm .

Here you can see the exact steps and the tools used in each step outlined. IC-Station. . There are detailed PD Flows that are used depending on the Tools used and the methodology/technology. etc) Mentor Graphics (Olympus SoC. Calibre) A more detailed Physical Design Flow is shown below. NanoRoute) Synopsys (Design Compiler) Magma (BlastFusion. Some of the tools/software used in the back-end design are :     Cadence (SOC Encounter. VoltageStorm.     Placement Clock-tree Synthesis (CTS) Routing Physical Verification GDS II Generation These steps are just the basic.

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the slower the design will operate. Counters. other IP cores and their placement needs. As a general rule. Floorplanning takes into account the macro's used in the design. required performance. Typical synthesis tools are:   Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS) Synopsys Design Compiler During the synthesis process. faster end-to-end signal paths. and random logic. Done correctly . less routing resources to be used. Example structures that make up data paths are Adders. and Muxes. memory. Only after the netlist is verified for functionality and timing is it sent for the Physical Design flow. Floorplanning is the process of identifying structures that should be placed close together. and even faster and more consistent place and route times. a suitable floorplan is decided upon. their interconnections. Optimizing for minimum area allows the design to use fewer resources. Registers. but also allows the sections of the design to be closer together. and the desire to have everything close to everything else. Area and Speed are considered to be things that should be traded off against each other. there are no negatives to floorplanning. data-path sections benefit most from floorplanning. area used. and other details. Based on the area of the design and the hierarchy. the routing possibilities and also the area of the entire design. Subtractors. A bad floorplan will lead to waste-age of die area and routing congestion. This leads to shorter interconnect distances. and the more routing resources that are used. The reason this is so is probably because there are limited routing resources.[edit] Design Netlist A Netlist/Gate-level netlist is the end result of the Synthesis process. and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip). Floorplanning also decides the IO structure. This netlist contains information on the cells used. state machines. Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. and other non-structured logic can safely be left to the placer section of the place and route software. In many design methodologies. Synthesis converts the RTL design usually coded in VHDL or Verilog HDL to gate-level descriptions which the next set of tools can read/understand. . aspect ratio of the design. [edit] Floorplanning The first step in the Physical Design flow is Floorplanning. constraints are applied to ensure that the design meets the required functionality and speed (specifications).

4. buffer insertion.    . net splitting. This is done mainly to separate different functional blocks and also to make placement and routing easier. gate duplication. [edit] Placement Before the start of placement optimization all Wire Load Models (WLM) are removed. It can fix setup. VR RCs are more accurate than WLM RCs. cell bypassing. Post placement optimization before CTS performs netlist optimization with ideal clocks. cell moving. It can do placement optimization based on global routing. This can perform cell sizing. In-placement optimization re-optimizes the logic based on VR. Pre-placement Optimization optimizes the netlist before placement. area recovery. HFNs are collapsed. Optimization performs iteration of setup fixing. 2. incremental timing and congestion driven placement.  Pre-placement optimization In placement optimization Post Placement Optimization (PPO) before clock tree synthesis (CTS) PPO after CTS. Post placement optimization after CTS optimizes timing with propagated clock. 3.[edit] Partitioning Partitioning is a process of dividing the chip into small blocks. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into subblocks and then proceeds to design each module. This kind of partitioning is commonly referred to as Logical Partitioning. It tries to preserve clock skew. These modules are linked together in the main module called the TOP LEVEL module. It re does HFN synthesis. hold. VR is the shortest Manhattan distance between two pins. It can also downsize the cells. max trans/cap violations. Placement uses RC values from Virtual Route (VR) to calculate timing. Placement is performed in four optimization phases: 1.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. Local skew achieves zero skew between two synchronous pins while considering logic relationship.sdc defined clock source and ends at stop pins of flop. Higher the rigidity tighter is the constraints.[edit] Clock tree synthesis Ideal clock before CTS The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock tree begins at . . There are two types of stop pins known as ignore pins and sync pins. After CTS hold slack should improve. If clock is divided then separate skew analysis is necessary. Clock is not propagated before CTS as shown in the picture. ‘Ignore’ pins are ignored for timing analysis. If clock is skewed intentionally to improve setup slack then it is known as useful skew.    Global skew achieves zero skew between two synchronous pins without considering logic relationship. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis).

We try to improve setup slack in pre-placement. in placement and post placement optimization before CTS stages while neglecting hold slack. gate sizing. The layout is represented in the GDSII stream format that is sent to a semiconductor fabrication plant (fab). This includes verifying that the layout     Complies with all technology requirements – Design Rule Checking (DRC) Is consistent with the original netlist – Layout vs. [edit] Physical Verification Physical verification checks the correctness of the layout design. Schematic (LVS) Has no antenna effects – Antenna Rule Checking Complies with all electrical requirements – Electrical Rule Checking (ERC). optical-lithography masks are generated for manufacturing. CTO is achieved by buffer sizing. level adjustment and HFN synthesis. [edit] Routing There are two types of routing in the physical design process. As a result of CTS lot of buffers are added. Global routing allocates routing resources that are used for connections. In post placement optimization after CTS hold slack is improved. Generally for 100k gates around 650 buffers are added. global routing and detailed routing.[2] [edit] GDSII Generation Once the design has been physically verified. . Detailed routing assigns routes to specific metal layers and routing tracks within the global routing resources. But shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also.Clock After CTS In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. buffer relocation.

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