LVS

Sandeep Rawat

7/26/2018
Layout versus schematic (LVS)
It is a method of verifying that the layout of the design is functionally equivalent to the schematic (RTL) of the design.
Verification EDA tool performs LVS by taking a set of instructional code input, commonly known as LVS rule deck, in the following two
steps:
1. Extraction .
 Connectivity Extraction
 Device recognitions
 SEED promotion
2. Comparison.

The LVS rule deck guides the verification tool by providing the instructions and identifying files which are needed for LVS. Design inputs
needed for running LVS are as follows:

• Graphical database system (GDS) layout database of the design

• Netlist of the design  CDL for the design
• CDL of all IP’s and std cells
• HCELL file

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LVS flow:
• A LVS rule deck is a set of code, which is written in Standard
Verification Rule Format (SVRF) or TCL Verification Format
(TVF), which guides the verification tool to extract the devices
and connectivity of the integrated circuit. The LVS rule deck
contains the layer definitions for the identification of layers
used in the layout file and matches description of a layer to
the location of the layer in the GDS file. This helps in the
recognition of the electrically connected regions in the layout,
namely the nets. Nets are recognized from the layout shapes
through analysis between layout shapes in layers. LVS rule
deck also contains device structure definitions.

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Device Recognition

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Commonly faced LVS issues.

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• Case 1: Signal short
In this simple example, two signal nets w_adch_2_ and w_ccode_lv_8_ connected to two pins of ADC integrated in an SOC
gets shorted in a particular metal layer as shown in Figure 2. In the LVS report, the number of nets in the source is greater
than that in the layout:
Layout Source Component Type
------ ------ --------------
Nets: 11634 11635 *
If a short is present in a design, then the connectivity extractor will only extract the shorted nets as a single net in the
layout and will not be able to identify them as two different nets. In the LVS report, w_adch_2_ and w_ccode_lv_8_ nets
are shorted nets.
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
*******************************************************************************
1 Net w_adch_2_ w_adch_2_
w_ccode_lv_8_
-------------------------- --------------------------
--- Devices on source net w_adch_2_ ---
X0/X0(-300.235,-244.000) ADC xadc ADC
AD_ch_sel_lv[3]: n_788 AD_ch_sel_lv[3]: n_788
refcode_s_lv: n_5 refcode_s_lv: n_5
vss_sub: vss vss_sub: vss
ccode_lv[8]: w_adch_2_ ** w_adch_2_ **
** w_adch_2_ ** ccode_lv[8]: w_ccode_lv_8_

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Case 1: Signal short (Solution)
• Open Database in innovus and highlight both the nets
and check for Cross section point
• Create text on every 3-4um distance on net.

w_adch_2_

w_ccode_lv_8_

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Case 2: Short between a chip top level net and IPs internal net or Mismatch in pin location between lef and GDS pins

Sometimes due to absence of routing blockage in the Layout Exchange Format (LEF) of IP, a mismatch can occur between the LEF and GDS of IP or due
to mistake by the designer while doing custom routing, the top level route gets shorted to the internal net of an IP. This kind of short is very difficult to
locate .

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• Short between a chip top level net and IPs internal net (Solution)

 Use LVS BOX flow to debug such kind of issues

1. LVS BOX BUFF
2. LVS BOX BLACK BUFF
LVS BLACK BOX PORT <original-layer> <text-layer> <connect-layer>
connect-layer: polygons outside of cell.
original-layer: Original port layer

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Case 3: Short between different power/ground supplies at chip top
If a power ground short is present in a design, then LVS tool generate short.rpt. It is very easy to quickly identify the
presence of power ground short in the design but very difficult to find its location. If a design has power ground short,
then all of the standard cells, IPs (which are connected to the shorted power and ground supplies) will show LVS as
incorrect.

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Case 3: Short between different power/ground supplies at chip top (Solution and debug method)
LVS ISOLATE SHORTS
1. Use calibre RVE to isolate shorts layer by layer

2. Create VDD/VSS text on power/ground layer in every 9-10um using innovus and then run LVS

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Case 4: Short creation due to power/signal routes after merging two partitions

Hierarchical design approach is used while dealing with very large designs. Each partition is shorts clean individually. But sometimes shorts might occur
while merging the partitions due to lack of considerations about the partition integration issues. Appropriate blockages and precise partition
placement with respect to chip top level should be done in order to avoid these kind of shorts.

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 Open:
Open in a design occurs when polygons having same layout text are not connected to each other. Alternatively, when two nets having same net names are not connected to each other, it will cause an open. Presence of an open in a
design may result in floating gates which leads to short circuit power dissipation and may even result in chip failure. In large designs, it is always suggested to run the open finding utility of the place and route tool before running LVS to
detect the open in the early phase of the design cycle. Presence of open in a design after running LVS can be identified as shown in the following example.

In this simple example, net w_adch_2_ is connected from the Z pin of a instance of NAND3X38 cell to the AD_ch_sel_lv[2] pin of the ADC. But somehow the net is cut into two pieces and caused an open as shown in Figure

In the LVS report, the number of nets in the layout is greater than that in source:

Layout Source Component Type

------ ------ --------------
Ports: 310 310
Nets: 11636 11635 *

If an open is present in a design, then the connectivity extractor will extract the net as two different nets in the layout and will not be able to identify them as a single net. In the report, net 5065 is the opened portion of net w_adch_2_.

INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**********************************************************************************
1 Net w_adch_2_ w_adch_2_
5065
-------------------------- --------------------------
--- Devices on layout net w_adch_2_ ---
X9/X3093 NAND3X38 xmux NAND3X38
Z: w_adch_2_ Z: w_adch_2_
A: 9971 A: xadc_dig_prog_I/xmux/n_1521
B: 10906 B: xadc_dig_prog_I/xmux/n_1518
C: 2832 C: xadc_dig_prog_I/xmux/n_692
gnd: vss gnd: vss
vdd: vdd vdd: vdd

--- Devices on layout net 5065 ---

X0/X0 ADC
AD_ch_sel_lv[3]: n_788
AD_ch_sel_lv[2]: 5065
AD_ch_sel_lv[1]: w_adch_1_
AD_ch_sel_lv[0]: w_adch_0_
xadc ADC
AD_ch_sel_lv[3]: n_788
AD_ch_sel_lv[2]: w_adch_2_
AD_ch_sel_lv[1]: w_adch_1_
AD_ch_sel_lv[0]: w_adch_0_

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 Missing Port in source netlist

This kind of issue arises when a port is missing in the pin list of the sub-circuit definition in the source spice file. But
this port would be present in the netlist extracted from the layout. Because there would be an additional port in
layout so on comparison between the source spice netlist and layout extracted netlist, it would be flagged as port
missing. This issue can be identified as shown in the following LVS report.
INCORRECT PORTS
DISC# LAYOUT NAME SOURCE NAME
*************************************************************************************
1 vdd on net: vdd ** missing port **

DISC# LAYOUT NAME SOURCE NAME

*************************************************************************************
1 ** missing port ** vdd on net: vdd
Reason :
1.GDS is missing the port text or GDS having extra port text

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 Bit swapping for a bus
The pin order of a sub-circuit mentioned in the source spice netlist is different with that mentioned in spice netlist extracted from layout. This is a very common LVS issue in the bits of a bus. This issue
can be corrected by making the bus bit order same in both spice netlists. This is how this issue looks like in the LVS report:
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**********************************************************************************
1 Net w_adch_1_ w_adch_1_
-------------------------- --------------------------
--- Incorrect Devices On This Net ---
X0/X0 ADC xadc ADC
AD_ch_sel_lv[0]: w_adch_0_ ** w_adch_0_ **
AD_ch_sel_lv[1]: w_adch_1_ ** w_adch_1_ **
AD_ch_sel_lv[2]: w_adch_2_ ** w_adch_2_ **
** w_adch_2_ ** AD_ch_sel_lv[1]: w_adch_2_
** w_adch_1_ ** AD_ch_sel_lv[2]: w_adch_1_
** w_adch_0_ ** AD_ch_sel_lv[3]: w_adch_0_
2 Net w_adch_0_ w_adch_0_
-------------------------- --------------------------
--- Incorrect Devices On This Net ---
X0/X0 ADC_12bSAR_c55fg xadc ADC
AD_ch_sel_lv[0]: w_adch_0_ ** w_adch_0_ **
AD_ch_sel_lv[1]: w_adch_1_ ** w_adch_1_ **
AD_ch_sel_lv[2]: w_adch_2_ ** w_adch_2_ **
** w_adch_2_ ** AD_ch_sel_lv[1]: w_adch_2_
** w_adch_1_ ** AD_ch_sel_lv[2]: w_adch_1_
** w_adch_0_ ** AD_ch_sel_lv[3]: w_adch_0_
3 Net w_adch_2_ w_adch_2_
-------------------------- --------------------------
--- Incorrect Devices On This Net ---
X0/X0 ADC xadc ADC
AD_ch_sel_lv[0]: w_adch_0_ ** w_adch_0_ **
AD_ch_sel_lv[1]: w_adch_1_ ** w_adch_1_ **
AD_ch_sel_lv[2]: w_adch_2_ ** w_adch_2_ **
** w_adch_2_ ** AD_ch_sel_lv[1]: w_adch_2_
** w_adch_1_ ** AD_ch_sel_lv[2]: w_adch_1_
** w_adch_0_ ** AD_ch_sel_lv[3]: w_adch_0_
Solution:
1. Use bit-blasted netlist for V2lvs
2. Or use v2lvs -l “Verilog file of IP “ for netlist to CDL conversion.

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 IP’s GDS – CDL mismatch
This issue arises when correct version of spice netlist of an IP corresponding to a given GDS is
not picked up. There can be different number of instances, nets and device or their properties
in the IP’s spice netlist as compared to that in GDS. This kind of issue may also result in
property errors as illustrated below. It is always suggested to run LVS on the individual IPs as
well before running LVS on chip top. This issue can be easily corrected by taking the correct
version of CDL and GDS of the IP.
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
*****************************************************************************
********
1 X43/X57/M0 MN(NHVT) XITIME/XIREG/MM0<0> MN(nhvt)
l: ? (reduced instance) l: ? (reduced instance)
w: ? (reduced instance) w: ? (reduced instance)
2 X43/X57/M0 MN(NHVT) XITIME/XIREG/MM1<0> MN(nhvt)
l: ? (reduced instance) l: ? (reduced instance)
w: ? (reduced instance) w: ? (reduced instance)

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 Duplicate sub-circuit definition

If a sub-circuit in the physical spice netlist of an IP is also present in spice netlist

of another IP with the same sub-circuit name but different sub-circuit definition
then it may result in LVS failure. This is because the LVS algorithm would get
confuse which sub-circuit definition to choose from. After choosing one sub-
circuit definition out of two, there would be a LVS mismatch for the IP whose
sub-circuit definition is not picked up. One approach to resolve this issue is to
first make sure to perform uniquification of the sub-circuits present throughout
the design.

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Device mismatch

Case 1: No resistor extraction due to a metal segmenting shorting both the end
of the resistor

During extraction stage, there is a possibility that a metal segment shorts both the
ends of the resistor. Due to this short, the verification EDA tool may ignore this
resistor and consider it as a single net due to zero potential difference. This would
result in a missing device in the layout and hence LVS mismatch because the
resistor is present in the schematic but is not extracted in the layout netlist.

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Case 2: Device mismatch because of the fact that one decoupling capacitor was
exactly overlapping the other

While placing the decoupling capacitors, at times, the decoupling capacitors may
get placed one over the other, and the designer may not be able to interpret the
error/warning issued by the place and route tool. This will cause device mismatch
in the LVS verification due to the fact that during extraction, the tool may not be
able to extract one the overlapped instances and instead extracts only one
decoupling capacitor. The LVS result will show an instance count mismatch
because there is a missing decoupling capacitor in the GDS which is present in the
schematic. It is suggested to carefully look at the warnings/errors issued by the
place and route tool while placing decoupling capacitors.

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Case 3: IP missing from the netlist/gds
This issue is quite common in the SOC level LVS. This issue arises in the following
situations:
• Missing of any of the intellectual property block/standard cell GDS in the GDS
list while dumping GDS from the place and route tool.
• Sometimes, it is quite possible that the GDS of an IP block is partially complete
or not available presently.
• Due to missing GDS, LVS will flag missing instances in the layout and would result
in LVS mismatch. However, if we know apriority that a GDS is not available or
partially complete then we can avoid this kind of issue by using LVS BOX
statement which tells the verification tool to ignore the cell specified during the
LVS comparison. It is suggested to carefully look at the missing GDS
warnings/errors issued by the Place and Route tool while dumping the GDS. It is
a good practice to manually look in the GDS if all the IP’s GDS are present in the
SoC’s GDS to ensure proper merging of all the IP’s GDS.

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Case 4: Decoupling capacitors missing in source spice netlist

This situation arises if we mention the decoupling capacitors in the exclude cell list
while dumping PG netlist from the place and route tool. Due to this, the
decoupling capacitors would not be present in the source spice netlist. But, during
the extraction phase, the tool will recognize decoupling capacitors and would
mention them in the extracted layout netlist. This would flag LVS mismatch
because of the decoupling capacitors missing in the source spice netlist. It is
suggested to not to include the decoupling capacitors in the exclude cell list while
dumping PG netlist from place and route tool.

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• GLOBAL statements in the spice netlist of the IP block

The .GLOBAL statement provides a convenient means of communicating power

supplies and clocks throughout the netlist. GLOBAL statement is used to specify
nodes which are globally shared by all sub-circuits. It does not matter where this
statement appears in a netlist, the behavior is always the same. Since LVS is
comparing between layout and schematic, it is possible that there is no issue
with the power and ground supplies in the layout yet LVS is failing for all the
instances throughout the design. It may be because of the GLOBAL statement
specified in the physical netlist of one of the IPs used in the design. Due to the
global power supply, it may cause LVS failure when IP is integrated with the
SOC. It is always recommended to remove “.GLOBAL” statements or “!” from the
net names in the sub-circuits in the spice netlist of the IPs

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ERC Errors
1. ERC errors may relate to something the is an electrical fault, like no path to power or
ground within your layout. An example of this would be an NWELL which is not tied
off to VDD. This can happen if someone places an NWELL guard ring and forgets to
connect it to VDD.

-floating NWELL
-source and drain connected to power and ground
-floating gate
-floating DNWELL
-floating PWELL

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Soft-Connect

Soft-connects are very different however, this shows a connection between two
nets or grounds. An example of this would be two grounds connected together like
AVSS_analog and VSS_digital. Normally a soft-connect would show up if the nets
are connected through the SUBSTRATE. They should have been isolated via
DNWELL but for some reason they are not.

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 Soft-Connect

Temporary Solution: VIRTUAL CONNECT BIASNW

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VIRTUAL CONNECT CONCEPT:
WARNING: Open circuit - Same name on different nets:
Temporary Solution: VIRTUAL CONNECT NAME VSS
Bump

VSS VSS

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SEED:From my perspective "seeds" are an important part of "devices", and "promotion" is another way of saying "moved to a higher level". So with those two ideas together, "seed promotion" can be thought of as another way to describe a case where devices ended up at higher levels than expected.
A device in Calibre LVS is comprised of the seed shape (device body) and pins. For a mosfet the seed shape is typically the intersection of poly and diffusion. The pins are typically the source and drain (typically defined as diffusion NOT poly) and the gate pin (typically poly), and a bulk pin (typically a well, or substrate).

One of the most common causes of seed promotion is the calculation of certain properties that relate to the device, but aren't the same for every placement of that device. These properties might be relative to the seed shape or the pins associated with the seed shape. AS and AD are examples of properties that have caused
problems of this nature for years. If a source pin on a device, in a cell, has a certain AS property value that is different in one placement than another, then that device can't really be described accurately in both locations by using just one property value.

W and L have never been a problem because the W and L of a device in a cell is typically the same in every placement of that cell.

AS and AD are not always the same because the calculations of these values can change depending upon the relationship of cell placements with each other. for instance, a cell could be placed once, with no cells nearby, and the AS/AD would be calculated with a certain value. Then the same cell might be placed somewhere else as a
pair of mirrored cells where the source pins of the mosfets are shared. The AS/AD properties would be different in this case. The subckt representing the placed cell would no longer be able to reflect accurate values for AS and AD because the values would be different for different placements. the affected transistors would typically
be "promoted" up until the devices were present in some higher subckt (flattened in other words) so that each could now be represented with different AS/AD values reflecting the different placements of the same cell.

There is much more that we could discuss in the area of seed promotion but before I go further it might be good to stop and check to see if this is the type of information you were interested in.
SEED PROMOTION
If device pushdown cannot be completed, the final seed promotions are shown in the SEED
PROMOTIONS section of the run transcript. You will also see subcircuits in the extracted
netlist that contain the *.SEEDPROM statement, such as this example:
.SUBCKT cell_1 1 2 4
** N=4 EP=3 IP=0 FDC=1
*.SEEDPROM
M0 4 1 2 2 n L=5e-08 W=1.25e-07 $X=1025 $Y=850 $D=0
.ENDS
The subcircuit cell_1 has had an NMOS seed shape promoted out of it.

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