Project: Chiptop

Specifications
Design flow
1. Synthesis
2. Floorplan
3. Power Plan
4. IR Drop measurement
5. Placement
6. CTS
7. Routing
Input files for floorplan
Chiptop using ICC tool
1. Start the ICC tool using the following commands.

Command:
csh
icc_shell -gui

icc_shell gui_start
2. Load Libraries and
Symbol Libraries
using GUI
Setup Command:
•set search_path /home/jayesh.munjani/chip_top/chip90

•set link_library /home/jayesh.munjani/chip_top/chip90/models/saed90nm_max_pg.db

/home/jayesh.munjani/chip_top/chip90/models/saed90nm_min_pg.db
/home/jayesh.munjani/chip_top/chip90/models/saed90nm_typ_ht_pg.db /home/jayesh.munjani/chip_top/chip90/models/SRAM4X128.db

•set target_library {/home/jayesh.munjani/chip_top/chip90/models/saed90nm_max_pg.db

/home/jayesh.munjani/chip_top/chip90/models/saed90nm_min_pg.db
/home/jayesh.munjani/chip_top/chip90/models/saed90nm_typ_ht_pg.db /home/jayesh.munjani/chip_top/chip90/models/SRAM4X128.db}

•set symbol_library /home/jayesh.munjani/chip_top/chip90/ref/icons/saed90nm.sdb

Content of .db and .sdb files
.db file
•It is compiled version of .lib file in synopsys database format.

•.lib contains information about characteristics and functions of each cell provided
by vendor.

•Cell characteristics includes information such as cell names, pin names, technology,
area, delay arc, fanout etc.

.sdb file
•It contains definitions of graphic symbols that represent library cells in design
schematic and is provided by vendor.

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3. Setting TLU+

•Command:
•set_tlu_plus_files -max_tluplus
•/home/eitra.group3/Downloads/chiptop/
chip90/ref/tlup/
saed90nm_1p9m_1t_Cmax.tluplus
•-min_tluplus
/home/eitra.group3/Downloads/chiptop/chip
90/ref/tlup/saed90nm_1p9m_1t_Cmin.tluplu
s
•-tech2itf_map
/home/eitra.group3/Downloads/chiptop/chip
90/ref/tlup/tech2itf.map
Content of TLU files
• TLU+ files contain RC parasitics of metal per unit length for accurate RC extractions.

• It includes effect of width, space, temperature etc. on coefficients.

• MAP file maps the .itf and .tf files

4: Creating Project Library

Command:
create_mw_lib -technology
/home/eitra.group3/Downloads/chiptop/chip90/ref/tech/saed90nm.tf -mw_reference_library
{/home/eitra.group3/Downloads/chiptop/chip90/ref/saed90nm_fr
/home/eitra.group3/Downloads/chiptop/chip90/ref/sram4x128}
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Content of .tf and .ref file

 tf file
• .tf file contains information of metal layers and via.
• It contains layers and via names, type of metal, its pitch, width, spacing etc.
• It also contains geometry of cells, coordinates, its symmetry, size etc.

 Ref file
• Reference libraries contains physical information of standard, macro and pad cells,
which is necessary for placement and routing.
5. Opening Library

Command:
open_mw_lib /home/eitra.group3/Downloads/chiptop/chip90/chip_top_iter5

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6. Importing verilog file

Command:
read_verilog {/home/eitra.group3/Downloads/chiptop/chip90/results/compile.v}
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7. Import a Design
Floorplan
 Objectives of floorplan
• Minimize the area
• Minimize the timing
• Reduce wire length
• Reduce IR drop

 The output of floorplan is .def file.

Create Floorplan

Command:
create_floorplan -left_io2core 10 -bottom_io2core 10 -right_io2core 10 -top_io2core 10
set_object_fixed_edit [get_selection]
Placement

• Placement is the process of deciding physical location of standard cell in the block.
• Objectives of placement:
• Timing, power and area optimization
• Routable design
• Minimizing timing DRC

• Types of placement
• Congestion driven
• Timing driven
Placing a Macros in floor-planning

• Macros are placed based on fly lines.

• Group macros based on hierarchy.
• Macros should be placed around boundaries of core area leaving some space
between macros to core edge.
• Macros that are communicating with pins/ ports of core should be placed near to
core boundary.
• Avoid notches.
• Create halo around four sides of macro.
Placement of Macro
Power Plan
Step – 1: Deriving PG Connections

Command:
derive_pg_connection -power_net {VDD} -ground_net {VSS} -power_pin {VDD} -ground_pin
{VSS}
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Step – 2: Creating Rings

Command:
create_rectangular_rings -nets {VDD VSS} -left_segment_layer M8 -right_segment_layer M8
-bottom_segment_layer M9 -top_segment_layer M9
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Offset

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Step – 3: Setting power network constraints of straps

Command:
set_fp_rail_constraints -add_layer -layer M6 -direction vertical -max_strap 50 -min_strap 16
-max_width 4.5 -min_width 1.5 -spacing minimum -offset 10
set_fp_rail_constraints -add_layer -layer M7 -direction horizontal -max_strap 50 -min_strap 16
-max_width 4.5 -min_width 1.5 -spacing minimum -offset 10
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Step – 4: Creating virtual power pads

Command:
create_fp_virtual_pad -net VDD -point {9.875 1542.345}
create_fp_virtual_pad -net VDD -point {1543.180
1542.350}
create_fp_virtual_pad -net VDD -point {1543.195 9.790}
create_fp_virtual_pad -net VDD -point {10.045 9.825}
create_fp_virtual_pad -net VSS -point {9.465 1543.325}
create_fp_virtual_pad -net VSS -point {1543.640 8.915}
create_fp_virtual_pad -net VSS -point {9.605 1543.480}
create_fp_virtual_pad -net VSS -point {9.780 1543.275}

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Step – 5: Synthesizing power network

Command:
synthesize_fp_rail -nets {VDD VSS} -synthesize_power_plan -power_budget 1000
-honor_conn_view_layers {M6 M7 M8 M9}

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Power Report (report_power)
Area Utilization (get_utilization)
Placement of standard cells (create_fp_placement)
Congestion Report before Routing
Clock Tree Synthesis

• CTS is the process of connecting the clock to all clock pins of sequential circuits
by using inverters/buffers in order to balance the skew.
• All clock are driven by single clock source.
• The goal of CTS is to minimize the Skew and Latency.
• Constraints of clock tree synthesis are Latency, Skew Max Transition, Max
Capacitance Max Fan-out and list of buffers and inverters.
• Different types of clock tree routings are: H-tree, X-tree, Multi level clock tree,
Fish bone

• Command: clock_opt -only_cts

CTS output
CST report (report_clock_tree)
Routing

• Routing is the stage where the interconnections are made by determining the precise
paths for each nets.
• Objectives of routing: Skew requirement, Open/ short clean up, Routed path must
meet setup and hold timing margin, DRVs max capacitance / transition must be under
limit
• Types of routing: Global/ Trial, Track assignment, Detailed, Search and repair
• Constraints of routing: Setting limits on routing to specific regions, Setting the max
length for the routing wires, Blocking routing in specific region, Set preferred routing
direction.
report_constraints
 Thank You
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