RTL 2 GDS2

VLSI DESIGN FLOW: RTL TO
GDS
Lecture 1
Basic Concepts of Integrated Circuit: I
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Basic Concepts of Integrated Circuit
▪ Historical Perspective
▪ Structure
▪ Fabrication
▪ Designing vs. Fabrication
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Art of Copying …
Charles Babbage, On the Economy of Machinery and

Manufactures, Chapter 11, 1832
“…sources of excellence in the work produced by machinery

depend on a principle…., and is one upon which the
cheapness of the articles produced seems greatly to
depend.
The principle alluded to is that of COPYING, taken in its

most extensive sense.”
Source:
https://commons.wikimedia.org/wiki/Fi
le:Charles_Babbage_-_1860.jpg, See
page for author, Public domain, via
Wikimedia Commons

VLSI: An Historical Perspective

VLSI: An Historical Perspective
Electronic Circuit: Increasing Integration:
▪ Various active and passive components ▪ Small-Scale Integration, Large-Scale
➢ Connecting discrete components Integration, Very Large-Scale Integration
become expensive, time-consuming,
and unreliable. Moore’s Prediction:
▪ Number of components in an IC realized at
Integrated Circuit: minimum cost will double every year
▪ Monolithic silicon chips containing several ➢ Later revised to double every two year
components
➢ IC Technology Shrinking Transistors:
IC Technology: ▪ Moore’s prediction enabled by the shrinking
sizes of transistors
▪ Several key inventions and discoveries
➢ 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 16
➢ Photolithography nm ….
▪ Improving the speed, energy efficiency and
cost per transistor
▪ Designing an IC becomes more complicated
Structure of an Integrated
Circuit

Structure of Integrated Circuit (1)
▪ ICs are composed of multiple
layers
▪ Diffusion layer, implant layer,

metal layer etc.
▪ Bottom: devices
▪ Above devices: interconnect

layers of metal separated by
insulator
➢ Can be more than 10 such
metal layers
➢ Via is used to make
electrical connection
between different layers

Problem:
Connect points A1 to A2 and B1 to B2 using wires.
▪ Wires cannot go outside the rectangle shown.
▪ The wires are constrained to be in the plane containing

A1, A2, B1, B2.
What happens when the constraint of wires being in the

same plane is removed?

▪ Multiple layers are necessary to make connections between devices that would otherwise
short when connected in a single layer
▪ Layers defined by mask and fabricated using photolithography

Photolithography

Photolithography (1)
▪ Process of transferring geometric shapes that
are defined on a mask to the surface of a silicon
wafer
▪ Features marked on a glass plate with opaque

chrome thin films
➢ Also known as photomasks or reticles.
▪ For different layers of integrated circuits different

masks are used
▪ Photolithography is carried out for each layer

Photolithography (2)

Terminologies related to IC
Fabrication

Silicon Wafer and Ingots
Silicon Wafer:
▪ A silicon wafer is a thin slice of silicon that
serves as a substrate for an integrated circuit
▪ Currently, 300 𝑚𝑚 wafer are widely used
Silicon Ingots:
▪ Massive cylindrical single crystal of silicon
Source:
https://commons.wikimedia.org/wiki/File:I ▪ Silicon ingots are mostly prepared using
CC_2008_Poland_Silicon_Wafer_1_edit.png
FxJ, Public domain, via Wikimedia
Czochralski (CZ) process
Commons
➢ Pure seed crystal is pulled out from a
highly pure melted silicon at 1425℃
▪ A silicon wafer is sliced out from silicon ingots
Source: https://commons.wikimedia.org/wiki/File:Monokristalines_Silizium_f%C3%BCr_die_Waferherstellung.jpg,
German Wikipedia, original upload 7. Okt 2004 by Stahlkocher

Dies and Chips
Dies:
▪ Slices of silicon wafer containing the complete circuit are
called dies
▪ Hundreds of rectangular shaped integrated circuits are
fabricated on a single silicon wafer
▪ Dies are sliced out from silicon wafers after fabrication and
testing
Chips:
▪ After dies are sliced, they are encapsulated into a supporting
case for protection against physical and chemical damage.
▪ Packaged dies are generally known as chips

Designing vs. Fabrication

Designing vs. Fabrication
Designing:
▪ Determining the parameters and
composition of a circuit that can achieve
the desired functionality
Fabrication:
▪ It involves actual creation of integrated
circuit for a given design (layout of various
layers)

Semiconductor Foundries
Foundry:
▪ Semiconductor manufacturing plant where the fabrication of integrated circuits is done.
▪ Cost of setting-up and maintaining is very high.
▪ Sustainable only when the facilities of foundry are utilized close to their full potential

Semiconductor Industry: Business Model
Fabless Design Companies:
▪ Only designing, fabrication is outsourced
▪ Do not require to setup and maintain costly
foundries.
▪ Example: Qualcomm, Nvidia, etc.
Merchant Foundries:
▪ Only fabrication (for others)
▪ Draws business from many companies and
utilize foundry to full potential .
▪ Example: TSMC, UMC, GF, etc.
Integrated Device Manufacturers:
▪ Both designing and fabrication done in the same company
▪ Production is more efficient and cost-effective due to control over all the steps of the
process.
▪ Example: Intel, Samsung
Sharing Information between Design and Fabrication
Design and Fabrication:
▪ Related Task
▪ Share Information:
➢ Process Design Kit (PDK)
➢ Design (Layout)

References
▪ J. D. Plummer. “Silicon VLSI Technology: Fundamentals, Practice and Modeling”. Pearson
Education India, 2009.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

GDS
Lecture 2
Basic Concepts of Integrated Circuit: II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Basic Concepts of Integrated Circuit

▪ Types of Integrated Circuits
▪ Design Styles
▪ Economics
▪ Figures of Merit

Introduction: Some Basic
Concepts
Different VLSI
Design Flows

Different VLSI Design Flow
What is VLSI Design Flow?
▪ Methodology to design an IC such that it delivers the required functionality or behavior.
What decides VLSI Design Flow?
▪ The VLSI design flows depends on the type of integrated circuits:

▪ Scope of application
▪ Design Styles

Concepts
Types of Integrated
Circuits

Types of Integrated Circuit
Types of Integrated Circuit based on

scope of application
Application Specific General Purpose Integrated

Integrated Circuits (ASICs) Circuits

Types of Integrated Circuit
Application Specific General Purpose Integrated

Integrated Circuits (ASICs) Circuits
Functionality A chip designed to perform A chip designed to perform as a
as a particular end system wide range of end-system
Examples IC for digital camera, Microprocessors, memory, FPGA
audio/video processor,
security chip etc.
Programmability Not software programmable Usually software programmable
to perform a wide variety of to perform a wide variety of
different tasks different tasks
Volume of production Less More

Concepts
Types of Design
Styles

Types of Design Styles
Design Styles
Full-custom Standard-cell Gate-array FPGA based

design based design based design design
▪ FPGA: Field Programmable Gate Array

Full-custom design
▪ Layout of transistors and interconnects are design specific
▪ Huge design effort
▪ Very few designs are full-custom
▪ Analog mixed/signal designs
▪ High volume products such as microprocessors (some portion)
▪ Merit: design can be highly optimized

Standard-cell based design
▪ Standard Cells: simple cells such as AND,
NAND, flip-flop etc. that are optimally
designed and modeled in a library, fixed
height
▪ Macros: complex cells such as full-adder,

multiplier, memory etc.
▪ Allows high degree of automation
▪ Rows of standard cells with interconnection in between
▪ Custom blocks can also be embedded in a design
▪ Types, locations and interconnections of standard-cells are design specific

➢ All layers have different masks for different designs
Gate-array based design
▪ Transistors are predefined on an IC in the form of a gate array
▪ Base cell or primitive cells: smallest element that is repeated to form a gate array
▪ Designer define only the interconnection between transistors:

➢ Top-most layers of the masks are design specific
▪ Fixed functionality of the base cell may make implementing some functions such as memory
difficult or inefficient
▪ Some custom blocks can be embedded in the IC to obtain special functionality such as
memory, micro-controller etc.

FPGA based design
▪ IC hardware is fixed
▪ Designer obtain the desired functionality by

programming
➢ Programming changes the interconnections
between the elements of the circuits
▪ FPGA consist of array of logic blocks, I/O blocks and

routing channels
▪ Logic blocks can be programmed to perform different

functions such as AND, OR, adder etc.
▪ FPGA boards may also have embedded

microprocessors, analog components and blocks
performing special functions such as DSP block
▪ Xilinx (AMD), Altera (Intel)

Design Styles (Summary)
Full-custom Standard-Cell Gate-array based FPGA based

design based design design design
Description Design specific Pre-characterized Transistors Programming

customization at cells/macros predefined on logic blocks and
the level of instantiation and wafer, interconnect
transistors and interconnect interconnect
layout design specific design specific
Design effort Highest High Lower Lower
Custom Mask All All Top few layers None
Layers
Performance, Best Very Good Comparatively Comparatively
Power, Area Inferior Inferior

Introduction: Some Basic Concepts
Economics of
Integrated Circuit

Economics of Integrated Circuits: Components
Fixed Product Cost Variable Product Cost
▪ Cost of designing ▪ Cost of wafer

▪ Depends on size/complexity of design
▪ Cost of die
▪ Software tools ➢ Depends on size of die
➢ Yield
▪ Hardware
▪ Cost of masks
▪ Depends on number of layers
𝑇𝑜𝑡𝑎𝑙 𝑝𝑟𝑜𝑑𝑢𝑐𝑡 𝑐𝑜𝑠𝑡 = 𝐹𝑖𝑥𝑒𝑑 𝑝𝑟𝑜𝑑𝑢𝑐𝑡 𝑐𝑜𝑠𝑡 + 𝑉𝑎𝑟𝑖𝑎𝑏𝑙𝑒 𝑝𝑟𝑜𝑑𝑢𝑐𝑡 𝑐𝑜𝑠𝑡 × 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑃𝑟𝑜𝑑𝑢𝑐𝑡

Economics of Integrated Circuits: Comparison
Standard-cell FPGA-based design
based design
Fixed Cost High: designing Low: tools for

cost, tools, mask programming
Variable Cost Low: cost of die High: cost of die

(small die size, (large die size, low
higher yield) yield)
For small volume FPGA is better, for large volume standard-cell based design is better.

Concepts
Figures of Merit

Figures of Merit (FoMs) (1)
▪ How do we assess the “goodness” of an IC?
▪ Power, Performance, Area (PPA) Performance

measure
➢ Power: sum of static and dynamic
power consumed by an IC
➢ Performance: maximum frequency
of clock at which an IC will work
➢ Area: area of the die for an IC Integrated
▪ Example: (1 𝑊, 2.0 𝐺𝐻𝑧, 1 𝑚𝑚2) Circuit
Area Power

Figures of Merit (FoMs) (2)
▪ Other FOMs:
➢ Testability
➢ Reliability
➢ Schedule
▪ Figures of Merit are also called Quality of Result

(QoR) measure
▪ Improving one measure might adversely affect

other measure(s)
➢ Some measures might be required to be
traded-off
▪ Mathematical optimum FoM for a given design is rarely known or achieved
▪ Goal of a design flow is to find one of the feasible solutions with acceptable FoM

References
2023.
▪ M. J. S. Smith. “Application-Specific Integrated Circuits,” vol. 7. Addison-Wesley Reading,
MA, 1997.
soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

GDS
Lecture 3
Overview of VLSI Design Flow: I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Overview of VLSI Design Flow
▪ Design Flows
▪ Abstraction
▪ Pre-RTL Methodologies
▪ Hardware—software partitioning
VLSI Design Flow: RTL to GDS NPTEL 2023 S.Saurabh 2

VLSI Design Flow: A top-level
perspective

Chip Designing: Input and Output
How to tackle this problem?
Divide and conquer

VLSI Design Flow: Divide and Conquer
RTL: Register Transfer Level (Verilog, VHDL)
GDS: Graphical Database System (Layout)
Idea to RTL Flow: takes a high-level

idea/concept of a product and represents the
hardware portion of the implementation in
RTL.
RTL to GDS flow: takes an RTL through various
stages of logical and physical design steps
and finally represents the design as GDS.
GDS to Chip Processes: takes a GDS, prepares

masks for a given GDS and
fabricates/tests/packages chips

VLSI Design Flow: A top-level
perspective
Abstraction

Abstraction: Basic Concept
Abstraction: Level of Representation
Abstraction
▪ Hiding lower level details in a
description
Idea to RTL Very high System,
▪ As a design moves through VLSI design flow Behavior
flow:
➢ Details are added RTL to GDS Decreases RTL, Gate,
➢ Abstraction decreases flow subsequently Transistor,
down the flow Layout
GDS to No abstraction, Mask, Integrated
chip actual Circuit.
implementation

Why to Abstract?
Scope of Turn-around
Considerations for design tasks:
Optimization time
▪ Optimization: Choosing right
combination of design parameters Idea to RTL Flow Very High Low
to obtain desired QoR by trading-
off some of them.
▪ Turn-around Time: Time taken to RTL to GDS flow Decreases Increases

make changes in a design subsequently down subsequently
the flow down the
Impact of Abstraction: flow
▪ At higher level of abstraction large
number of solutions can be GDS to Chip No optimization. Very costly
analyzed in less amount of time. flow Some corrections. re-spin
▪ Result of optimization at the higher

level of abstraction is expected to
be better.
Abstraction: Illustration
Consider that the functionality is represented in two ways:
A. Logic Formula: 𝐹 = 𝐴 + 𝐵 ′
B. Using a standard cell delivering NOR function placed and connected on the layout.
Which of the above representations:

1. Has greater abstraction?
Ans: A
2. Smaller turn-around time in evaluating different implementations?
Ans: A
3. Greater accuracy in evaluation?
Ans: B

Pre-RTL Methodologies

System-level
Design

System-level Design: Top View
Evaluation of “idea”:
• Market requirement
• Financial viability
• Technical feasibility
Preparing specifications:
• Features (functionality)
• PPA
• Time to market (TTM)
HW—SW Partitioning:
• Identify components
• Determine which components to
implement in HW/SW
• HW/SW Development (separately)

• System Integration, Validation, Test
• Final Product
Hardware—software
Partitioning

Hardware—Software Partitioning: Motivation
Motivation: Exploit the merits of both hardware and software by choosing right combination of
hardware and software to implement a given function
Hardware Software
Performance High Low
Cost High Low
Risk due to bug High Low
Customization Low High
Development Time High Low
• Hardware: usually runs as parallel circuits and

can have very good PPA
➢ Can be implemented in full custom IC,
ASIC or FPGA
• Software: usually run sequentially on a
general purpose processor

Hardware/Software Partitioning: Example
Video Compression
• Algorithm can be divided in two main parts:
1. Computing Discrete Cosine Transform (DCT):
Performed multiple times, bottleneck
2. Frame Handling and other computation
• DCT • Frame Handling and other

➢ Hardware for computing DCT computation
➢ Can be computed using parallel ➢ Software on a general purpose
circuits microprocessor
➢ Several orders of magnitude faster ➢ Provides Flexibility
and more energy efficient
implementation in hardware

Hardware/Software Partitioning: Methodology(1)
Objective: Finding a minimum set of
functions that need to be implemented in
hardware to achieve the desired
performance
Inputs:
• Given algorithm that is implemented
entirely in software
➢ 𝑆 contains set of functions
implemented in software
• Acceptable performance 𝑃
• Parameter for the algorithm 𝑁: maximum
number of functions to be move to
hardware in each iteration
Output:
• Set of function 𝐻 to be implemented in
hardware (initially 𝐻 is empty)

Hardware/Software Partitioning: Methodology (2)
Measure performance: 𝐸𝑣𝑎𝑙𝑢𝑎𝑡𝑒(𝐻, 𝑆)
Profiling: Measures frequency or duration of
each function calls [𝑃𝑟𝑜𝑓𝑖𝑙𝑒(𝐻, 𝑆)]
In each iteration:
• Identify 𝑖 − 𝑡ℎ most severe bottleneck
function 𝑓𝑖
➢ Assume that 𝑓𝑖 is implemented in the
hardware
➢ Measure performance and check
whether target performance 𝑃 is met
• Moves maximum of N most critical
bottleneck functions to hardware
Termination criteria:
• Success: Performance target P is met
• Failure: No improvement even after moving
𝑁 functions to hardware
Hardware/Software Partitioning: Methodology (3)
• Takes a greedy approach

• Very simplistic
Challenges:
• Performance estimation
• Verification: hardware-software co-
simulation

References
2023.
inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S.Saurabh 19

GDS
Lecture 4
Overview of VLSI Design Flow: II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Functional description to RTL
▪ Reusing RTL
▪ Behavior Synthesis

Functional
Specification to RTL

Functional Specification
▪ Functional Specification can be made at a

higher level of abstraction
▪ Opens up implementation gap
▪ Need to convert to RTL

➢ Describes data flow from register to
register at various time instants or clock
cycle
➢ Carries timing information

RTL: General Structure
RTL: Register Transfer Level
▪ Modelling of circuit as flow of data (signal)

between registers
▪ RTL can also be referred to as “data flow”

description
▪ FSM generates control signals
▪ MUX passes the data based on control

signals
▪ Computation is done on the data path

Functional Specification to RTL
▪ Manual Coding: straight forward
▪ IP Assembly: reusing existing RTL
▪ Behaviour synthesis: automatic method of

generating RTL from high-level language

Reusing RTL

System-on-chip (SoC) Design Methodology
▪ Reusing RTL is especially popular in SoC (system-on-chip) design methodologies
System-on-chip (SoC)
▪ A complete system built on a single chip
▪ Composed of:
➢ Processors, hardware accelerators, memories, peripherals, analog components, and RF
devices connected using some structured communication links
➢ Embedded software
▪ Merits:
➢ Improves productivity
➢ Lowers cost
➢ Increases features

Intellectual Properties (IP)
Intellectual Properties (IP) Sharing of Information:

▪ Pre-designed and pre-verified sub- ▪ IPs contain information related to
systems or blocks structure, configurability, and interfaces
of the subsystem
▪ Can be developed internally or
purchased from IP vendors ▪ Challenge: how to package the
information?
Content:
▪ Hardware blocks: processor, memory,

interface, etc.
▪ Software: real-time operating system

(RTOS), device drivers, etc.
▪ Verification IPs (VIPs) eases verification

effort
Integration of IPs
Integration of IPs (IP Assembly) Configuring IPs
▪ Instantiating various IPs in an SoC and ▪ IPs can have configuration parameters such
making their connections as bus width, power modes, and
communication protocols
▪ IP assembly involves choosing the set of
Method configuration parameters
▪ Metadata: top-level IP models, bus ▪ Challenges: optimality and consistency
interfaces, ports, registers, and the
required configuration
➢ IP-XACT, SystemRDL, XML, or Communication Links
spreadsheet ▪ Ad-hoc bus-based
▪ Generator tools: produce an SoC-level ▪ Structured network on chip (NoC)
RTL with instantiated IPs.
➢ A generator tool can also produce a Verification Challenges
verification environment and low-
level software drivers. ▪ Huge functional space
▪ Software and Hardware

Behaviour Synthesis

Behavioral Synthesis: What?
Behavioral Synthesis
• Process of converting an
algorithm (not timed) to an
equivalent design in RTL (fully
timed) and satisfy the
specified constraints.
• Behavioral Synthesis is also called High-level Synthesis

Behavioral Synthesis : Cost Metrics (1)
• An untimed algorithm can be implemented in many different ways
• Different implementations can have different cost metrics
Cost Metrics:
• Area: number of circuit elements
• Latency: number of clock cycles required before results are available
• Maximum clock frequency: worst case combinational delay
• Power dissipation, Throughput, etc.

Behavioral Synthesis : Maximum Clock Frequency
Consider a synchronous circuit:
• Path: sequence of pins through which a signal can propagate
• Combinational path: a path that does not contain any sequential circuit element such as a
flip-flop
• Sequentially adjacent flip-flops: if the output of one flip-flop is fed as an input to the other
flip-flop through a combinational path
• Clock period should be

greater than the delay of the
critical path (𝑇𝑝 > 𝑑𝑚𝑎𝑥 )
• Maximum clock frequency
𝑓𝑚𝑎𝑥 < 1/𝑑𝑚𝑎𝑥
• Critical Path: the
combinational path that has
the largest delay in the circuit
Synchronous circuit: data launched must be captured by (approximately)
the sequentially adjacent flip-flop in the next clock cycle.

Behavioral Synthesis: Illustration (1)
• Algorithmic behavior: 𝑌 = 𝑎 + 𝑏 + 𝑐
• Cost metrics: circuit elements used, latency, and maximum delay of combination path.
Resources Resources
• 2 Adders (+) and 1 Register • 2 Adders (+) and 2 Registers
Latency Latency
• 1 clock cycle • 2 clock cycle
Worst Delay Worst Delay
• Delay of 2 Adders • Delay of 1 Adders

Behavioral Synthesis: Illustration (2)
• Adder is used in the first cycle to
compute (𝑌 = 𝑎 + 𝑏) and is used
in the next cycle to compute
(𝑌 = 𝑐 + 𝑌)
• Inputs to adders are controlled

by multiplexers
• Multiplexers get “𝑠𝑒𝑙𝑒𝑐𝑡” signal
from the control circuitry
Resources
• 1 Adders (+), 2 Register, 2
Multiplexer and 1 Inverter
Latency
• 2 clock cycle
Worst Delay
• Delay of 1 Adder + Multiplexer

Behavioral Synthesis: Evaluating Trade-offs
Area (𝝁𝒎𝟐 ) Delay (ns)
Let us compute the area, latency and critical path
Inverter 1 1 delay for three implementations.
Multiplexer 6 10
Adder 200 100
Flip-flop 12 0 RTL-1 RTL-2 RTL-3
Area 412 424 237
Latency 1 2 2
cycle cycle cycle
Delay 200 100 110

Behavioral Synthesis: Untimed to Timed Behavior
Algorithmic behavior: 𝑌 = 𝑎 + 𝑏 + 𝑐 RTL-1 RTL-2 RTL-3
Timed Behavior Area 412 424 237

• Three different “timed” implementation
illustrated Latency 1 cycle 2 cycle 2 cycle
• There can be several other Delay 200 100 110
implementations
• Behavior synthesis tool will choose the
best possible implementation satisfying Which RTL will be generated when:
the constraints • Area is to be minimized?
• Latency is to be minimized?
Trade offs • Clock Frequency is to be maximized?
• Behavior synthesis tool can trade off
one FoM to improve other FoM

Behavioral Synthesis: Merits and Challenges
Merits: Challenges:
• Automatic exploration of different • Physical design:
possible implementations ➢ Down the flow the QoR may degrade due
➢ More exhaustive than to other metrics such as congestion not
handwritten RTL taken into account
• Reduces design effort • Incremental changes:
• Less chance of introducing errors ➢ Lacks readability and debuggability
compared to handwritten RTL • Verification challenges

References
▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education,
1994.

2023.

GDS
Lecture 5
Overview of VLSI Design Flow: III
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ RTL to GDS Implementation

➢ Logic Synthesis

Overview of RTL to GDS Flow

VLSI Design Flow: RTL to GDS Flow

Logic Synthesis

RTL to GDS flow: Logic Synthesis
▪ Logic Synthesis: process by which RTL is converted to an equivalent circuit as
interconnection of logic gates
▪ RTL: given design (Verilog, VHDL)
▪ Library: standard cells and macros

(Liberty)
▪ Constraints: design goals, expected

timing behavior, environment (SDC)
▪ Netlist:
➢ Interconnection of logic gates
➢ Usually represented using
Verilog constructs or schematic

Logic Synthesis: Illustration
module top(a, b, clk, select, out);
input a, b, clk, select;

output out;
reg out;
wire y;
assign y = (select) ? b : a;
always @(posedge clk) module top(a, b, clk, select, out);

begin input a, b, clk, select;
out <= y; output out;
end wire y;
endmodule MUX2 INST1(.A(a), .B(b), .S(select), .Y(y));

DFF INST2(.D(y), .CP(clk), .Q(out));
endmodule

Logic Synthesis: Inputs and Outputs
Netlist
module …..
……. module top(a, b, clk, select, out);
endmodule
Logic input a, b, clk, select;
RTL Synthesis output out;
wire y;
library
cell(MUX2) MUX2 INST1(.A(a), .B(b), .S(select),
… Library .Y(y));
cell(DFF)
DFF INST2(.D(y), .CP(clk), .Q(out));
create_clock –name clock – endmodule

period 10 [get_ports clk]
set_input_delay ….
Constraints

Netlist Terminologies

Netlist Terminologies: Design and Ports
Design: Top level entity that represents the circuit. Example: MYDESIGN
Ports: The interfaces of the Design through which it communicates with the external world.
Example: in1, in2, CLK, out1, out2
▪ Input Ports: Signals going inside the design. Example: in1, in2, CLK
▪ Output Ports: Signals going outside from the design. Example: out1, out2

Netlist Terminologies: Cells
▪ Cells: basic entity delivering combinational or sequential function contained in libraries.

Examples: AN2, NOT, BUF, DFF
▪ Design is composed of multiple cells connected together

Netlist Terminologies: Instances
▪ Instances: cells when used inside a design are called instances.

Examples: I1, I2, I3, out1_reg, out2_reg.
▪ Using a cell in a design is called instantiation.
▪ The same cell can be instantiated multiple times.
Example: out1_reg and out2_reg are instances of the same cell DFF.

Netlist Terminologies: Pins
▪ Pin: An interface of a library cell or instance through which it communicates with the other
components is called a pin.
▪ Examples: A, B, Y are the pins of the cell AN2 and the instance I1
▪ Library Pin and Instance Pin (if we want to be explicit)
➢ Often apparent from the context
▪ Input Pin or Output Pin based on direction of flow of signal to cell/instance
Netlist Terminologies: Pin Names
▪ Instance pin name: typically specified as combination of instance name and pin name
separated by /
▪ Examples: I1/A, I1/B , out1_reg/Q

Netlist Terminologies: Nets
▪ Net: The wire that connects different instances and ports is a called net.
Examples.: N1, N2, N3, …N8

Logic Synthesis Tasks

Logic Synthesis Tasks: RTL Synthesis
RTL synthesis:
▪ Initial part of logic synthesis consisting of translating
an RTL to a netlist of generic logic gates
Generic Logic Gates

▪ A generic logic gate has a well-defined Boolean
function.
➢ AND, NAND, XOR, multiplexer, demultiplexer etc.
➢ Latches and flip-flops.
▪ Does not have a fixed transistor-level
implementation
➢ Does not have a well-defined area, delay, and
power attributes

Logic Synthesis Tasks: Logic Optimization
Logic Optimization:
▪ Optimizations on a generic gate netlist
▪ Typically area-driven

Logic Synthesis Tasks: Technology Mapping and
Optimization
Technology Mapping:
▪ Map a netlist consisting of generic logic gates to the
standard cells in the given technology library
▪ Obtain a netlist consisting of standard cells
Technology-dependent optimization:
▪ PPA can be estimated more accurately after
technology mapping
▪ Perform timing, area, and power optimizations over
netlist consisting of standard cells

References
1994.

2023.

GDS
Lecture 6
Overview of VLSI Design Flow: IV
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ RTL to GDS Implementation

➢ Physical Design

Physical Design

VLSI Design Flow: Physical Design
Physical Design: Process by which a design in the form of a netlist is converted to an
equivalent design in the form of layout or GDS (geometrical patterns of masks)
Netlist: input design (output of logic synthesis)

Library:
▪ Similar as in logic synthesis (Liberty)
▪ Abstract physical information of cells and
technology-specific information (LEF)
Constraints: design goals, expected timing

behavior, environment (similar as in logic synthesis)
(SDC)
Floorplan: designer’s intent about the physical

design (size and shape of die, predefined
placement information)

Physical Design: Major Tasks

Physical Design: Chip Planning
Chip Planning
▪ First step in physical design in

which we take major decisions
▪ Partitioning into subsystems or

blocks
▪ Arrange the blocks on the

chip/die
▪ Allocation of area for the

standard cells, macros,
memory
▪ Includes IO cell planning and

Power Planning

Physical Design: Placement
Placement
▪ Decides location of standard cells in the design
Objectives:
▪ Total wire length minimization: based on estimates
▪ Ensure timing is met: reduce the delay of the critical path
▪ Ensure no congestion
Physical Design: Clock Tree Synthesis
Clock Tree Synthesis (CTS)
▪ Decides topology of clock network and

how clock reaches each clocked
element
▪ CTS also performs wiring of clock

network (avoids detour since majority of
routing resources still unused)
Objectives:
▪ Ensure minimum skew: symmetric

structure
▪ Minimize power dissipation: clock

network consumes large fraction of total
power

Physical Design: Routing
Routing
▪ Creates wire layout for all the nets (other than clock
and power supply) satisfying certain constraints
▪ Objective: Use minimum wire-length, routing area, vias
▪ Very complicated process (too many nets and routing

constraints)
▪ It is typically done in two steps:

➢ Global Routing
➢ Detailed Routing

Physical Design: Global Routing
Global Routing
▪ Planning stage for routing
▪ Actual layout of wires not

created
▪ A routing plan for a given net is

created
▪ Entire routing region is partitioned

into rectangular tiles or global
bins
▪ Global routing assigns a set of

global bins that will be used for
making connections for a given
net

Physical Design: Detailed Routing
Detailed Routing
▪ Decides actual layout of each net

in the pre-assigned global bins
▪ The detailed router decides the

actual physical interconnections
of nets by:
▪ Allocating wires on each
metal layer
▪ Vias for switching between
metal layers

Physical Design: ECO and GDS Writing
Engineering Change Order (ECO)
▪ Make small final fixes in the

design
Write GDS
▪ Dump the layouts of each layer in

a GDS file

Physical Design: Optimizations
▪ Between each physical design task there are optimization steps:
➢ Small changes in the design to improve PPA
➢ Example of changes in the design:
✓ Buffer insertion on a given net
✓ Changes in the size of a given cell
✓ Changes in the placement of a given cell
✓ Changes in routing for a given net
▪ Incremental refinements to the design
▪ Changes are kept to be small and restricted to a small portions

of a design
➢ Do not create large disruptions in the design
➢ Design flow should converge

Physical Design: Iterative flow
▪ Physical design implementation tasks performed along with
verification tasks (timing, power, signal integrity, etc.)
▪ Physical design implementation should ensure design closure

(including timing closure) [all constraints are satisfied]
▪ Achieving design closure is challenging

➢ Design tasks do not have the full information and works
with estimates that can be wrong
▪ Physical design flow is typically iterative
▪ One task may require that previous tasks retract some design
decisions
➢ This creates loops in the physical design flow
▪ Achieving design closure with minimum number of iterations is

the goal of a physical design flow

References
2023.
▪ M. J. S. Smith. “Application-Specific Integrated Circuits,” vol. 7. Addison-Wesley Reading,
MA, 1997.

GDS
Lecture 7
Overview of VLSI Design Flow: V
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Verification
▪ Testing

Verification

VLSI Design Flow: Verification
Verification:
We perform verification to ensure that the design

works as per given functionality
▪ Verification is done multiple times throughout a

VLSI design flow
➢ Whenever design undergoes some changes,
verification must be done
➢ If verification fails remedial action can be
taken immediately
▪ Significant effort of VLSI design flow is spent on

verification

Functional Verification: Simulation
Is design (RTL) producing the same results as given in the specification?
Simulation: technique for ensuring the functional correctness of the RTL using test vectors
▪ Test vectors: sequence of zeroes/ones and the associated timing information
▪ Obtain the response for the

given RTL using a simulator
▪ Expected output is computed

using another model (C, C++,
MATLAB, etc.)
▪ Compare output response

and expected response
▪ Merits of simulation:-based verification: fast and versatile
▪ Demerit of simulation-base verification: incompleteness

Functional Verification: Model Checking
Is design (RTL) producing the same results as given in the specification?
Model checking: technique for ensuring the functional correctness of the RTL using formal
methods
▪ Formal methods: establish the proof Property Checking/Model Checking
of a given property using formal
mathematical tools such as ▪ Define properties that must be satisfied for a
deductions given specification
▪ Once we have proven a property ▪ Check whether properties are being satisfied in
mathematically, it is guaranteed to the implemented design RTL using formal
hold for all test stimuli. methods
Verification using formal methods: Example:
▪ Merits: completeness ▪ A traffic controller should generate signals such

that “Not more than one light should be green”
▪ Demerits: computationally difficult
▪ In a resource sharing environment: “Request for a
resource should be granted eventually”
Combinational Equivalence Checking
Will the RTL and the netlist generated by a logic
synthesis tool always produce the same (equivalent)
output?
Combinational equivalence checking (CEC):

establishes the functional equivalence of two models
using formal methods
▪ CEC required whenever non-trivial design changes

occur
▪ Carried out multiple times in a design flow

Static Timing Analysis
How to ensure the synchronicity of data
transfer between flip-flops in a synchronous
design?
Synchronicity: data launched by a flip-flop

gets captured in the sequentially adjacent
flip-flop in the next clock cycle
Static Timing Analysis (STA): ensures

deterministic synchronous timing behavior in
a circuit
▪ STA tools consider the worst-case

behavior (may be pessimistic), but will
always ensure the timing safety
▪ Carried out multiple times in a design flow

Physical Design Verification
How to ensure that the layout does not have manufacturing and connectivity issues and the
yield for a design remains high?
Physical verification:
▪ Check a set of rules during physical design before sending the layout to the foundry.
Design rule check (DRC):
▪ Rules are defined by the foundries and depend on the manufacturing technology
▪ All DRC violations must be fixed before sending it to the foundry for fabrication.
Electrical rule check (ERC):
▪ Rules are defined to ensure proper connectivity (for e.g.: no short circuit between distinct
signal lines).
Layout vs. schematic (LVS) check:
▪ Ensure that the layout is functionally equivalent to the original netlist

Rule Checking
Rules are some restrictions imposed on the design entity such as RTL, constraints, netlist,
layout etc. such that there are no issues in using that design entity downward in the VLSI
design flow
RTL: Ensure that RTL constructs used in

the design have no synthesis/simulation
issue down the flow
Constraints: Ensure that no conflicting

constraints are applied or any
constraint is missing
Netlist: Ensure that connectivity of
instances do not cause any issue down
the flow

Testing

VLSI Design Flow: Testing
▪ Verification : Ensures that GDS represents
the circuit correctly such that original
specification is met.
▪ Testing : Ensures that fabricated chip does

not have any manufacturing defect
Why testing is important during designing?
▪ RTL to GDS flow ensures that the chip that is

manufactured can be easily tested
(Testability)
▪ RTL to GDS flow ensures that if some defect

is found then the problem can be easily
diagnosed (debugged) and fixed

Manufacturing Defects: Origin
Defects
▪ Physical imperfections in a fabricated chip that are of permanent nature
Origin of defects
▪ Statistical deviations in material properties
▪ Finite tolerances in process parameters
▪ Airborne particles, and undesired chemicals
▪ Deviations in mask features
Large area and Spot defects

▪ Large area defects: simpler to eliminate
▪ Small area defects, of random nature
➢ Inevitably appears in chip fabrication
➢ Increases with increase in die area
Source:
https://commons.wikimedia.org/wiki/File:Clean_room.jpg ➢ Primary concern for testing
Uploaded by Duk 08:45, 16 Feb 2005 (UTC), Public domain, via
Wikimedia Commons

Manufacturing Defects: Manifestation
Manifestation of defects Faults:
▪ Short-circuit and open-circuit (functional failure)
▪ Testing focuses on
▪ Change in circuit parameters (such as delay) finding defects that
can be problematic for
a circuit behavior
▪ We model defect
(physical phenomenon)
using faults (circuit
model)
Distortions Inconsequential flaws

▪ Photolithography can produce distorted ▪ Deviations of a fabricated circuit from
features on a die the ideal, but not causing any
measurable change
▪ These are inevitable due to optical effects, etc.
▪ E.g.: if the size of particle is too small
▪ Needs to be handled using suitable techniques
▪ Testing does not detect these
▪ Testing does not detect these distortions inconsequential flaws
Quality of Process: Yield
Yield Factors affecting yield

▪ Fraction of die on a wafer that are good 1. Die area: when area increases, yield
or without any fatal manufacturing defect falls
▪ Usually expressed in percentage
▪ E.g.: If 300 dies are good out of 400 dies 2. Defect density: average number of
manufactured, then yield is: defects per unit of chip area
300 (depends on process)
= 400 × 100% = 75%
3. Clustering: distribution of defects on
the chip area
Yield and process technology
▪ Function of complexity and maturity of the

process
▪ Desirable > 50%, and often > 90%

Yield: Dependency on clustering
Which is better for yield, when defects are clustered (defects lying in small region) or
unclustered (same number of defects distributed over a larger region)?
Let us compute the yield in two

cases shown.
Unclustered defects
24
Yield=34 × 100 = 71%
Clustered defects
26
Yield=34 × 100 = 76%

Yield Model
Yield model:
▪ Required to estimate yield (and hence
profitability of IC manufacturing)
▪ Various models have been proposed with
varying accuracy and complexity
▪ We can assume that the probability of having

a defect in a given area increases linearly
with the number of defects already present in
that area
▪ One of the models
Yield 𝒀 = (𝟏 + 𝑨𝒅/𝜶)−𝜶 × 𝟏𝟎𝟎%
where
➢ 𝐴 is die area, Clustering parameter
➢ 𝑑 is defect density, • 0<𝛼<∞
➢ 𝛼 is the clustering parameter • 𝛼 → ∞ ⇒ 𝑤𝑒𝑎𝑘 𝑐𝑙𝑢𝑠𝑡𝑒𝑟𝑖𝑛𝑔

Testing Technique
Automatic Test Equipment (ATE)
▪ Consists of test head, probe cards with probe
needles
➢ Probe needles make contact with the test pads
on the design under test (DUT)
▪ Test program controls all operation
▪ Test Patterns are applied to the manufactured chip

▪ Actual responses are compared with the expected
response
▪ If comparison FAILs ⇒ The chip has some defect(s)
▪ The failed chip can be diagnosed to find the root

cause of the problem
▪ After diagnosis corrective measures can be taken to
reduce the defects
Fault Coverage and Defect Level
We measure the quality of testing using a ▪ Perceived quality of a chip strongly
parameter called fault coverage depends on: fault coverage and
yield
▪ Fault coverage: measures the ability of the set of ▪ Quality of chip is measured by a
test patterns to detect a class of faults quantity called defect level
# 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑎𝑏𝑙𝑒
▪ 𝐹𝑎𝑢𝑙𝑡 𝑐𝑜𝑣𝑒𝑟𝑎𝑔𝑒 = # 𝑓𝑎𝑢𝑙𝑡𝑠 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 Defect Level (DL)
▪ Fault coverage is a measure of quality of testing ▪ Ratio of chips that are “bad” or faulty
among the chips that have PASSED
the tests
▪ Practically achieving 100% fault coverage is ▪ Measured in parts per million (ppm)
challenging
▪ We try to attain more than 99% coverage ▪ DL is a measure of effectiveness of
▪ Some faulty products can reach the end user the tests (if test is fully effective,
because the employed set of test patterns may then 𝐷𝐿 = 0)
not cover/test all possible faults ▪ For commercial chips 𝐷𝐿 < 500 𝑝𝑝𝑚

Design For Test (DFT)

References
2023.

GDS
Lecture 8
Overview of VLSI Design Flow: VI
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 2

Post-GDS Processes

Mask Fabrication
▪ Mask is the replica of the patterns on a given layer of
the layout created on a substrate (glass) for transferring
pattern during photolithography
▪ We need to fabricate mask before fabricating the

corresponding IC
Mask fabrication typically involves following steps:

▪ Data preparation
▪ Mask writing and chemical processing
▪ Quality checks and adding protections
Source:
https://commons.wikimedia.org/wiki/File:Se
miconductor_photomask.jpg Peellden, CC BY-
SA 3.0
<https://creativecommons.org/licenses/by-
sa/3.0>, via Wikimedia Commons

Mask Writing, Quality Checks and Protection
Data preparation: Mask Writing
▪ Translate the layout-specified mask information to ▪ Start with chromium and photoresist
a format comprehended by a mask writing tool coated on glass or quartz (blank)
➢ Convert complicated polygons to simpler ▪ Pattern written on the blank by
rectangles and trapeziums (fracturing) exposing to LASER or electron beam
▪ Augment mask data to enhance resolution ▪ Photoresist is developed, chromium is
etched and then photoresist is
stripped
Quality checks and protection

▪ Inspect for defects by scanning its
surface and comparing it with the
reference image
▪ If a defect is beyond tolerance, we
repair it with the help of LASER
▪ Finally, protective cover called
pellicle is applied
VLSI Design Flow: S. Saurabh GDS to Chip: Overview 5
Resolution Enhancement Techniques (RET)
▪ If mask is patterned exactly as in GDS, then
features obtained on silicon is distorted
➢ Due to physical effects such as
diffraction
▪ Resolution Enhancement Techniques (RET):

mask is pre-compensated such that the
features obtained on the mask is same as
is desired
➢ Examples: Optical Proximity Correction
(OPC) and Double/Multi-Patterning

RET: Optical Proximity Correction (OPC)
▪ Printing mask patterns

smaller than the light
wavelength produces
distortions
▪ E.g.: rounding of corners

and line-end pullback.
Optical Proximity Correction

(OPC)
▪ Add appropriate serifs,
hammerheads, and mouse
bites to the mask
▪ Improves the resolution of
photolithography by
compensating errors due to
diffraction etc.
RET: Double- or Multiple-patterning
▪ Limited resolution of photolithography, pose problems in printing closely spaced features on
a die (leads to overlaps)
▪ We can solve the problem by increasing the spacing between features printed at a time
Double- or Multi-patterning
▪ Decompose a closely spaced layout into

two or more layouts (assign colors to
features)
▪ We use different masks and different

exposures for layout features of different
colors.
▪ Each exposure needs a lower resolution

due to decreased feature or pattern
density.

Wafer Fabrication and Die Testing
Wafer Fabrication ▪ Fabrication is done layer by layer
▪ Actual fabrication of design on the ➢ Front End Of the Line (FEOL) processes:
silicon wafer is carried out fabricate circuit elements such as
▪ Based on photolithography resistors, capacitors, diodes, and
transistors on the lower layers
▪ Consist of hundreds of individual
process steps ➢ Back End Of the Line (BEOL) processes:
make interconnections using metallic
layers at the top of the wafer
Die Testing
▪ Each die is tested and compared with the expected pattern
▪ Bad dies are marked and not packaged

Packaging
Packaging Various types and materials are
used for package
▪ We encapsulate a die in a supporting case known as a
package to form a chip. Dual in-line
package
Functions of a package (DIP)
Source:
https://commons.wi
1. Package provides pins for connecting to external kimedia.org/wiki/File
environment :Three_IC_circuit_chi
ps.JPG
➢ Characteristics of the package have great impact
on the delay of the signal entering/leaving the
chip Ball grid
➢ Needs to be carefully designed array (BGA)
2. Package allows dissipation of heat and must be

carefully designed
Source:
3. Package prevents from mechanical damage and https://commons.wikimedia.org/wiki/File:Solder_ball
_grid.jpg Janke at English Wikipedia, CC BY-SA 3.0
corrosion <https://creativecommons.org/licenses/by-sa/3.0>,
via Wikimedia Commons
Final Testing and Binning
Final Testing Finished/Tested chips
▪ Final testing is done to check if packaging is ▪ Can be sent to market directly for sale
fine ▪ Can be integrated with other chips to form
▪ Burn-in testing: infant mortality a product and then sent to market for sale
Binning
▪ Classification based on characteristics such
as maximum frequency and power dissipation
▪ Statistical variations in performance
▪ On-chip delay measurement circuitry
▪ Assign performance-based price points to
different bins.

References
2023.
▪ R. Seisyan. “Nanolithography in microelectronics: A review.” Technical Physics 56, no. 8
(2011), p. 1061.
inprotected.com VLSI Design Flow: S. Saurabh Overview of VLSI Design Flow 12

GDS
Lecture 12
RTL Synthesis- Part I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
RTL synthesis: ▪ Parsing, Elaboration

▪ Initial part of logic synthesis that translates
the Verilog code into netlist of generic logic ▪ Translation of some Verilog
gates Constructs to Circuit
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

RTL Synthesis
Tasks

RTL Synthesis: Parsing
▪ Reads the given RTL files and populates a data structure for further processing
▪ Lexical analysis:
keywords, identifiers
▪ Grammar/syntax
checking
▪ Syntax tree built:

➢ If grammar is
correct
➢ Hierarchical data
structure

RTL Synthesis: Elaboration (1)
▪ Checks whether the connections among RTL-specified components are legitimate.
➢ If legitimate, then make connections in the internal model; else report error
module leaf(d, clk, module Top(data, clk,

q); result);
input d, clk; input data, clk;
output q; output result;
... wire w1, w2;
endmodule
leaf I1(.d(data), .clk(clk),
module middle(D,
.q(w1));
CLK, Q);
input D, CLK; leaf I2(.d(w1), .clk(clk),
output Q;
.q(w2));
leaf F1(.d(D), middle I3(.D(w2),

.clk(CLK), .q(Q)); .Q(result), .CLK(clk));
endmodule
endmodule

▪ Elaboration needs to process parameterized modules
➢ Parameterized modules can have different interfaces for varying parameters.
▪ Creates separate modules with different interfaces for each distinct set of parameters
module counter(clk, rst,

count); module top(clk, rst, count1, count2,
parameter WIDTH=4; count3);
input clk, rst; input clk, rst;
output [WIDTH-1:0]count; output [15:0]count1;
reg [WIDTH-1:0]count; output [7:0]count2;
... output [3:0]count3;
endmodule
counter C1(clk, rst, count3);
counter #(8) C2(clk, rst, count2);
counter #(.WIDTH(16)) C3(clk, rst,
count1);
endmodule S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge

University Press, 2023.

RTL Synthesis
Verilog Constructs to
Circuit

Synthesizable and Non-synthesizable Constructs
▪ Some Verilog constructs cannot be Typically non-synthesizable:
synthesized into circuit elements
➢ They are helpful in other design tasks ▪ Delay specification:
such as functional verification ▪ out1 <= #12 a; treated as out1 <= a;
▪ A given RTL synthesis tool may not support ▪ initial block

all synthesizable Verilog constructs or
▪ fork, join, force, release
modeling styles.
➢ Need to be aware of the Verilog ▪ data types real and time
constructs supported by the synthesis
tool used in design implementation ▪ $display, $monitor, and other system
tasks

Assign Statement
▪ Combinational circuit elements inferred
module top(a, b, c, p, q, s, x, y, out1, out2, out3);

input a, b, c, p, q, s;
input [3:0]x, y;
output out1;
output [3:0]out2;
output out3;
assign out1 = (a & b) | c; // logic network

assign out2 = (x & y); // bitwise logic network
assign out3 = (s) ? q : p; // multiplexer
endmodule
S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
If-else Statement
▪ Multiplexer or selecting logic inferred
module top(a, b, s, out1);

input a, b, s;
output out1;
reg out1;
always @(*) begin

if (s==1’b0)
out1 = a;
else
out1 = b;
end
endmodule University Press, 2023.

Case Statement
▪ Multiplexer or selecting logic inferred module top(a, b, c, s,
out1);
module top(a, b, c, d, s, input a, b, c;
out1); input [1:0]s;
input a, b, c, d; output out1;
input [1:0]s; reg out1;
output out1;
reg out1; always @(*) begin
case (s)
always @(*) begin 2’b1?: out1 = a;
case (s) 2’b?1: out1 = b;
2’b00: out1 = a; default: out1=c;
2’b01: out1 = b; endcase
2’b10: out1 = c;
2’b11: out1 = d; end
default: out1=a;
endcase endmodule
end
S. Saurabh, “Introduction to VLSI Design
Flow”.Cambridge University Press, 2023. If-else-if with priority will be synthesized
endmodule similarly
Synthesis of Always Block
▪ Always block can be synthesized to combinational logic, latches, or flip-flop
▪ Depends on the sensitivity list and how are variables assigned with the always block

Always Block: Edge-sensitive
Flip-flops are inferred for module AsyncRstFlipFlop(d, clk, q, rst); module SyncRstFlipFlop(d, clk,
edge-sensitive always input d, clk, rst; q, rst);
blocks output q; input d, clk, rst;
reg q; output q;
reg q;
module DFlipFlop(d, clk, q); always @ ( posedge clk or
input d, clk; negedge rst) always @ ( posedge clk)
output q; if (rst == 1’b0) begin if (rst == 1’b0) begin
reg q; q <= 1’b0; q <= 1’b0;
end else begin end else begin
always @ ( posedge clk) q <= d; q <= d;
q <= d; end end
endmodule endmodule endmodule

Always Block: Blocking and Non-blocking
Assignments
Handling of blocking and non-blocking assignments in always block done differently (follows
the semantics of simulation).
module top1(in1, clk, out1); module top2(in1, clk, out1);
input in1, clk; input in1, clk;
output out1; output out1;
reg reg1, reg2, reg3, out1; reg reg1, reg2, reg3, out1;
always @ ( posedge clk) always @ ( posedge clk)

begin begin
reg1 = in1; reg1 <= in1;
reg2 = reg1; reg2 <= reg1;
reg3 = reg2; reg3 <= reg2;
out1 = reg3; out1 <= reg3;
end end
endmodule endmodule

Always Block: Level-sensitive
When always block does NOT module top(a, b, c, s, en, out1, out2);
contain edges in the sensitivity input a, b, c, s, en;
list, combinational circuit output out1, out2;
elements or latches are reg out1, out2;
inferred. always @(*) begin
if (s==1’b0)
▪ Combinational elements: out1 = a;
when the value of a variable else
is updated (refreshed) in out1 = b;
every possible path end
(conditional branches in the
code) within an always block always @(*) begin
if (en==1’b1)
out2 = c;
▪ Latch: if the variable retains end
its old value in some paths of endmodule
the always block
always @(*) begin
if (en==1’b1) out2 = c;
else out2 = out2;
end
Always Block: Unintentional Latch Inference
▪ Latches often get inferred due to incorrect module top(in1, out1);
modeling of a combinational block input [0:1]in1;
output out1;
▪ Example: inadvertently miss updating reg out1;
value in one of the branches of a case
statement. always @* begin
case(in1[0:1])
2’b00: out1 = 1’b0;
To avoid such problems: 2’b01: out1 = 1’b1;
2’b10: out1 = 1’b1;
▪ Use default case to cover all possible endcase
paths in a case statement. end
endmodule
▪ Set the output of a combinational logic to S. Saurabh, “Introduction to VLSI Design
Flow”.Cambridge University Press, 2023.
a default value at the beginning of the
always block

References
2023.
soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

GDS
Lecture 13
RTL Synthesis- Part II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Translation of some more Verilog

Constructs to Circuit
▪ Optimization

RTL Synthesis
Verilog Constructs to
Circuit

For Loop
▪ A for loop can model {carry, sum[0]}=a[0]+b[0]+cin;
{carry, sum[1]}=a[1]+b[1]+carry;
repeated logic module top(a, b, cin, sum, cout);
{carry, sum[2]}=a[2]+b[2]+carry;
structure input [3:0]a, b; input cin;
{cout, sum[3]}=a[3]+b[3]+carry;
output [3:0]sum; output cout;
▪ RTL synthesis tool can reg [3:0]sum; reg cout; reg carry;
unroll (expand) the reg [2:0]idx;
loop and instantiate always @(*) begin
circuit elements for carry = cin;
each iteration. for(idx=0; idx < 4; idx=idx+1)
➢ Must know the begin
number of {carry, sum[idx]} =
iterations during a[idx] + b[idx] + carry;
synthesis (not end
cout = carry;
during runtime) end
➢ Synthesizable for
a fixed number of endmodule
iterations

Functions
Function synthesizes to a combinational logic block with one output (scalar or vector).
module top(a, b, c, d, e, out1, out2);

input a, b, c, d, e;
output out1, out2;
reg out2;
function MAJOR3;
input A, B, C;
begin
MAJOR3 = (A&B)|(B&C)|(C&A);
end
endfunction
assign out1 = MAJOR3(a, b, c);
always @(*) begin

out2 = MAJOR3(c, d, e);
end
endmodule
Operators: Synthesis Tasks
Operators: Arithmetic and relational operators:

▪ Verilog supports various kinds of operators
➢ Logical: operators !, &&, || etc. ▪ Translate them to an internal
representation or data structure
➢ Bitwise operators: ~, !, |, ^, ~^ etc.
➢ Arithmetic operators: +, -, * / etc. ▪ Perform operator-level optimization
➢ Relational: <, >, == etc.
▪ Map operators to specific implementation
▪ Directly translate logical and bit-wise

operators to their corresponding logic gates
and optimize them subsequently.

RTL Synthesis
Resource/Timing
Optimization

Operators: Resource Sharing
if (sel == 1’b0)
z = a*b;
else
z = x*y;
Assume: a, b, x, y
are of 8 bits and
z is of 16 bits.
▪ Critical path can change
▪ Need to ensure that path through the select pin of the multiplexer does not violate timing
constraint

Operators: Speculation (Resource Unsharing)
if (sel == 1’b0)
y = b;
else
y = c;
z = a+y;
Assume: a, b, c, y
are of 8 bits.
▪ Assume that path through sel ▪ Decreases delay of the critical path
is critical. by employing more resources
▪ Performs addition irrespective of

the sum being needed
➢ speculation or eager
computation
RTL Synthesis
Implementation of
Arithmetic Function

Operators: Implementation
▪ Tools map arithmetic operators to predefined modules implementing these operators.
▪ A set of internal parameterized modules implementing arithmetic operators (+, −, *, /) and

relational operators (==, >, >=, <, <=).
▪ Instantiate these internal modules and choose the right set of parameters

Operators: Implementation Example
module top(a, b, c, d, sum, carry, comp);

input [7:0]a, b, c, d;
output [7:0]sum;
output carry, comp;
assign {carry,sum}= a + b;
assign comp = (c > d);
endmodule S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge

▪ Exact implementation tool-specific (logical

function same)
▪ Architecture switching in later stages

possible

RTL Synthesis
Compiler Optimizations

Compiler Optimizations
▪ Adapt compiler optimization techniques to RTL synthesis
▪ Can be applied to the parse tree or the internal model of the RTL
➢ Typically, optimizations applied in passes
▪ Gives significant gains for arithmetic operators

Compiler Optimizations: Examples
a = 8*8; a = 64;
Constant Propagation: replace expression with b = 2048;
b = (a*1024)/32;
constant when possible c = (b+32+b+32); c = 4160;
Common subexpression elimination: replace c = a*b;

identical subexpression in multiple expressions x = p+a*b; x = p+c;
y = q+a*b; y = q+c;
with a single variable if it reduces the cost, such
as area
Strength reduction: replace an expensive x = a*64; x = a<<6;

arithmetic operation with an equivalent less y = b/4; y = b>>2;
expensive operation z = c*17; z = (c<<4)+c;


References
1994.

2023.

GDS
Lecture 14
Logic Optimization: Part I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Two-level Combinational Logic

Optimization

Simplicity and beauty …
‘We ascribe beauty to that which is simple; which has
no superfluous parts; which exactly answers its end...’
—R. W. Emerson, The Conduct of Life, on “Beauty,”
1871
Source:
https://commons.wikimedia.org/wiki/File:Ralph_Waldo_Emer
son_by_Josiah_Johnson_Hawes_1857.jpg Josiah Johnson
Hawes, Public domain, via Wikimedia Commons
Logic Optimization
Two-level

Boolean Function: Definitions
Boolean variable: variable that can take one of the two values 0 or 1
Boolean function: function that takes Boolean variables as arguments and evaluates to 0 or 1.
Denoted as: 𝑦 = 𝑓(𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑁 ) where the variables {𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑁 } are Boolean variables.
Literal: a Boolean variable or its

Cube: a product of literals.
complement.
Example: 𝑥1𝑥2𝑥3, 𝑥1 𝑥2 ′, 𝑥3 ′ etc.
Example: 𝑥1 , 𝑥2 , 𝑥1 ′, 𝑥3 ′etc.
Consider a Boolean function of 𝑁 variables: Example: Consider a function of three variables

Minterm: the cube of 𝑁 literals in which 𝑥1, 𝑥2, 𝑥3:
each variable or its complement appears Minterms are: 𝑥1𝑥2𝑥3, 𝑥1′𝑥2𝑥3, 𝑥1′𝑥2′𝑥3 etc.
exactly once. Maxterms are (𝑥1 + 𝑥2 + 𝑥3) , (𝑥1 + 𝑥2′ + 𝑥3), etc.
Maxterm: the sum of 𝑁 literals in which
each variable or its complement appears
exactly once.

Boolean Function Representations
Truth Table: The row of a truth table shows the
value (0 or 1) assigned to each input variable 𝑦 = 𝑥1 𝑥2 + 𝑥2 𝑥3 + 𝑥3 𝑥1
𝑥1, 𝑥2, … , 𝑥𝑁 and its corresponding output value.
▪ Will contain 2𝑁 rows in the table. 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝑦 Minterm

0 0 0 0 𝑥1 ′𝑥2 ′𝑥3 ′
Minterm representation of a function:
0 0 1 0 𝑥1 ′𝑥2 ′𝑥3
▪ Each row of a truth table corresponds to a
0 1 0 0 𝑥1 ′𝑥2 𝑥3 ′
minterm.
➢ The minterm evaluates to 1 only for the 0 1 1 1 𝑥1 ′𝑥2 𝑥3
assignment of variables corresponding to 1 0 0 0 𝑥1 𝑥2 ′𝑥3 ′
that row in the truth table.
1 0 1 1 𝑥1 𝑥2 ′𝑥3
➢ For all other assignments of variables, the
minterm evaluates to 0 1 1 0 1 𝑥1 𝑥2 𝑥3 ′
0 1 1 1 𝑥1 𝑥2 𝑥3
▪ Sum of minterms: From the truth table, we take
the sum of only those minterms for which the
function evaluates to 1. 𝑦 = 𝑥1 ′𝑥2 𝑥3 + 𝑥1 𝑥2 ′𝑥3 +𝑥1 𝑥2 𝑥3 ′+𝑥1 𝑥2 𝑥3
Boolean Space and Hypercube: Definition
▪ Boolean functions of 𝑁 variables [𝑦 = 𝑓(𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑁 )]
spans an 𝑵 −dimensional Boolean space
▪ An 𝑁 −dimensional Boolean space can be represented

and visualized using an 𝑵 −dimensional Boolean
hypercube
Boolean Hypercube:
▪ Associate each variable with one dimension of the

hypercube.
▪ The corners of the hypercube represent binary-valued N-

dimensional vectors
➢ i-th entry in the vector corresponds to the value of
variable 𝑥𝑖 .
▪ A Boolean hypercube has 2𝑁 corners, representing 2𝑁

input combinations (or the associated minterms)
Boolean Function Representation: Hypercube
▪ Mark the corners in the Boolean hypercube with the value of the function for the
associated input combination.
𝑦 = 𝑥1 ′𝑥2 ′𝑥3 ′ + 𝑥1 ′𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3

Don’t Care (DC) Conditions
Don’t Care (DC) conditions:
▪ For some input combinations, the function 𝑦 = 𝑓(𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑁 ) may not be specified.
➢ These input combinations are known as don’t care
▪ DC conditions are denoted by X
▪ DC conditions are related to the input combinations that can never occur
➢ Example: If a function receives binary coded decimal (BCD) digits it cannot receive input
combinations {1010, 1011, ..., 1111}
▪ Can also be those input combinations for which the output is not observed
➢ Example: A function producing an output for a block that is in a sleep state

Incompletely-specified Boolean Function
Incompletely-specified Boolean function: Example:
▪ A Boolean function with DC conditions ▪ A function of three variables 𝑥1 ,𝑥2 , and 𝑥3 .
▪ Can represent using three sets: ON-set={010, 011},
➢ ON-set: input combinations for which OFF-set={000, 001, 100, 101}, and
the output is 1 DC-set={110, 111}.
➢ OFF-set: input combinations for which
the output is 0
➢ DC-set: input combinations for which
the output is X

Implicant of a Boolean Function
Implicant of a Boolean function:
▪ A cube whose corners are all in the ON-set or DC-

set of that function
Implicants:
▪ 𝑥1 ′𝑥2 𝑥3 ′
▪ 𝑥1 𝑥2
▪ 𝑥2 𝑥3 ′
▪ 𝑥2
Not an implicant:
▪ 𝑥1 ′𝑥3 ′
▪ 𝑥1 ′

Cover of a Boolean Function
Cover of a Boolean function:
▪ Set of implicants that includes

all its minterms
▪ The number of implicants in a

cover is known as the size of
the cover.
𝑦 = 𝑥1 ′𝑥2 𝑥3 ′ + 𝑥1 ′𝑥2 𝑥3 𝑦 = 𝑥1 ′𝑥2 𝑥3 ′ + 𝑥1 ′𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
▪ The cover with the minimum

size is known as the minimum
cover
𝑦 = 𝑥1 ′𝑥2 𝑦 = 𝑥2
Prime Implicant
Prime Implicant of a function:
▪ An implicant of a function that is not covered
by any other implicant of that function
▪ Also called prime (in short)
Prime Implicants:
▪ 𝑥2 : Yes
▪ 𝑥1 ′𝑥2 𝑥3 ′: No
▪ 𝑥1 𝑥2 : No

Essential Prime Implicant and Prime Cover
Essential prime implicant:
▪ If there is at least one minterm that is
covered by only that prime implicant.
▪ Prime implicants: 𝑥1 ′𝑥2 ′, 𝑥2 ′𝑥3 , 𝑥1 𝑥3 , and

𝑥1 𝑥2
▪ Essential primes: 𝑥1 ′𝑥2 ′ and 𝑥1 𝑥2
▪ Non-essential primes: 𝑥2 ′𝑥3 and 𝑥1 𝑥3
▪ Both 𝑥1 ′ and 𝑥2 ′𝑥3 are essential primes

Exact Two-level Logic Minimization
▪ Aim: To find the minimum cover.
▪ Reason: correlates with the circuit’s reduced hardware or reduced area.
▪ For simple problem: conventional techniques such as Boolean algebra-based manipulations

and Karnaugh maps.
▪ For problems with more than 20 variables: conventional techniques becomes too
complicated.
▪ In finding the minimum cover, we can reduce the search space by employing Quine’s
theorem

Quine’s Theorem
Prime cover: a cover that consists only of prime implicants
Quine’s Theorem:
▪ There exists a minimum cover consisting only of prime implicants (prime cover)
Proof:
▪ Consider a minimum cover that is not a prime cover.

➢ It implies that it contains some implicants that are not prime implicants.
➢ Can replace each non-prime implicant with a prime implicant that contains it.
➢ A new cover is obtained that consists of primes only and is of the same size.
➢ Hence, there exists a minimum cover that is a prime cover.
Application:
▪ We can focus on only prime cover for finding minimum cover.

Prime Implicant Table
How to find minimum cover among prime covers?
▪ By finding the set of prime implicants and building a prime implicant table.
How to build prime implicant table?
▪ Arrange the prime implicants in separate columns and the minterms in individual rows of the
prime implicant table.
▪ Fill entries in the table: If a given prime (column) covers a given minterm (row), then the
corresponding entry is made 1, else it is made 0.

Prime Implicant Table: Illustration
Prime Implicants
Minterms 𝑥1 ′𝑥2 ′ 𝑥2 ′𝑥3 𝑥1 𝑥3 𝑥1 𝑥2
𝑥1 ′𝑥2 ′𝑥3 ′(000) 1 0 0 0
𝑥1 ′𝑥2 ′𝑥3 (001) 1 1 0 0
𝑥1 𝑥2 ′𝑥3 (101) 0 1 1 0
𝑥1 𝑥2 𝑥3 ′(110) 0 0 0 1
𝑥1 𝑥2 𝑥3 (111) 0 0 1 1
How to find minimum cover using prime

Simplification:
implicant table?
▪ Identify essential primes: (𝑥1 ′𝑥2 ′ and 𝑥1 𝑥2 )
▪ Find the minimum set of columns that
covers all the rows in the prime implicant ▪ Work on remaining minterms [𝑥1 𝑥2 ′𝑥3 (101)]:
table. cover either using 𝑥2 ′𝑥3 or 𝑥1 𝑥3 ]
▪ Solve set covering problem (can grow ▪ Efficient reduction and covering algorithms
exponentially with the number of variables)
Heuristic Minimizer: Basics
For large problems we prefer heuristic minimizer over exact minimization.
▪ Heuristic minimizers are faster for large problem sizes.
▪ We often do not need the exact minimum cover.

➢ Any solution that can be found quickly and is near-optimal is acceptable.
Minimal Cover:
▪ A minimal cover satisfies certain local minimum cover property rather than the global
minimum property.
▪ For example, a cover in which no implicant is contained in any other implicant of the cover.
➢ Minimal with respect to single-implicant containment.
▪ The size of a minimal cover can be more than the size of the minimum cover.

Heuristic Minimizer: Approach
Approach:
▪ Starts with an initial cover and iteratively improves the solution by applying some operators
on it.
▪ The iteration terminates when the algorithm can no longer improve the solution.
Operators:
▪ Expand: expands a non-prime implicant to make it prime (removes implicants covered by
the expanded implicant)
▪ Reduce: replaces an implicant with a reduced implicant (covering fewer minterms) such that
the function is still covered.
▪ Reshape: operates on a pair of implicants (expands one implicant and reduces others such
that the function is still covered).
▪ Irredundant: makes a cover irredundant
➢ Cover in which, if we remove any implicant, then it will be no more a cover.

Heuristic Minimizer: Illustration
▪ Can carry irredundant

operation at the end of
iterations
▪ Not guaranteed to be
minimum
▪ ESPRESSO two-level
minimizer: practically very
efficient
References
1994.

2023.
inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

GDS
Lecture 9
Hardware Modeling: Introduction to Verilog-I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Features of Hardware Description Languages (HDLs)
▪ Language constructs of Verilog

Hardware Description Languages
(HDL)

HDL: Distinct Features (1)
▪ Several features that are similar to programming
languages such as C, C++
▪ Additional features in HDL to model hardware easily and

realistically
Concurrency
▪ Computation can be done in parallel in hardware
▪ HDL must support syntax/semantics to distinguish
parallel and sequential operations
Notion of Time
▪ Describe behavior of circuit with respect to time
▪ Concurrent/sequential operations
▪ Ability to create waveform (periodic signal)

HDL: Distinct Features (2)
Electrical Characteristics
▪ Tristate
▪ Driver Strength
Bit-true data types

▪ Behaviour of buses and how individual bits
behave

HDLs : Verilog and VHDL
▪ Two common HDLs are: Verilog and VHDL
Verilog: VHDL: VHSIC Hardware Description Language

▪ Created in 1983-84 at Gateway Design ▪ VHSIC: Very High Speed Integrated
Automation Circuit
▪ Verilog = Verification + Logic ▪ Initially started as documenting
language for integrated circuits in early
▪ Started for the purpose of verification
1980s
using simulation (fast simulation using
Verilog XL) ▪ Verbose and strict type checking
▪ Logic synthesis using Design Compiler ▪ IEEE standardized in 1987 and 2019
▪ Gained popularity due to simplicity
(similarity with C)
▪ IEEE standardized in 1995 and 2001
▪ SystemVerilog: superset of Verilog with
added functionality for design
verification (standardized in 2009)

Introduction to Verilog
Language Features

Meaning of Words…
‘When I use a word,’ Humpty Dumpty said in rather a

scornful tone, ‘it means just what I choose it to
mean—neither more nor less.’
‘The question is,’ said Alice, ‘whether you can make
words mean different things.’
‘The question is,’ said Humpty Dumpty, ‘which is to be
master—that’s all.’
—Lewis Carroll, Through the Looking-Glass, Chapter
6, 1871
Source:
https://commons.wikimedia.org/wiki/File:Lew
isCarrollSelfPhoto.jpg Lewis Carroll, Public
domain, via Wikimedia Commons

Lexical Tokens
▪ A Verilog file is a stream of lexical Comments
tokens
▪ Single line comment: //
▪ Lexical Rules
▪ Multiple line comments: /* … */
➢ Similar to C
// This is a comment
➢ Case sensitive /*
This is a block comment
Tokens */
▪ White spaces, Comments, Keywords,
Operators Keywords
▪ Identifiers ▪ Reserved word for Verilog
▪ Numbers, Strings ▪ In lower case only
▪ Examples: module, input, output, initial,
White space begin, end, always, endmodule, etc.
▪ White space can contain the characters Operators
for spaces, tabs, newlines, and form ▪ Predefined sequences of one, two, or three
feeds. characters used in an expression
▪ Used as separators for tokens ▪ Examples: ! + − && == !== etc.
Syntax and Semantics: Identifiers
Identifiers
▪ Unique names given to an object so that it can be referred to in the
Verilog code
▪ Objects can be modules, ports, nets, registers, functions, etc.
Rules for Identifiers Mymodule_top

▪ Must begin with an alphabetic character or underscore (a-z A-Z _) Register_123
▪ Subsequent characters can be a-z A-Z 0-9 _ $
Net_1
▪ Case sensitive
net_1
▪ Maximum allowed length < 1024 [by language]
Escaped Identifiers \net_(a + b)∗c

▪ Any character can be used in an identifier by “escaping” the
identifier
S. Saurabh, “Introduction to VLSI
➢ Preceding the identifier with a backslash “\” Design Flow”. Cambridge University
Press, 2023.
➢ Ending with a white space
Syntax and Semantics: Numbers (1)
Numbers
▪ Can be integers or real number
▪ Convenient/readable representation in code
➢ Can be specified in decimal, hexadecimal, octal or binary format
▪ Internally represented as sequence of bits
Integers:
▪ In traditional format like 169, -123
Verilog Internal Representation
▪ In the format:
-<size>’<base><value> 1 0000 0000 0000 0000 0000
0000 0000 0001
▪ - for negative sign (optional)
▪ <size> number of bits (default 32) 1’b1 1
▪ <base> can be b/B for binary, o/O, for 8’ha1 1010 0001
octal, d/D for decimal, h/H 6’o71 111 001
hexadecimal
S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge University
▪ <value> value of the integer Press, 2023.

Syntax and Semantics: Numbers (2)
Rules for Integers: -<size>’<base><value>
Verilog Internal Representation
▪ For hexadecimal, octal, and binary constants, 8’b100z00?1 100z 00z1
x/X represent the unknown/don’t care value and
z/Z/? represent the high-impedance value Verilog Internal Representation
➢ Prefer ? when high impedance is don’t care
6’h88 00 1000
▪ When <size> is smaller than <value> then
leftmost bits from the <value> are truncated Verilog Internal Representation
8’b11 0000 0011
▪ When <size> is greater than <value> then
leftmost bits are filled with 8’bz1 zzzz zzz1
▪ 0 if leftmost bit in <value> is 0/1
▪ Z if leftmost bit in <value> is Z Verilog Internal Representation
▪ X if leftmost bit in <value> is X 8’b1010_1010 1010 1010
▪ _ can be used in the middle of number to Verilog Internal Representation
enhance readability
-8’d6 1111 1010
▪ Negative numbers are internally represented in S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge University
two’s complement form. Press, 2023.
Syntax and Semantics: Real Numbers, Strings
Real Numbers: String:
▪ Can be represented in decimal <>.<> ▪ Is a sequence of characters enclosed by
➢ Example: 3.14159 double quotes and contained on a
single line
▪ Can be represented in scientific notation
<mantissa>E<exponent> ▪ Each character is represented by its
corresponding 8-bit ASCII value.
➢ Example: 2.99E8
▪ Example: “Hello”
▪ Internally, real numbers are represented in
IEEE standard for double-precision floating-
point numbers

Data Values and Data Types
Verilog supports four-valued data:
Two primary data types:
▪ 0: logic false or Boolean zero
1. Nets
▪ 1: logic true or Boolean one
2. Variables
▪ X: unknown value
▪ Z: high-impedance state
wire w1, w2;
Nets: wire w3=1’b1;
▪ Represent structural connections supply0 gnd;
▪ Cannot store value supply1 vdd;
▪ wire, supply0, supply1, wand, wor
reg r1, r2;
Variables:
▪ Element that store value in simulation ▪ We can assign reg in procedural
▪ Declared using keyword reg blocks
▪ Store last assigned value, until changed by ▪ Can model flip-flops, latches, and
another assignment also combinational elements
Press, 2023.
Data Types: Vectors and Arrays
▪ Nets and variables are 1-bit wide (scalar) by
default wire [31:0]databus;
▪ Can declare them as vectors by preceding the reg [7:0]addressbus;
declaration with vector definition in the following
format:
databus[4] = 1’b0;
[⟨left_range⟩:⟨right_range⟩].
addressbus[3:0] = 4'b1001;
▪ ⟨left_range⟩ is the most significant bit (MSB) and
⟨right_range⟩ is the least significant bit (LSB).
▪ Bit-select: select a bit of a vector by specifying reg r[15:0];
the address within the square bracket ([]).
wire matrix[9:0][9:0];
▪ Part-select: select a portion of a vector by
specifying the range of MSB and LSB separated
by a colon (:)
S. Saurabh, “Introduction to VLSI Design Flow”.
Cambridge University Press, 2023.
▪ Arrays: can be used for grouping elements into
multidimensional objects (specify
[⟨left_range⟩:⟨right_range⟩] after the identifier

References
2023.
▪ R. Seisyan. S. Palnitkar, “Verilog HDL: a guide to digital design and synthesis”, Pearson
Education India, 2003
▪ “IEEE standard Verilog hardware description language.” IEEE Std 1364-2001 (2001), pp. 1–
792.

GDS
Lecture 10
Hardware Modeling: Introduction to Verilog-II
Sneh Saurabh
Engineering
IIIT Delhi
Modules
▪ Modules are building blocks of a Verilog design: starts with a keyword module and ends
with endmodule
▪ Modules are instantiated inside another modules to create a design hierarchy
▪ Instantiation of a module means using that module in another higher-level module
module Top; module Bottom_1;

Mid m1; endmodule
Bottom_2 b2;
endmodule module Bottom_2;
endmodule
module Mid;
Bottom_1 b1;
endmodule
S. Saurabh, “Introduction to VLSI Design Flow”.
Cambridge University Press, 2023.

Ports
▪ Ports allow communication between the module top(clock, reset, test_port, data,
counter_out);
module and the environment
▪ Ports can be declared with keywords input, input clock;
output or inout input reset;
inout test_port;
▪ Can be scalar or vector (similar to net and input [3:0]data;
variables) output [3:0]counter_out;
endmodule

Press, 2023.

Instances and Connections
module mid(clock, d_in, d_out);
Connections for an instance can be input clock;
specified in two ways: input d_in;
output d_out;
1. By order (implicit connection) endmodule
▪ Ports connected automatically in
the instantiation based on order module top(c, p_in, p_out);
specified in the module
declaration mid m1(c, p_in, p_out);
▪ Difficult to debug
endmodule
2. By name (explicit connection)
▪ Ports connected by explicitly giving module top(c, p_in, p_out);
names
▪ Order not important mid m1(.clock(c), .d_in(p_in), .d_out(p_out));
endmodule
S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge University Press,

2023.

Parameterized Module
▪ Verilog allows definition of constants module counter(clk, rst, en, count);
for a module using the keyword parameter WIDTH=4;
parameter. input clk, rst, en;
output [WIDTH-1:0] count;
➢ The module in which a parameter reg [WIDTH-1:0] count;
is defined is referred to as a ...
parameterized module. endmodule
▪ Declare and provide a default value for module top();

the parameter in the module. ...
counter #(.WIDTH(16)) C1(clk, rst, en, count1);
➢ Can be overridden during counter #(128) C2(clk, rst, en, count2);
instantiation by providing non- counter C3(clk, rst, en, count3);
default values within #(). ...
endmodule

2023.

Built-in Gates
▪ Verilog primitive gates available for module mygates(a, b, en, y1, y2);
modelling logic gates
input a, b, en;
▪ Using keyword and, nand, or, nor, xor, output y1, y2;
xnor
and a1(y1, a, b);
▪ First pin is output pin and rest are and a2(y2, a, b, en);
inputs
endmodule

2023.

Operators and Expressions
Operators:
Expression
▪ Verilog supports operators with symbols
similar to C programming language ▪ Expressions can be formed by combining
operators with operands that yield some
➢ Arithmetic operators: +, -, * / etc. result
➢ Logical: operators !, &&, || etc. ▪ Paratheses can be used for specifying
➢ Bitwise operators: ~, !, |, ^, ~^ etc. precedence
➢ Relational: <, >, == etc.
➢ Shift operators: >> << etc. !(a&b);
▪ Operators act on operands to produce p<q
results (x+y)*z
▪ Operands can be of various data types such
as net, variable, bit-select, part-select, or
array element. S. Saurabh, “Introduction
2023.
to VLSI Design Flow”. Cambridge University Press,
▪ Number of operands for an operator is

defined by the language
➢ Example: One: !, Two: <, Three: (c ? a :
b) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Special Operators
▪ &, ~&, |, ~|, ^, ~^: Reduction operator ▪ Assume that A={1011}
perform a bit-wise operation on a single
operand to produce a single bit result. ▪ Then, Y = &A = 0
➢ The computation starts from the LSB
and moves toward the MSB
▪ Assume that:
a =2'b00,
b =4'b1111,
▪ {}: Concatenation operator, combines and c =1'b0.
(concatenates) the bits of two or more
data objects ▪ Then, {a, b, c} is 7'b0011110.
▪ Assume that:
a =2'b00,
▪ {N{}}: Replication operator (Multiple b =4'b1111,
concatenations performed N times)
and c =1'b0.
▪ Then, {4{a}, b, 2{c}} is 14'b00000000111100
Block of statement
▪ A group of statements within the keywords fork : my_block_name
begin and end forms a block statement-1
▪ A name can be given to a block statement-2
statement-3
begin : my_block_name join
statement-1
statement-2 ▪ Statement executed concurrently within
statement-3 fork-join block
end ➢ Known as parallel block
▪ Statement executed sequentially within

begin-end block S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge University Press,
2023.
➢ Known as sequential block

Control Statements
▪ Verilog supports control statements such as if-else, case, for, while, repeat similar to
traditional programming languages such as C
if (sel == 1’b0) begin input [1:0]sel;

y = a; case (sel) ▪ casez: treats z as
end 0: y = a; don’t care
else begin 1: y =b;
y = b; 2: y = c; ▪ casex: treats x and z
end default: y = d; as don’t care
endcase
for (i = 1; i < 8; i = i + 1 )
while (i < 8) begin repeat (8) begin
begin
y[i]= c[i]; y[i]= c[i];
state[i] = 1'b1;
i = i + 1; i = i + 1;
y[i]= c[i]; end
end
end
S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge University Press, 2023.

Structured Procedures
Verilog supports structured procedures using four constructs:

➢ Initial Block and Always block
➢ Function and Task.

Initial and Always Block
▪ Initial block: block of code starting with
the keyword initial module myTop(datain, dataout);
▪ Always block: block of code starting with input datain;
the keyword always output dataout;
reg clock, counter, dataout;

▪ Both types of blocks are enabled when
the simulation begins (time is 0). initial begin
clock = 1'b0;
▪ Initial block executes only once and counter = 1'b0;
stops when it reaches the end of the end
block
always begin
▪ Always block executes repeatedly #10 clock = ˜clock;
throughout the simulation. end
endmodule

Press, 2023.

Always block: Event Control
▪ Can also define event based on the
▪ Controlling event can be a value change
direction of change of a net or variable
on a net or a variable (level sensitive)
(edge sensitive).
always @(en) begin Two types edge sensitivity:

rega = regb;
end ▪ posedge : towards 1
➢ Transition from 0, x, and z to 1
➢ Transition from 0 to z or x.
▪ negedge : towards 0
➢ Transition from 1, x, and z to 0
➢ Transition from 1 to z or x.
always @(posedge clk) begin

q=d;
end

Always block: Sensitivity List
▪ Can specify the logical OR of multiple always @(posedge clk or negedge rst) begin
events such that any one of the events q=d;
can trigger the associated block or end
statement.
▪ The keyword or/comma (,) is used to

specify logical OR of event.
▪ The or-separated list of triggering events

is called the sensitivity list
▪ Sometimes we need to put all signals always @* begin

read in an always block in the sensitivity q=((a&b|c)^d)|e;
list end
➢ While modelling combinational logic
block
▪ Can use @* 2023.

Usage of Initial and Always Block
▪ Initial blocks used in test benches to initialize our design for simulation.
▪ Always blocks are essential element for RTL and behavioral modeling.
▪ A module can have any number of Initial and Always blocks.

▪ All these blocks get executed at the beginning of the simulation time.
➢ No predefined order in starting the execution of these Initial and Always blocks.
➢ Initial blocks need not get executed before Always blocks
▪ Initial and Always blocks provide a mechanism to model the concurrency of the hardware.
➢ Different hardware components working in parallel and whose order of starting the
execution is not within our control
❑ a simulation tool is free to choose any arbitrary order

Functions and Tasks (1)
▪ Functions and tasks can be Functions Tasks
used to model repeated
code Input / Can have one or Can have zero or
Output multiple inputs, but multiple inputs,
▪ Keywords are: function,
only one output outputs, inouts
endfunction, task, endtask
Timing Cannot have delays Can have delays
Delay modelled by posedge, modelled by posedge,
negedge, # negedge, #
Model Only combinational Both combinational
circuit and sequential circuits
Call Can call another Can call other task or
function but cannot function
call other task

Functions and Tasks (2)
module top(a, b, c, s1, c1, s2, c2);
module top(a, b, c, d, out1, out2); input a, b, c;
input a, b, c, d; output s1, c1, s2, c2;
output out1, out2;
task mytask;
function myfunc; input x, y;
input x, y, z; output sum, carry;
begin begin
myfunc = x-y+z; sum = x ˆy;
end carry = x & y;
endfunction; end
endtask;
assign out1 = myfunc(a, b, c);
assign out2 = myfunc(b, c, d); mytask(a, b, s1, c1);
mytask(b, c, s2, c2);
endmodule
endmodule

Assignments
Continuous assignment: module mymux(a, b, s, out);
Two types of assignments in Verilog: input a, b, s;
▪ Continuous assignment ▪ Provide values to the nets output out;
▪ Procedural assignment ▪ Using keyword assign
assign out = (s) ? a : b;
▪ Models combinational
circuit endmodule
always @(posedge clk)

Procedural assignment:
begin
▪ Provides values to the variables (such as reg or integer types) q = d;
➢ Do not change their values until the next procedural end
assignment
▪ Used inside structured procedures (initial block, always block, always @(posedge clk)
functions, and tasks) begin
q <= d;
▪ Two types: end
➢ Blocking assignment (=)
➢ Non-blocking assignment (<=) S. Saurabh, “Introduction to VLSI Design
Flow”. Cambridge University Press, 2023.

Blocking and Non-blocking Assignments
Blocking Non-blocking module top( );
Assignment Assignment reg a, b, c, p, q, r;
Symbol = <= initial begin
a = #10 1'b1; //at time = 10
b = #30 1'b1; //at time = 40
Execution Execution of next Execution of next c = #20 1'b1; //at time = 60
end
statement blocked statement not
until the current blocked until the initial begin
statement is current statement p <= #10 1'b1; //at time = 10
executed is executed q <= #30 1'b1; //at time = 30
r <= #20 1'b1; //at time = 20
end
Multiple Executes Executes
endmodule
statement sequentially parallelly

Press, 2023.

System Tasks and Functions
▪ Verilog supports some in-built system tasks and system functions that help in debugging
and verification
▪ Names start with $
▪ Examples: $display, $probe, $monitor, $stop, $finish, $reset, $random, $time etc..

References
2023.
▪ R. Seisyan. S. Palnitkar, “Verilog HDL: a guide to digital design and synthesis”, Pearson
Education India, 2003
792.

GDS
Lecture 11
Functional Verification using Simulation
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Functional Verification using Simulation
▪ Framework of Simulation
▪ Testbench
▪ Coverage
▪ Types of Simulators
▪ Mechanism of Simulation

Simulation
Framework

Simulation: Framework
Simulation is performed to verify that the output generated by the design is in agreement with
the desired functionality for the given test stimuli
Testbench
▪ Interacts with simulator
▪ Applies stimulus
▪ Observes response
Robustness of verification strongly depends on the testbench

Simulation
Testbench

Testbench: Illustration (1)
module Mycounter(CLK, RST, OUT);
input CLK, RST;

output [3:0]OUT;
reg [3:0]OUT;
always @ (posedge CLK)

begin
if (RST == 1'b1)
OUT <= 4'b0000;
else
OUT <= OUT + 1;
end
endmodule
▪ Instantiate the DUT
▪ Generate test signals
▪ Monitor the signals and save it in a file

Testbench: Illustration (2)
module Testbench();
reg Clock, Reset;
wire [3:0]Count;
// instantiate the DUV and make connections

Mycounter I1(.CLK(Clock), .RST(Reset), .OUT(Count));
// initialize the testbench
initial begin
Clock = 1’b0; Reset = 1'b1; // reset the counter at t=0
#100 Reset =1'b0; // remove reset at t=100
#2000 $finish; // end the simulation after t=2000
end
// generate stimulus (in this case clock signal)
▪ Instantiate the DUT always #50 Clock = ~Clock; // clock period = 100
▪ Generate test signals // monitor the response and save it in a file
initial begin
▪ Monitor the signals and $dumpfile (“count.vcd”); // specifies the VCD file
save it in a file $dumpvars; // dumps all variables
$monitor(“%d,%b,%b,%d”,$time, Clock, Reset, Count);
end
endmodule

Code Coverage
A good testbench:
▪ Performs comprehensive design verification without wasting resources on dispensable tasks
▪ Contains a sufficiently diversified set of stimuli

➢ Adding more test stimuli for already tested features may be redundant
Code Coverage:
▪ Identifies sections of DUV’s source code that did not execute during verification.
▪ Helps monitor the progress of verification effort
▪ Line coverage: number of times each RTL ▪ State coverage: whether all the states of an
statement is executed during simulation FSM have been activated and all the state
transitions traversed.
▪ Branch coverage: whether all branches of
the code (as in if–else and case statements) ▪ Toggle coverage: whether all variables or bits
were exercised in simulation in variables have risen and fallen.
Code Coverage vs. Functional Coverage
Code coverage: Functional coverage:
▪ Measures coverage of an existing code ▪ Measures whether the specified design

features have been exercised during
▪ An empty module will have a 100% code simulation
coverage, while complete functionality is
missing ▪ We need to provide design features using
coverage model
➢ Not automatically inferred by the tool
▪ Coverage model is independent of the

design implementation.
➢ Can detect missing features also in the
implementation

Simulation in Verilog
Mechanism

Verilog Simulation: Definitions (1)
Verilog considers a design as consisting of module top(in1, in2, out1, out2);
connected processes. input in1, in2;
output out1, out2;
reg out1, tt;
Processes: design objects that a simulator can
evaluate and produce a response to a given and A1(out2, tt, in1); // gate primitive
stimulus.
assign out1 = tt; // contn. assignment
Examples: gate primitives, initial block, always
block, continuous assignment, and procedural always @(in1 or in2) // always block
assignment statements. begin
tt = in1 & in2;
▪ Event: Anything that requires simulator to take end S. Saurabh, “Introduction to
VLSI Design Flow”. Cambridge
endmodule
some action. University Press, 2023.
▪ Processes: gate instance, continuous

▪ Events are of two types: assignment, always block
1. Update Event: change in the value of a net
or a variable. ▪ Assume: in1 makes a 0→1 transition
➢ Update event: for the net in1
2. Evaluation Event: evaluation of processes
when an update event has occurred ➢ Evaluation event: in gate instance and
always block (because sensitive)
Verilog Simulation: Definitions (2)
▪ Simulation time: time value maintained
by a simulator to model the actual time
in the simulated circuit.
➢ Simulation time depends on test-
bench and the design being
simulated
➢ Simulation time is different from the
time taken by the simulator to
simulate.
▪ Events have simulation time associated
with it
▪ Simulators need to ensure events are
processed in the increasing order of
time ▪ Timing wheel: an efficient data structure
to implement event queue
▪ Event Queue: internal queue maintained
by a simulator ordered by simulation ▪ An array of 𝑀 slots indexed by
time simulation time 𝑇%𝑀

Processing of Events
▪ Applying stimulus creates update
events At t=0, let A make
a 0→1 transition
▪ Update events can trigger evaluation
events
▪ Evaluation events can further change
values of nets/signals and lead to
new update events
▪ Sequence of:
update → evaluate → update →
evaluate …
goes on until the end of simulation
time
Assume that the circuit is as shown

above. Assume that delay of each gate
is 1 time unit.

Stratified Verilog Event Queue
Stratified Verilog Event Queue:
▪ Conceptual model that explains how different Verilog
constructs are simulated
▪ Events at a given simulation time is divided into five
layers and processed top-down
▪ There is no priority among Active Events
➢ Execution order among Active Events is arbitrary
➢ Source of indeterminism in simulation of Verilog
code
▪ Statements in a sequential block (within begin-end) are

executed as they appear in the block: deterministic
▪ Different blocks can be put in Active Events Queue in
any order: source of indeterminism
▪ NBA Updates can trigger further Active Events

Mechanism of Simulation: Illustration
For the Verilog code initial begin
shown along side, let a = 1'b0;
us determine the a <= 1'b1;
output of the $display $display("\nValue of a is :%b", a);
function. end
▪ a = 1'b0; put in Active Events Queue

▪ a <= 1'b1; RHS put in Active Events Queue and LHS put in
NBA Update Queue
▪ $display: put in Active Events Queue
▪ Active Event Queue is processed:
➢ a gets value of 1’b0
➢ $display produces “0” for a
▪ NBA Update Queue is processed:
➢ a gets value of 1’b1

Race conditions in Verilog : Definition
▪ Verilog language specification (IEEE standard) defines which statements have a guaranteed
order of execution and which statements have no guaranteed (indeterminate) order of
execution
▪ Definition: When two or more statements that are scheduled to execute in the same
simulation time, and would give different results when the order of execution of the
statements are changed (as permitted by IEEE standard), then race condition is said to
exist

Race conditions in Verilog : Illustration
module race();
reg a, b;
▪ Race conditions can occur in many
initial begin situations
a = 0;
b = 1; ▪ Race conditions are difficult to debug
end
initial begin ▪ Some guidelines or good coding practice

a = 1; can be followed to avoid race conditions
b = 0;
end
endmodule
S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge

References
2023.
▪ J. Bergeron, “Writing Testbenches: Functional Verification of HDL Models”, Springer Science &
Business Media, 2012.
792.

GDS
Lecture 15
Logic Optimization: Part II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Multilevel Logic Optimization

Multilevel Logic Optimization

Multilevel Logic Optimization: Introduction
Multilevel Logic: more than two levels of logic
▪ Can appear naturally in RTL
Limitations of two-level logic
▪ Sum of Product (SOP) representations of some

functions can become too big
➢ Example: parity functions, adders, and
multipliers.
▪ Cannot reduce area by trading off speed

➢ Multilevel logic circuits offer more flexibility in
exploring area–delay trade-off
Multilevel Logic Representations

▪ Factored Form
▪ Boolean Logic Network
Factored Form
A factored form consists of: A factored form is an SOP, of SOP, of SOP,
a) literals …, of arbitrary depth.
b) sum (logical OR) of factored form
c) product (logical AND) of factored form.
▪ Given an SOP, it can be converted to a

factored form by factoring ▪ Consider the following Boolean function in
the SOP form: 𝑎𝑐 + 𝑎𝑑 + 𝑏𝑐 + 𝑏𝑑 + 𝑐𝑒
▪ Factoring can convert a two-level
representation to a multilevel ▪ We can obtain a factored form
representation. representation as:
(𝑎 + 𝑏)(𝑐 + 𝑑) + 𝑐𝑒
▪ Given an SOP, its factored form is not (𝑎 + 𝑏)𝑑 + (𝑎 + 𝑏 + 𝑒)𝑐
unique
▪ Number of literals in the factored form correlates with the circuit area

Boolean Logic Network (1)
▪ Boolean logic network is a directed acyclic graph
➢ annotate each vertex with a single-output local Boolean function
▪ It can conveniently represent multilevel logic circuit with more than one output.
▪ Consider the following set of equations:

𝑝 = 𝑎 + 𝑏
𝑞 = 𝑒𝑓
𝑟 = 𝑝 + 𝑐′𝑑 + 𝑞
𝑠 = 𝑑′ + 𝑞′
𝑥 = 𝑟
𝑦 = 𝑠
▪ Assume that inputs are 𝑎, 𝑏, 𝑐, 𝑑, 𝑒, and 𝑓.
▪ Assume that 𝑥 and 𝑦 are outputs
▪ The incoming edges to a vertex denote the

variables on which the local function at
that vertex depends

Boolean Logic Network (2)
Flexibility of Boolean logic network:
▪ Local functions in a Boolean logic network can be arbitrarily complicated
▪ Both its underlying graph and the local functions can be manipulated during optimization
▪ Optimization can explore both the behavioral and the structural features of the
implementation
Estimating Area and Delay:
▪ Local functions restricted to be in an SOP form and made minimal with respect to single-
implicant containment
▪ Estimating area: sum of all the literal counts of the local functions
▪ Estimating delay: number of stages of vertices in the logic network

Transformations

Transformations
▪ Multilevel logic optimization is performed by applying transformations.
➢ These transformations can be viewed as operators for the Boolean logic network.
▪ These operators applied iteratively until no more improvement in some QoR measures is
possible.
➢ The final QoR depends on the order of operation and is hard to predict.

Eliminate
▪ It removes a vertex from the graph and replaces all its occurrences in the network with the
corresponding local function
▪ We carry out eliminate in the hope that subsequent transformations can reduce the cost
(area)

Simplify
▪ It simplifies the associated local SOP expression to reduce the literal count (two-level logic
optimization carried out on each local function individually)
▪ Reduces the literal count from 8 to 4

Substitute
▪ It replaces the local function with a simpler SOP by creating new dependencies and possibly
removing other dependencies.
▪ Creates dependencies by searching for an appropriate match.

➢ It adds more structural information to the network.
▪ Substitute operator needs to find whether local function 𝑓𝑖 divides another local function 𝑓𝑗
➢ If it divides, we can replace 𝑓𝑗 = 𝑄. 𝑓𝑖 + 𝑅
➢ Need to perform division efficiently
Extract
▪ It finds a common subexpression for functions associated with two or more vertices.
➢ Subsequently, it creates a new vertex associated with the subexpression.
➢ Then replaces the common subexpressions in the original functions with the variable of
the new vertex.

▪ Extract operator needs to find divisors for the local functions and then search vertices with
matching divisors.
➢ Implementing extract operator is computationally challenging
Challenges of Multilevel Logic Optimization
▪ Huge search space for optimization
Division Operation:
▪ During multilevel logic optimization, we need to carry out division too many times.
▪ Practical circuits have thousands of vertices in the Boolean logic network.

➢ Might need to divide each vertex with the rest [𝑂(𝑛2 ) times, where 𝑛 is the number of
vertices in the Boolean logic network]
▪ Efficiency of division of expressions is critical for multilevel logic optimization
Divisors:
▪ Need to find good divisors (one that can reduce cost) for Boolean expressions
▪ Finding a good set of divisors for a given Boolean expression is nontrivial

Algebraic Model
Algebraic Model:
▪ Neglecting some Boolean properties of the local functions
▪ Simplified model treats the local Boolean functions as polynomials and employs rules of
polynomial algebra
➢ Treat a variable and its complement as separate variables.
Applications of algebraic model:
▪ Efficient algorithms can be designed to carry out division in the algebraic model (rather than
in the Boolean model)
▪ Good divisors or common subexpressions in a complex Boolean logic network can be

determined efficiently in a complex Boolean logic network
➢ By intelligently pruning the search space (applying properties of algebraic models)

Algebraic Model versus Boolean Model
▪ Algebraic model (and associated mathematics) form the basis of fast multilevel optimization
in the contemporary logic optimization tools.
Boolean Model:
▪ An algebraic model is weaker than a Boolean model for optimization

➢ Cannot fully optimize a Boolean logic network.
▪ Post algebraic model-based optimization, transformations that utilize the power of the
Boolean model is applied

Boolean Model

Don’t Care (DC) Conditions
▪ Don’t Care (DC) conditions arise naturally in Boolean logic network
➢ Due to the graph structure and dependencies among local functions.
▪ DCs are a rich source of optimization in multilevel logic synthesis

➢ Simplifying local functions and improving the circuit’s overall QoR.
▪ A logic synthesis tool needs to discover them using Boolean algebra (in contrast to given
DCs)
There are two types of DC that are useful in simplifying local functions in a Boolean logic
network:
1. Controllability Don’t Cares (CDCs)
2. Observability Don’t Cares (ODCs).

Controllability Don’t Cares (CDCs)
▪ The combination of input variables that can never occur at a given vertex in a Boolean logic
network produces CDCs.
▪ Local functions can be simplified by accounting for CDCs and two-level logic minimizers
▪ At the input of vertex 𝑞, 𝑝 = 1 and 𝑏 = 0 can

never occur
▪ 𝑝𝑏′ can be treated as CDC
▪ Cover is: 𝑞 = 𝑝 +
𝑏𝑐
▪ Reduces the literal
count by 1
Cover is:
𝑞 = 𝑝𝑏 + 𝑏𝑐
Satisfiability Don’t Cares (SDCs)
▪ CDCs can be computed using efficient algorithms by exploiting Satisfiability Don’t Cares
(SDCs).
▪ SDCs get enforced by the local functions associated with a vertex at its output.
Consider the vertex 𝑝 = 𝑎𝑏
▪ The following function will never evaluate to 1:
𝑝 ⊕ 𝑎𝑏 = 𝑝𝑎′ + 𝑝𝑏′ + 𝑝′𝑎𝑏
▪ Hence, the combination of values that make the
above function 1 can never occur in the network:
𝑝 = 1, 𝑎 = 0,
𝑝 = 1, 𝑏 = 0,
𝑝 = 0, 𝑎 = 1, 𝑏 = 1
▪ These values can be treated as DCs for the Boolean
logic network
▪ Logic synthesis tools typically derive CDCs algorithmically using SDCs.

▪ Subsequently, the CDCs get utilized in simplifying local functions.

Observability Don’t Cares (ODCs)
▪ The ODCs are input variable combinations that obstruct the vertex output from being
observed at the network output.
▪ We derive ODCs induced by vertices in the fanout of a given vertex.
▪ If 𝑐 = 0, then 𝑥 = 0 irrespective of 𝑝
▪ 𝑐 = 0, can be treated as ODC for 𝑝
Cover is: ▪ Cover is: 𝑝 = 𝑎 + 𝑏

𝑝 = 𝑎𝑏 + 𝑏𝑐 + 𝑎𝑐 ▪ Literal count reduces from 9 to 5
References
1994.

2023.

GDS
Lecture 16
Logic Optimization: Part III
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Sequential Logic Optimization

Sequential Logic Optimization

Finite State Machine (FSM) : Definition
▪ FSM is an abstract mathematical model to represent wide variety of sequential circuits and
systems
An FSM consists: An FSM consists:

▪ Finite non-empty sets of states (𝑆) ▪ State transition function (𝛿)
▪ Finite non-empty sets of inputs (𝐼) and ➢ Given the current state and current
outputs (𝑂) input, it produces the next state
▪ Given initial state (𝑠0 )
Output function can be modelled in two ways in an FSM:
▪ Output is a function of the current state only: Moore Machine
▪ Output is a function of the current state and current input: Mealy Machine

Finite State Machine (FSM) : State Diagram
▪ We can represent an FSM pictorially using a directed graph called state diagram
State diagram is a directed graph:
▪ A state corresponds to a vertex in the graph
▪ Transition from one state to another state is

represented as an edge in the graph
➢ Edge starts from the current state and
ends in the next state
➢ Mark inputs at the edge
▪ Mark output value:

➢ Inside the state for Moore machine
➢ At the edges for the Mealy machine.

Finite State Machine (FSM): Example-1
A fan regulator can be described as an FSM:
▪ Four settings of regulator described as four states

➢ 𝑆 = {𝑠0, 𝑠1, 𝑠2, 𝑠3}
➢ 𝑠0 can be taken as an initial state
▪ Inputs to the regulator (rotate clockwise and rotate anti-clockwise) are inputs of the FSM
➢ 𝐼 = {𝐶, 𝐴}
▪ Four different speeds at four settings are outputs of the FSM

➢ 𝑂 = {𝑠𝑝𝑒𝑒𝑑0, 𝑠𝑝𝑒𝑒𝑑1, 𝑠𝑝𝑒𝑒𝑑2, 𝑠𝑝𝑒𝑒𝑑3}
Transitions:
▪ Rotate clockwise successively: 𝑠0 → 𝑠1 → 𝑠2 → 𝑠3 → 𝑠0 …
▪ Rotate anti-clockwise successively: 𝑠0 → 𝑠3 → 𝑠2 → 𝑠1 → 𝑠0 …
We can draw the state diagram for this FSM.

Finite State Machine (FSM): Example-1
Which kind of FSM is this?
Ans: Moore FSM.

Finite State Machine (FSM) Implementation
▪ FSM is implemented using flip-
flops and combinational circuit
elements
▪ States are represented by the

combination of the Q-pin value of
flip-flops.
▪ Transition function is implemented
using combinational logic
▪ Cost (area) of FSM implementation

can be reduced by:
➢ Reducing number of flip-flops
(state minimization)
➢ Reducing logic complexity of
combinational circuit elements
(state encoding)

State Minimization

State Minimization: Basics
Motivation for state minimization:
▪ To represent a state we use a sequence of bits
➢ For 𝑛𝑠 states, minimum ⌈𝑙𝑜𝑔2 𝑛𝑠 ⌉ bits required
▪ By reducing number of states 𝑛𝑠 , we can reduce number of bits in FSM representation
➢ Reduce number of flip-flops in FSM implementation
Objective of state minimization:

Two states of an FSM are equivalent :
▪ To derive an FSM that has the minimum
1. They produce identical outputs
number of states and exhibits the same
behavior as the original FSM 2. The corresponding next states are the
same or equivalent.
▪ Relies on determining equivalent states
▪ Among set of equivalent states, retain any one of the equivalent states and remove others
▪ Update the transition function to maintain the same behavior as the original FSM.

State Minimization: Illustration
Consider an FSM shown: inputs 𝐼 = {𝐴, 𝐵} and outputs 𝑂 =
{0, 1}.
Consider the states 𝑠𝐴 and 𝑠𝐶 :

▪ Outputs:
➢ When input is 𝐴, both states produce 1
➢ When input is 𝐵, both states produce 0.
▪ Next States:
➢ When input is 𝐴, 𝑠𝐴 transitions to 𝑠𝐶 (equivalent state)
and 𝑠𝐶 transitions to 𝑠𝐴 (equivalent state).
➢ When the input is 𝐵, both 𝑠𝐴 and 𝑠𝐶 transitions to 𝑠𝐵.
▪ The states 𝑠𝐴 and 𝑠𝐶 are equivalent
▪ Efficient algorithms exist to find set of equivalent states.

State Encoding

State Encoding
State encoding:
▪ It assigns a binary representation to each state
of an FSM.
Impact of state encoding:

▪ Changing the state encoding, can change the
next state function and the output function
▪ Combinational circuit block CL and the
associated QoR can change.

Encoding Length
Encoding length:
▪ To represent an FSM with 𝑛𝑠 states, we need at least ⌈𝑙𝑜𝑔2 𝑛𝑠 ⌉ bits
▪ Longer encoding lengths can also be chosen
▪ Example: one-hot encoding reserves one bit for each state (encoding length is 𝑛𝑠 )
Impact of encoding length:
▪ Number of flip-flops
▪ Inputs/Outputs of CL
▪ Sometimes CL can be simplified by changing

encoding length.
➢ One-hot encoding: identifying a state
requires examining only one state bit.
➢ One-hot encoding can have fewer logic
levels between flip-flops and be faster

Choosing Encoding Scheme
Challenges:
▪ Exponential number of possibilities
➢ Brute force cannot be applied to examine all solutions.
▪ During encoding, CL implementation is not done
➢ Need to assess the encoding quality based on the expected FSM implementation.
Approach:
▪ CL needs to produce the next state functions and
output functions
➢ Encode such that they share logic
➢ Allow more common cubes and common sub-
expressions
Heuristics-based Algorithms:
➢ Quantify the possibility of common cube extraction
as “gain” of an encoding scheme
➢ Determine encoding that maximizes the “gain”
References
2023.

1994.
▪ S. Devadas, H.-K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. “MUSTANG: State

assignment of finite state machines targeting multilevel logic implementations.” IEEE
Transactions on Computer-aided Design of Integrated Circuits and Systems 7, no. 12 (1988),
pp. 1290–1300.

GDS
Lecture 17
Formal Verification- I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Functional Verification
Simulation-based Formal methods
▪ Functional Verification using Formal Methods

Proof of correctness …
‘...program testing can be a very effective way to show

the presence of bugs, but is hopelessly inadequate for
showing their absence. The only effective way to
raise the confidence level of a program significantly is
to give a convincing proof of its correctness...”
—Edsger W. Dijkstra, “The humble programmer,” ACM
Turing Lecture, 1972
Source:
https://commons.wikimedia.org/wiki/File:Edsger_Wybe_Dijks
tra.jpg Hamilton Richards, CC BY-SA 3.0
<http://creativecommons.org/licenses/by-sa/3.0/>, via
Wikimedia Commons VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
Formal
Verification

Limitations of Simulation-based Verification
Illustration:
▪ Consider multiplication of two 32-bit integers
▪ There are 232 × 232 = 264 combinations.
▪ If simulation of one test vector take 1μs to simulate,
➢ Will take 264 × 1 × 10−6 seconds (≈ 0.5 million years approximately!)
▪ Simulation-based exhaustive verification is not feasible for real-world designs
Problems of Simulation-based Verification:

▪ Input patterns biased towards anticipated sources of errors
➢ Errors often occur where not anticipated
▪ Can never prove the correctness of a given design.
▪ Formal verification methodologies provide a feasible alternative.

Formal Verification as an Alternative
Formal Verification as an alternative
▪ Applies mathematical reasoning to establish proof of correctness
▪ Correctness ⇒ the system behaves correctly irrespective of input vectors
➢ All cases implicitly covered in Formal Verification
Specification: 𝑦 = (𝑥 − 4)2
Design: 𝑦 = 𝑥 2 − 8𝑥 + 16
𝒙 Specification: Design: 𝒚 = Pass/Fail? Formal verification

𝒚 = (𝒙 − 𝟒)𝟐 𝒙𝟐 − 𝟖𝒙 + 𝟏𝟔
0 16 16 Pass (𝑥 − 4)2
1 9 9 Pass = 𝑥−4 . 𝑥−4
2 4 4 Pass
= 𝑥. 𝑥 − 4 − 4. 𝑥 − 4
= 𝑥. 𝑥 − 𝑥. 4 − 4. 𝑥 + 16
-1 25 25 Pass
= 𝑥 2 − 8𝑥 + 16
104 10000 10000 Pass
Formal Verification : Differences with Simulation
Simulation-based verification Formal verification
Test Vectors Required Not Required

Completeness No Yes
Mechanism Test Vectors simulate the A mathematical proof of
design and output response correctness is established or
compared with the expected a counter-example is
response produced
Memory Requirement Comparatively Low Comparatively High

Formal Verification: Techniques
▪ Formal verification is computationally challenging
▪ Early 1990s, efficient formal verification techniques for VLSI applications developed
Formal Verification
Techniques
Binary Decision Diagrams Satisfiability (SAT) Problem

(BDDs) Solvers

Formal Verification
Binary Decision
Diagram

Boolean Function Representations: Compactness
▪ Boolean functions can be represented in many ways
Compactness of Representation:
▪ Quantifies the growth in the size of a representation with the increase in the number of
Boolean variables
▪ Examples:
➢ A truth table has 2𝑁 rows for a Boolean function of 𝑁 variables.
❑ Truth table size increases exponentially with the number of Boolean variables
➢ A logic formula representation of a function: 𝑦 = 𝑎𝑏 + 𝑎𝑐𝑑 + 𝑏′ 𝑑 + 𝑏𝑐′ can be very
compact
▪ Desirable: a Boolean function representation should be as small as possible.

➢ Data structure consumes less memory and easy manipulation

Boolean Function Representations: Canonicity
Canonicity of Representation:
▪ If a representation is canonical, then the two equivalent functions are represented
identically.
▪ Conversely, if a representation is canonical, and if two functions have the same
representation, they are functionally equivalent.
▪ Examples:
➢ A truth table is a canonical representation of a Boolean function
➢ A logic formula is not canonical:
❑ We can represent 𝑦 = 𝑎𝑏 + 𝑎𝑐 + 𝑏𝑐 as 𝑦 = 𝑎 𝑏 + 𝑐 + 𝑏𝑐, 𝑦 = 𝑎𝑏 + 𝑐(𝑎 + 𝑏), 𝑦 =
𝑎𝑏 + 𝑎𝑐 + 𝑏(𝑐 + 𝑎𝑎′ ), 𝑦 = 𝑎𝑏 + 𝑏𝑐. 𝑎 + 𝑎′ + 𝑎𝑐, etc.
▪ Desirable: In general, we want a representation to be canonical.
➢ Manipulating Boolean functions becomes easier in a canonical representation
(Example: checking the equivalence of two functions is trivial)
Compact canonical representation of Boolean functions is of great interest for logic synthesis
and verification

Binary Decision Diagrams (BDD)
BDD: a data structure to represent Boolean functions canonically
▪ Is compact for many practically relevant functions
▪ Boolean operations relevant to formal verification is very efficient
• BDDs are built using Shannon 𝒚 = 𝒂𝒃 + 𝒂𝒄𝒅 + 𝒃′ 𝒅 + 𝒃𝒄′

expansion
➢ Boolean Function is split into two 𝑎 = 0 : 𝑦0 = 𝑏’𝑑 + 𝑏𝑐’
sub-functions by assigning 0/1 to a 𝑎 = 1 : 𝑦1 = 𝑏 + 𝑐𝑑 + 𝑏’𝑑 + 𝑏𝑐’
variable
➢ The subfunction obtained by 𝒚 = 𝒂′ 𝒃’𝒅 + 𝒃𝒄’ + 𝒂(𝒃 + 𝒄𝒅 + 𝒃’𝒅 + 𝒃𝒄’)
assigning 0 is called negative
cofactor
➢ The subfunction obtained by
assigning 1 is called positive
cofactor

Binary Decision Tree
Boolean functions can be represented as Binary Decision Tree by applying Shannon Expansion
Theorem recursively
𝑦 = 𝑥1 𝑥2 + 𝑥2 ′𝑥3 + 𝑥1 ′𝑥3 ′ Level 1: (Expand w.r.t 𝑥1 ) Level 2: (Expand w.r.t 𝑥2 )
𝑦𝑥1 =0 = 𝑥2′ 𝑥3 + 𝑥3′ 𝑦𝑥1=0,𝑥2=0 = 𝑥3 + 𝑥3′
Level 3: (Expand w.r.t 𝑥3 ) 𝑦𝑥1=1 = 𝑥2 + 𝑥2 ′𝑥3 𝑦𝑥1=0,𝑥2=1 = 𝑥3′
𝑦𝑥1=0,𝑥2=0,𝑥3=0 = 1 𝑦𝑥1=1,𝑥2=0 = 𝑥3
𝑦𝑥1=0,𝑥2=0,𝑥3=1 = 1 𝑦𝑥1=1,𝑥2=1 = 1
𝑦𝑥1=0,𝑥2=1,𝑥3=0 = 1
𝑦𝑥1=0,𝑥2=1,𝑥3=1 = 0
𝑦𝑥1=1,𝑥2=0,𝑥3=0 = 0
𝑦𝑥1=1,𝑥2=0,𝑥3=1 = 1
𝑦𝑥1=1,𝑥2=1,𝑥3=0 = 1
𝑦𝑥1=1,𝑥2=1,𝑥3=1 = 1
To make it canonical and compact, we need to add constraint on variable ordering and
remove redundancies
Binary Decision Tree: Variable Order
• At an intermediate node, we can choose any variable for expansion in a binary decision
tree
• In general, different variable orders can give different binary decision tree
To enforce canonicity, we need to add constraint on the Binary Decision Tree
Ordered Binary Decision Diagram (OBDD): A BDD becomes an OBDD if the decision variables
follow the same order in all the paths from the root to the leaf nodes

Ordered Binary Decision Diagram (OBDD)
• Consider a Boolean function 𝑓(𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑛 ) of 𝑛 Boolean variables {𝑥1,𝑥2 ,𝑥3 , … , 𝑥𝑛 }
• OBDD is a rooted, directed, acyclic graph consisting of two types of vertices:
➢ Terminal vertices
➢ Non-terminal vertices
Terminal vertices (outdegree is 0): Each non-terminal vertex 𝑣 has:

➢ 0 Node : function assumes a value “0” ➢ Two children 𝑙𝑜𝑤 𝑣 and ℎ𝑖𝑔ℎ 𝑣
➢ 1 Node : function assumes a value “1” ➢ Attribute 𝑖𝑛𝑑𝑒𝑥 𝑣 ∈ {1,2, … 𝑛} and it
refers to the corresponding variable in
the set {𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑛 }
• Edge between a vertex 𝑣 and 𝑙𝑜𝑤 𝑣 represents the case when the corresponding
variable assumes 𝑥𝑖𝑛𝑑𝑒𝑥(𝑣) = 0
• Similarly high 𝑣 corresponds to 𝑥𝑖𝑛𝑑𝑒𝑥(𝑣) = 1
▪ To enforce ordering of non-terminal vertices: 𝑖𝑛𝑑𝑒𝑥 𝑣 < 𝑙𝑜𝑤(𝑖𝑛𝑑𝑒𝑥 𝑣 ) and 𝑖𝑛𝑑𝑒𝑥 𝑣 <
ℎ𝑖𝑔ℎ(𝑖𝑛𝑑𝑒𝑥 𝑣 )

OBDD: Example
𝑦 = 𝑥1 𝑥2 + 𝑥1 𝑥3 + 𝑥2 ′𝑥3 ▪ A Boolean function is not
uniquely defined by an
OBDD (i.e. OBDD is not
canonical)
▪ OBDD can be made canonical by removing redundancies

➢ Obtain a Reduced OBDD (ROBDD)

Isomorphic OBDDs
Isomorphism:
• Two OBDDs 𝐹1 and 𝐹2 are isomorphic if there exists a one-to-one mapping between their
set of vertices such that the adjacency is preserved.
• The correspondence of the value at the terminal vertices and index at the nonterminal
vertices must exist.

Reduced Ordered Binary Decision Diagram (ROBDD)
ROBDD is an OBDD with the following constraints: Can be obtained by systematically
▪ No vertex 𝑣 has 𝑙𝑜𝑤(𝑣) = ℎ𝑖𝑔ℎ(𝑣) removing vertices from the OBDD:
▪ No pair of vertices {𝑢, 𝑣} exists in the OBDD such ▪ Any vertex with identical children
that subgraph rooted at 𝑢 and 𝑣 are isomorphic. is removed and replaced with any
of its children.
▪ Two vertices with identical OBDDs
are merged into one.

Reduced Ordered Binary Decision Diagram (ROBDD)
• Bryant proved that an ROBDD is a Applications:
canonical representation of a Boolean • Testing equivalence of two functions is easy
function • Testing satisfiability and tautology becomes
• When we talk of BDD, we typically refer easy
to ROBDD
Compactness:
• Size of ROBDDs for many Boolean functions grows as polynomial with the number of
variables
• Size of ROBDDs for a given function depends on the variable order.
➢ Depending on the variable order, the size of ROBDD can be linear or exponential for an
adder circuit
➢ Finding a good variable order is difficult
➢ For some functions, such as a multiplier, the size of ROBDD is always exponential

References
▪ R. E. Bryant. “Symbolic Boolean manipulation with ordered binary-decision diagrams.” ACM
Computing Surveys (CSUR) 24, no. 3 (1992), pp. 293–318.
2023.

GDS
Lecture 18
Formal Verification - II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Formal Verification Techniques
Boolean Functions using Boolean Satisfiability (SAT)

Binary Decision Diagrams (BDDs) Problem Solvers
▪ Boolean Satisfiability Problem Solvers

Formal Verification
Satisfiability Problem
Solver

Satisfiability : Problem Definition (1)
• Given 𝑦 = 𝑓(𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑛 ) where the variables {𝑥1,𝑥2 ,𝑥3 , … , 𝑥𝑛 } are Boolean variables
• Can 𝑦 be evaluated to 1 by any assignment of variables {𝑥1 ,𝑥2 ,𝑥3 , … , 𝑥𝑛 }?
• If yes, then 𝑓 is a satisfiable (SAT) instance, else it is an unsatisfiable (UNSAT) instance.
Given: 𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = 𝑥1 𝑥2 + 𝑥1 𝑥3 + 𝑥2 ′𝑥3 . Is Given: 𝑔(𝑥1 ,𝑥2 ,𝑥3 ) =

it a SAT instance? (𝑥1 +𝑥2 )(𝑥1 ′ +𝑥2 ′)(𝑥1 ′+𝑥2 )(𝑥1 + 𝑥3 )(𝑥1 +𝑥3 ′).
Is it a SAT instance?
• The function 𝑓 can be evaluated to 1 • Cannot be evaluated to 1 for any
by following assignments: combination of values of {𝑥1 ,𝑥2 ,𝑥3 }
• 𝑥1 = 0, 𝑥2 = 0, 𝑥3 = 1 • It is an UNSAT instance
• 𝑥1 = 1, 𝑥2 = 0, 𝑥3 = 1
• 𝑥1 = 1, 𝑥2 = 1, 𝑥3 = 0
• 𝑥1 = 1, 𝑥2 = 1, 𝑥3 = 1
• Yes, it is a SAT instance

Satisfiability: Problem Formulation
Inputs to SAT solvers are typically given in Conjunctive Normal Form (CNF)
➢ CNF is AND of clauses
➢ Clauses are OR of literals
➢ Literals are variable or its complement
𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = (𝑥1 +𝑥2 ) (𝑥1 ′+𝑥2 )(𝑥1 +𝑥3 ′) ▪ Variables: 𝑥1 ,𝑥2 , 𝑥3
▪ Literals: 𝑥1 ,𝑥2 , 𝑥1 ′,𝑥3′
▪ Clauses: (𝑥1 +𝑥2 ) , (𝑥1 ′ +𝑥2 ) and (𝑥1 +𝑥3 ′)
Why to use CNF in SAT solver?

• It reduces to 0 if any of the clauses is 0.
➢ To make a function satisfiable, all its clauses must be made 1
• SAT Solvers can exploit this observation
➢ Easily detect conflicts
➢ Apply reasoning and reduce search space
• A given combinational logic circuit can be transformed into a CNF representation in linear
time and space

Satisfiability : k-SAT problem
• We encounter various forms of SAT problems
• k-SAT problem: each clause in the CNF representation of a Boolean function is of maximum
𝑘 literals
Examples
• 2-SAT Problem: 𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = (𝑥1 +𝑥2 ) (𝑥1 ′+𝑥2 )(𝑥1 +𝑥3 ′)
• 3-SAT Problem: 𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = (𝑥1 +𝑥2 + 𝑥3 ) (𝑥1 ′+𝑥2 )(𝑥1 +𝑥3 ′)
• 4-SAT Problem: 𝑓(𝑥1 ,𝑥2 ,𝑥3 , 𝑥4 ) = (𝑥1 +𝑥2 + 𝑥3 ) (𝑥1 ′+𝑥2 )(𝑥1 +𝑥2 + 𝑥3 ′ + 𝑥4 ′)
Complexity:
• 2-SAT Problem: can be solved in polynomial time
• 3-SAT Problem: NP-complete problem (No known algorithm exist that can solve in
polynomial time for the worst case)
• k-SAT where k >3: NP-complete

Satisfiability Solver: Technique (1)
• For a function of 𝑛 variables, there are 2𝑛 possible variable assignments.
➢ In the worst case, we need to try all of them (not feasible for practical cases)
• Perform a systematic search and pruning the search space
• Davis–Putnam–Logemann–Loveland (DPLL) algorithm:
➢ Heuristically assigning a value 0/1 to an unassigned variable.
➢ Deduces the consequences of the assignments or determines forced assignments
• Unit Clause and Implications: clause in which all but one literal takes a value 0 and the
corresponding forced assignment of variable is called implication
• Assignment of variables leads to implications
➢ Implication can further generate unit clauses
• Example: 𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = (𝑥1 +𝑥2 ) (𝑥1 ′+𝑥3 )(𝑥2 ′ +𝑥3 ′). Let us assign 𝑥1 = 1.
➢ (𝑥1 ′+𝑥3 ) becomes unit clause. 𝑥3 = 1 is an implication
➢ (𝑥2 ′ +𝑥3 ′) becomes unit clause. 𝑥2 = 0 is an implication
• Boolean Constraint Propagation (BCP): deduce implications iteratively until possible

Satisfiability Solver: Technique (2)
Conflict and Backtracking:
• Variable assignments (and associated implications), can make all literals in a clause
evaluate to 0.
➢ This scenario is known as a conflict
➢ Requires to backtrack some earlier decisions by flipping the variable assignment
• Example: 𝑓(𝑥1 ,𝑥2 ,𝑥3 ) = (𝑥1 +𝑥2 ) (𝑥1 ′+𝑥3 )(𝑥1 ′ +𝑥3 ′). Let us assign 𝑥1 = 1.
➢ (𝑥1 ′+𝑥3 ) becomes unit clause. 𝑥3 = 1 is an implication
➢ All literals in (𝑥1 ′ +𝑥3 ′) becomes 0.
➢ Backtrack 𝑥1 = 0 and proceed.
• When is a function satisfiable: If no conflict is encountered, the solver goes on assigning

variables until all variables get assigned.
• When is a function unsatisfiable: If we obtain a conflict and no more backtracking is

possible, the function is unsatisfiable.

Satisfiability Solver: Algorithm (1)
Input: Given function 𝑓 in CNF
Output: return SAT if satisfiable and UNSAT if not satisfiable
1: decision_level ← 0
2: while (DECIDE( f, decision_level) != ALL_ASSIGNED) do
3: if (DEDUCE( f, decision_level) = CONFLICT) then
4: backtrack_level ← DIAGNOSE( f, decision_level)
5: if (backtrack_level = NOT_POSSIBLE) then
6: return UNSAT
7: else
8: BACKTRACK( f, decision_level, backtrack_level)
9: decision_level ← backtrack_level
10: end if
11: else
12: decision_level ← decision_level + 1
13: end if
14: end while ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
15: return SAT
Satisfiability Solver: Algorithm (2)
Improvements:
• Preprocessing to simplify the SAT problem,
• Employing efficient data structure for BCP
• Intelligent pruning of search spaces and random restarts
• Multicore processing

References
2023.
▪ S. Malik and L. Zhang. “Boolean satisfiability from theoretical hardness to practical success.”,
Communications of the ACM 52 (Aug. 2009), pp. 76–82.
▪ S. A. Cook. “The complexity of theorem-proving procedures.” Proceedings of the Third
Annual ACM Symposium on Theory of Computing, STOC ’71, (New York, NY, USA) (1971), pp.
151–158, ACM.

GDS
Lecture 19
Formal Verification- III
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Model Checking
▪ Verifies that for a given model
(design), whether the
Formal Verification
specifications or given set of
Usage
properties are satisfied
Equivalence Checking
Model Checking Equivalence Checking ▪ Verifies that the two
representations of the same
design will exhibit exactly the
same behavior

Formal Verification
Model Checking

Model Checking: Framework
Inputs
▪ Given design in RTL or Netlist
➢ Typically modelled as an FSM
▪ Set of properties that a model checker needs to
verify
Challenges
▪ Model checker needs to verify that the given
property is valid as the FSM evolves through its
states
▪ For 𝑁 state elements: number of states can be
2𝑁
▪ This problem is known as the state explosion
problem

Model Checking: Property Specification
▪ Properties are specified in Temporal Logic ▪ Ordering of events is implicit
▪ eventually, never, always, whenever,
Temporal Logic etc.
▪ System properties need time-related ▪ Modelled using System Verilog Assertion
specification, in addition to logic related (SVA)
expressions ➢ Embed SVA in RTL
➢ Checked by both model checker and
Examples of temporal properties simulators
▪ Whenever a correct password is entered, ➢ Can specify assumptions and
the door eventually opens constraints (to make property
▪ For traffic lights at a given post, one of the checking easier for the tool)
red, yellow or green light is always ON
▪ Whenever a request is made by multiple
requesters, it is never granted to more
than one requesters simultaneously

Model Checking: Techniques
Primary Difficulty:
▪ Exhaustive search becomes difficult due to the state explosion problem
➢ Explicitly enumerating states and representing them as graphs could not scale
▪ A breakthrough came around 1990 when symbolic state-space exploration was proposed :
➢ First it employed BDDs
➢ Later SAT-based techniques.

Formal Verification
BDD-based Model
Checking

BDD-based Model Checking: Characteristics Function
Characteristic Function for a set:
▪ Consider an FSM with a finite set of states 𝑄.
▪ Further, consider a subset of states 𝐴 ⊂ 𝑄
➢ 𝐴 can be represented by a Boolean function 𝑓 such that for any state 𝑥 ∈ 𝑄, 𝑓(𝑥) = 1 if
and only if 𝑥 ∈ 𝐴
Example:
▪ Consider an FSM with five states 𝑄 = {𝑠0 , 𝑠1 , 𝑠2 , 𝑠3 , 𝑠4 }.
▪ Let the states be represented by 3 bits {𝑥2 𝑥1 𝑥0 }. We refer to these bits as state bits.
▪ We can encode these states {𝑠0 , 𝑠1 , 𝑠2 , 𝑠3 , 𝑠4 } as {000,001,010,011,100}.
▪ In this representation we can represent the subset of states: 𝐴 = 𝑠0 , 𝑠2 , 𝑠4 as a Boolean
function: 𝑓 𝑥2 , 𝑥1 , 𝑥0 = 𝑥2 ′𝑥1 ′𝑥0 ′ + 𝑥2 ′𝑥1 𝑥0 ′ +𝑥2 𝑥1 ′𝑥0 ′
▪ We can represent a large set using its characteristics function with the help of compact
BDDs
▪ We can also compute the transition from a set of states to another set of states very
efficiently using BDDs

BDD-based Model Checking: Transition Relation
▪ Consider an FSM with set of states 𝑄. Transition relation for an FSM:
▪ Let us denote the set of input values as 𝐼. ▪ The transition can be defined using a
▪ Let us denote the next-state function as transition relation 𝑇(𝑥, 𝑖, 𝑥′) such that
𝑥′ = 𝛿(𝑥, 𝑖) for 𝑥 ∈ 𝑄 and 𝑖 ∈ 𝐼. 𝑇(𝑥, 𝑖, 𝑥′) = 1 if and only if 𝛿(𝑥, 𝑖) = 𝑥′.
▪ We can represent a transition

relation 𝑇 𝑥, 𝑖, 𝑥 ′ compactly
using BDD
▪ Subsequently, we use the
transition relation in BDD-based
model checking

BDD-based Model Checking: Image/Preimage
Image of a set of states:
▪ Image for a given set of states 𝑆 is the set of states 𝑆′ that we can reach in one step from 𝑆.
▪ We denote the image computation as 𝑆′ = 𝐼𝑚𝑎𝑔𝑒(𝑆, 𝑇) [𝑇 is the transition relation].
Preimage of a set of states:

▪ Preimage of a set of states 𝑆′ is a set of states 𝑆 from which we can reach 𝑆′ in one step.
▪ We denote preimage computation as 𝑆 = 𝑃𝑟𝑒𝑖𝑚𝑎𝑔𝑒(𝑆′, 𝑇).
▪ For a given set of states, we can compute image and preimage very efficiently using BDDs.
▪ BDD-based model checking relies on this computation

BDD-based Model Checking: Computing Reachable
States
Input: ▪ The set of reachable states 𝑆𝑟𝑒𝑎𝑐ℎ until no
▪ Given starting set of states 𝑆0 more new states are discovered
▪ Transition relation 𝑇(𝑥, 𝑖, 𝑥′) ➢ Algorithm is said to have attained a fixed
Output: point.
▪ Returns reachable set of states 𝑆𝑟𝑒𝑎𝑐ℎ
1: 𝑆𝑟𝑒𝑎𝑐ℎ ← 𝑆0
2: 𝑆𝑛𝑒𝑤 ← 𝑆0 ▪ States represented compactly
3: 𝑘 = 0 as characteristic functions
4: while (𝑆𝑛𝑒𝑤 ≠ {}) do using BDDs
5: 𝑘 ← 𝑘 + 1 ▪ Canonicity of BDDs eases
6: 𝑆𝑘 ← 𝐼𝑚𝑎𝑔𝑒(𝑆𝑛𝑒𝑤 , 𝑇) manipulation
7: 𝑆𝑛𝑒𝑤 ←𝑆𝑘 − 𝑆𝑟𝑒𝑎𝑐ℎ ▪ Pre-image computation: set of
8: 𝑆𝑟𝑒𝑎𝑐ℎ ← 𝑆𝑟𝑒𝑎𝑐ℎ ∪ 𝑆𝑛𝑒𝑤 all states from which 𝑆0 can be
9: end while reached.
10: return 𝑆𝑟𝑒𝑎𝑐ℎ

BDD-based Model Checking: Technique
Example: Suppose it is required to check whether a state satisfying a Boolean function 𝑃 is
reachable from a given initial state 𝑠0 .
▪ Let both the states and the Boolean function 𝑃 be represented in terms of state bits.
▪ A model checker considers a set of states 𝑆𝑃 for which 𝑃 holds.
▪ Let us represent the set 𝑆𝑃 using the characteristic function 𝐶𝐹𝑆𝑃 .
▪ But, 𝐶𝐹𝑆𝑃 = 𝑃 (i.e., the characteristic function of the set of states for which 𝑃 holds is
nothing but 𝑃)
➢ Consider a state 𝑥 for which 𝑃 holds. Therefore, 𝑃(𝑥) = 1 and 𝑥 should belong to 𝑆𝑃 .
Hence, 𝐶𝐹𝑆𝑃 (𝑥) = 1
➢ Consider a state 𝑦 for which 𝐶𝐹𝑆𝑃 (𝑦) = 1 . Therefore, 𝑦 belongs to 𝑆𝑃 and 𝑃 should hold
for it. Hence, 𝑃(𝑦) = 1.
➢ Thus, 𝐶𝐹𝑆𝑃 = 𝑃
▪ Using preimage computation, we can determine the set of all states 𝑆𝑟𝑒𝑎𝑐ℎ ′ from which 𝑆𝑃
can be reached.
▪ If 𝑆𝑟𝑒𝑎𝑐ℎ ′ includes the initial state 𝑠0 , given property holds.
▪ If 𝑆𝑟𝑒𝑎𝑐ℎ ′ does not include the initial state 𝑠0 , the given property does not hold
BDD-based Model Checking: Limitations
▪ In the worst case, the size of BDD can be exponential in the number of inputs.
➢ A BDD-based representation of transition relation can blow up with an increase in the
number of state bits.
➢ Different variable orders can be tried
▪ Manual interventions, such as adding constraints, can help.

➢ Simplify the problem for the model checker and make it solvable.

Formal Verification
SAT-based Model
Checking

SAT-based Model Checking: Technique
Approach:
▪ Obtain a counterexample of a finite length 𝑛 (𝑛 is the number of clock cycles from the initial
state)
▪ We derive a Boolean function 𝜙𝑛 using the given circuit and the given property such that:
the function 𝜙𝑛 is satisfiable if and only if a counterexample of length exists.
▪ This type of model checking is known as Bounded Model Checking (BMC)
➢ Typically, we carry out BMC iteratively by incrementing 𝑛.
➢ It continues until we have found a counterexample or the problem becomes too
complicated to be handled by the SAT solver.
Mechanism:
▪ To derive 𝜙𝑛 , we unfold the behavior of the system one cycle at a time using the next-state
function until it reaches 𝑛th clock cycle.
▪ The Boolean function 𝜙𝑛 is the logical conjunction (ANDs) of clauses obtained from:
➢ Given initial state.
➢ The system behavior obtained from the next-state function.
➢ A Boolean expression that evaluates to 1 for a counterexample (derived from the given
property).
SAT-based Model Checking: Merits/Demerits
Merits:
▪ Avoids the problem of memory blow-up in representing transition relations in the BDD-based
model checking
➢ Next-state function grows linearly as the BMC traverses the next state in each cycle.
➢ But can take longer time by SAT solver because introduction of new variables
▪ Exploits power of SAT solver
Demerits:
▪ Lacks completeness.
➢ In practice, can quickly find bugs (if it exists)

References
▪ J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L.-J. Hwang. “Symbolic model
checking: 1020 states and beyond.” Information and Computation 98 (1992), no. 2, pp. 142–
170.
▪ J. Herve, S. Hamid, L. Bill, K. B. Robert, and S.-V. Alberto. “Implicit state enumeration of
finite state machines using BDD’s.” Computer-aided Design, 1990ICCAD-90. Digest of
Technical Papers. 1990 IEEE International Conference on (1990), pp. 130–133.

2023.

GDS
Lecture 20
Formal Verification- IV
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Formal Verification
Usage
Model Checking Equivalence Checking
▪ Equivalence Checking

Formal Verification
Equivalence
Checking

Equivalence Checking: Usage

Formal Verification : Equivalence Checking (2)
Equivalence Sequential Equivalence Checking
Checking ▪ Generalized approach to comparing two models
▪ First convert models to FSM
Sequential Combinational ▪ Given their initial states, it is checked whether the two
Equivalence Equivalence FSMs produce matching output sequences for all input
Checking (SEC) Checking (CEC) sequences
Challenges of SEC: Combinational Equivalence Checking

▪ Need to explore all reachable ▪ Assume that there is a one-to-one correspondence
states among memory elements or flip-flops and the ports of
➢ Encounters state explosion the two models.
problem ▪ Problem reduced to establishing the equivalence of
➢ Computationally difficult pairs of combinational circuits
▪ Assumption holds in most cases
➢ Integral part of design flows

Formal Verification
Combinational
Equivalence
Checking (CEC)

Combinational Equivalence Checking (CEC): Steps

CEC: Register and Port Matching (Illustration)

CEC: Register and Port Matching (Techniques)
No exact algorithm : heuristics employed module flip_flop_d(d, clk, q);
input d, clk;
Name-based matching: output q;
• Works very well for I/O Ports reg q;
• Works good where a model has not undergone
sequential optimization and register always @(posedge clk) q <= d;
correspondence is kept intact endmodule
• RTL synthesis keeps names of registers based S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge
on some rules/conventions (such as add suffix University Press, 2023.
to the name of signal in the RTL code)
• Sophisticated structural or functional analysis

can also be used
• User can guide the tools to match the registers

CEC: Miter Creation
• Need to ensure that the
corresponding combinational circuits
lying between matched
registers/ports are equivalent
• Derive multiple small combinational
circuits (known as miters) from the
given two models
➢ A separate miter is derived for
each register and output port of
the two models

CEC: Miter and Equivalence
▪ Z=1 for any combination of

{𝑥1, 𝑥2, 𝑥3, … , 𝑥𝑛} ⇒ Model-1 and Model-
2 are not equivalent
▪ Z=0 for all possible combinations of

{𝑥1, 𝑥2, 𝑥3, … , 𝑥𝑛} ⇒ Model-1 and Model-
2 are equivalent

CEC: Illustration
Given two models with ports matched by names.
▪ Let us draw the miter circuit for checking equivalence

of Model-1 and Model-2.
▪ Let us determine patterns of values that can be ▪ A=0, B=1

assigned to ports A and B such that the output of the
miter is 1. ▪ A=1, B=0

CEC: Establishing Equivalence
Using BDDs:
• Build a BDD for a miter,
➢ Equivalent models: reduce to a terminal vertex with the value of 0
➢ Nonequivalent models: yield some other vertex.
Using SAT Solver:
• Invoke a SAT solver on the Boolean expression representing a miter
➢ Equivalent models: UNSAT
➢ Nonequivalent models: SAT
CEC:
• Create miter circuits for all flip-flops and output ports in the models
• For equivalent models, all miter circuits should be equivalent
Safety and False Failures:

• CEC can sometimes give false failures
• Still it is always safe

References
2023.

GDS
Lecture 21
Technology Library
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Till now….
▪ Logic Synthesis:
➢ Transformation of RTL to netlist of generic logic gate
➢ Logic optimization
Subsequently ….
▪ Map generic logic gates to the cells of a given technology library
▪ Perform timing analysis and other types of verification
▪ Need information of the cells contained in a given technology library

Libraries in VLSI Design Flow
Libraries
Technology Library Physical Library
Technology Library: Physical Library:

▪ Introduced for logic synthesis ▪ Contains abstract information about the
▪ Evolved to support various design tasks layout of the cells and technology.
➢ Timing verification, physical ▪ Library Exchange Format (LEF)
implementation, and test activities ➢ ASCII files (.lef extension)
➢ Also referred to as timing library.
▪ Liberty format
➢ ASCII files (.lib extension)

Motivation for using Libraries
▪ Simplifies design task by decomposing the overall design process into two steps:
➢ Creating Library
➢ Using Library
Creating Library: Using Library:

▪ Design each cell at the transistor level ▪ Instantiate cells from a library to achieve
➢ Determine its optimal layout. desired functionality
▪ Extract essential information about the ▪ Allows focusing on their instantiations
cells and write them in the library. ➢ Design time and effort decrease.
▪ Many designs can employ the same ➢ Reduce the chances of errors within
library the cells.
➢ Cost of developing a high-quality ▪ Raises the abstraction from the transistor
library gets distributed over multiple level to the cell level
designs ➢ Makes complex synthesis, static timing
analysis (STA), and physical design
tasks feasible

Library : How are libraries created? (1)
Library Characterization: process of creating the library (at foundry or design house)
▪ Design each cell optimally and verify

▪ SPICE simulations of each cells for:
▪ Given operating condition and stimulus
▪ Transistor model, process (retrieved from
PDKs)
▪ Measure/extract the parameters of interest
such as delay, slew, voltage, capacitance,
power, etc.
▪ Build an abstract model and write in the given
format

Library Models
Why are SPICE simulations using PDKs not directly used for delay/power computation?
▪ SPICE simulations are time taking

➢ Differential equations are formulated and typically solved using iterative techniques
Library models: Requirement of library models:

▪ Relevant information from SPICE simulation ▪ Speed and Accuracy
are extracted and modelled in the library
▪ Robustness
▪ EDA tools use library models instead of
SPICE simulations for computing delay, ▪ Portability
slew, power, voltage variations, etc. ▪ Variety and Uniformity:
➢ Order of magnitude faster than SPICE ➢ Multiple cells for same function
simulation and of reasonable accuracy ➢ Low Power, High Performance, High
Density, Low-VT, High-VT
➢ Height uniform, width variable

Library: Content
▪ Process parameters, Voltage, ▪ Libraries typically contains cells with
Temperature (collectively called PVT hundreds of different logic functions:
conditions) ➢ Combinational/sequential standard
▪ Cell data: cells
➢ Pins, functionality ➢ I/O Pads
➢ Timing, area and power information ➢ Memories, macros
When do we use libraries?
▪ Libraries are used throughout RTL to GDS flow

➢ Synthesis, timing and power analysis, verification, Design For Test (DFT), physical
design

Library: Liberty format (1)
▪ Liberty format is simple ASCII/text format
▪ Data is primarily stored as attributes

➢ Mapping between an attribute name and its value
➢ Example: time_unit : “10ps”;
▪ Information is organized as a hierarchy of groups
▪ At the top level it has a Header
▪ Header contains:
➢ PVT conditions, scaling factors, units
➢ Information that are valid for all the cells/pins/arcs
➢ List of cells

Library: Liberty format (2)
▪ Cell contains:
➢ Area
➢ Cell Leakage Power
➢ List of pins
▪ Pin contains:
➢ Direction
➢ Capacitance
➢ Functionality (for output pins)
➢ List of timing arcs
➢ List of power arcs
▪ Timing arcs are used to perform timing analysis or

computing delays of the arcs
▪ Power arcs are used to perform power analysis

Technology Library
Modelling Delay

Library : Timing Arcs
▪ Timing Arcs are used to model timing attributes for
combinational or sequential cells in a library
Each Timing Arc has:
▪ Start Pin and End Pin
▪ Timing arc is specified on the End Pin
▪ Start Pin is specified using the attribute related_pin
Timing Arcs can be of type:
▪ Delay Arc
▪ Constraints Arc (setup check, hold check etc.)

Slew Definition
▪ Slew of a signal quantifies how steeply or sharply
transition occurs from “0” → “1” or “1” → “0”
Slew measured by defining two transition points:

▪ Lower threshold percentage (LTP)
▪ Upper threshold percentage (UTP)
10-90 Threshold:
▪ Rise slew: time taken for a signal to reach from 10%
to 90% of supply voltage
▪ Fall slew: time taken for a signal to reach from 90%
to 10% of supply voltage
▪ Slew threshold of 20-80, 30-70 can also be used
▪ Also called: rise transition time, fall transition time,

rise time, fall time

Delay Definition
▪ Quantifies how much time it takes for the change in input to propagate to the output
Delay can depend on the direction of transition

(rising/falling)
▪ Rise delay: output rising
▪ Fall delay: output falling
▪ Predefined threshold points on the input

waveform and the output waveform.
▪ For the input signal:
➢ input rise threshold percentage (IRTP)
➢ input fall threshold percentage (IFTP).
▪ For the output signal:
➢ output rise threshold percentage (ORTP)
➢ output fall threshold percentage (OFTP)

CMOS : Characteristics of Slew and Delay
▪ In general, the delay (𝐷) and output slew (𝑆𝑂𝑈𝑇 ) of a given timing
arc depend on:
➢ Input Slew (𝑆𝐼𝑁 )
➢ Output Load (𝐶𝐿 )
▪ The relationship may be non-linear:

➢ 𝐷 = 𝑓(𝑆𝐼𝑁 , 𝐶𝐿 )
➢ 𝑆𝑂𝑈𝑇 = 𝑔(𝑆𝐼𝑁 , 𝐶𝐿 )
➢ 𝑓, 𝑔 are non-linear function (typically monotonically increasing
▪ Modelled with 𝑆𝐼𝑁 and 𝐶𝐿 )
approximately as
two dimensional
discrete point ▪ Intermediate values are
tables interpolated from closest
match
▪ Different tables for delay and
output-slew

Non-linear Delay Model (NLDM)
u_table_template(index_1) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( "10, 20, 30" ) ;
index_2( "1.2, 5.0,15.0, 37.5) ;
}
….
pin(Z) {
timing() {
related_pin : “A" ;
timing_sense : positive_unate ;
cell_rise(index_1) {
values( " 4, 5, 7, 12, …3x4 table);
}
…
}
}
Library : Advanced Delay Model
▪ At advanced process nodes simple NLDM model is not accurate
▪ Other delay models based on current source model are employed

➢ Composite Current Source (CCS)
➢ Effective Current Source Model (ECSM)

Technology Library
Modelling
Setup/Hold

Setup/Hold Time : Definition
▪ Setup time: minimum amount of time the DATA

signal should be held steady before the CLOCK
edge so that the DATA is sampled correctly and
deterministically
▪ Hold time: the minimum amount of time the

DATA signal should be held steady after the
CLOCK edge so that the DATA is sampled
correctly and deterministically

CMOS : Setup/Hold Characteristics
▪ In general, the setup (SU) and hold (H) constraints depend on:
➢ Data Slew (𝑆𝐷 )
➢ Clock Slew (𝑆𝐶𝐿𝐾 )
▪ The relationship may be non-linear:

➢ 𝑆𝑈 = 𝑓(𝑆𝐷 , 𝑆𝐶𝐿𝐾 )
➢ 𝐻 = 𝑔(𝑆𝐷 , 𝑆𝐶𝐿𝐾 )
➢ 𝑓, 𝑔 are non-linear functions
▪ Modelled as two dimensional discrete point tables
▪ There are different tables for setup and hold

Library : Modelling Setup/Hold Constraints
u_table_template(index_1) {
variable_1 : constrained_pin_transition;;
variable_2 : related_pin_transition;
index_1( "10, 20, 30" ) ;
index_2( "10, 20, 30, 40) ;
}
….
pin(D) {
timing() {
▪ Intermediate values are interpolated related_pin : “CP" ;
from closest match timing_type : "setup_rising";
rise_constraint(index_1) {
values( " 4, 5, 7, 12,
…3x4 table);
}
…
}
}

Library : Other information contained in library
▪ Power Models
▪ Models for crosstalk noise analysis
▪ Power/Ground Pin Information
▪ State dependent arcs: sdf_cond, when
▪ Other attributes that may be vendor specific

References
▪ Synopsys Inc. “Liberty.” https://www.synopsys.com/community/interoperability-programs/tap-
in.html.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023.
▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A practical
approach. Springer Science & Business Media, 2009.

GDS
Lecture 22
Static Timing Analysis – Part I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
Static Timing Analysis (STA)

▪ Basics of STA (this lecture)
▪ Subsequent Lectures:
➢ Mechanics of STA
➢ Advanced concepts of STA
➢ Constraints

Static Timing
Analysis
Basics

Static Timing Analysis (STA): What is done?
▪ Ensures that the circuit is in a valid state at each STA Simulation
clock cycle
▪ Verifies that the design is capable of operating at No test-vector Test vector

the given frequency required required
➢ Information of frequency comes from
constraints
No check of Checks
▪ Ensures that the design does not have setup or functionality functionality
hold violation at flip-flop
Analysis Simulation done
performed taking based on
▪ The analysis is based on worst case scenario and pessimistic view of specified test
takes a pessimistic view wherever possible delays and other vectors and
➢ Verification is done without test vector and attributes of the delays
simulation (therefore static) design
➢ Ensures that design will not have setup or
hold violations for any test vector

Synchronous Circuit: Data Propagation
Consider a synchronous circuit shown alongside.
Assume that:
▪ Flip-flops are ideal
▪ Buffers have some delay
▪ Inputs at the port IN are applied as shown [using
identifiers for clarity]
▪ State defined by the combination of values at the
Q-pin
▪ Initial state is {PQ}
Let us understand the behavior of the circuit in

different clock cycles for various cases of delay of
the buffers.

Synchronous Circuit: Synchronous Behavior
Assume that:
▪ Delay of D1, D2, and D3 be some finite value less than
the clock period, and
▪ Delays of C1 and C2 are negligible.
These are valid states of a

synchronous circuit.

Synchronous Circuit: Zero Clocking
Assume that:
▪ Delay of C1 and C2 are negligible.
▪ Delay of the circuit element D2 is more than
one clock period, but less than two clock
periods.
▪ Delay of D1 and D3 are minimal.
▪ In effect clock fails to capture the right data

(zero-clocking) due to late data arrival
▪ The circuit goes into invalid states
Synchronous Circuit: Double Clocking
Assume that:
▪ Delay of circuit elements D1, D2, D3, and C1
are insignificant.
▪ Delay of the circuit element C2 is ∆
▪ In effect, the data gets captured by two flop-flops

by the same clock edge (double clocking)
▪ The circuit goes into invalid states
Synchronous Circuit: Verification
To ensure synchronous behavior:
▪ Avoid Zero Clocking: setup analysis or late analysis
▪ Avoid Double Clocking: hold analysis or early analysis
▪ A synchronous circuit can contain many flip-flops
➢ Data can propagate sequentially through a pipeline before reaching the output
▪ Examine each pair of launch and capture flip-flops separately
▪ Various types of combinational gates can be
encountered in a path
▪ Add the delay of all the combinational circuit
elements (and also the wire delay) in the path
and check for delay requirements
▪ Real flip-flops have ST, HT, CK-Q delay

▪ Account for them (make the verification a bit
more pessimistic)

Static Timing Analysis (STA) : Setup Requirement (1)
▪ Ensures that the data sent by launch
flip-flop in a given clock cycle is
captured reliably by the capture flip-flop
in the next clock cycle
▪ Ensures that the setup requirement of

the flip-flop is also met
Arrival Time of data at the D-pin: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 = 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎
Required time for data to settle at FF2/D: 𝑡𝑟𝑒𝑞,𝑠𝑒𝑡 = 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐
To avoid zero clocking and setup-time constraints of flip-flops: 𝑡𝑟𝑒𝑞,𝑠𝑒𝑡 > 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙
Setup requirement: 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 > 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎

Static Timing Analysis (STA) : Setup Requirement (2)
Setup Violations can occur if:
▪ Clock Period is decreased
(clock frequency is
increased)
▪ Delay of capture clock path
is decreased
▪ Delay of data path is
increased
▪ Delay of launch clock path
is increased
Setup requirement:
𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 > 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎
𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > (𝑇𝑙𝑎𝑢𝑛𝑐ℎ −𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 ) + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 What happens for an ideal
flip-flop?
𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 [𝛿𝑙𝑐 is the clock skew] What happens for an ideal
clocking structure?
Most Restrictive:
𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎,𝑚𝑎𝑥 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐
Static Timing Analysis (STA) : Hold Requirement (1)
▪ The hold check is from one active edge
of the clock in the launch flip-flop to the
same clock edge at the capture flip-flop
(independent of clock-period)
▪ Ensures that the hold requirement of the

flip-flop is also met
Data Reaches D-pin: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 = 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎
Data to arrive at FF2/D after the required time: 𝑡𝑟𝑒𝑞,ℎ𝑜𝑙𝑑 = 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐
To avoid double clocking and hold-time constraints of flip-flops: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 > 𝑡𝑟𝑒𝑞,ℎ𝑜𝑙𝑑
Hold requirement: 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐

Static Timing Analysis (STA) : Hold Requirement (2)
Hold requirement:
𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐
𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇ℎ𝑜𝑙𝑑−𝑐
Most Restrictive requirement:

𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎,𝑚𝑖𝑛 > 𝑇ℎ𝑜𝑙𝑑−𝑐
▪ Hold Violations can occur if:

What happens for an ideal
▪ Delay of data path is decreased flip-flop?
▪ Delay of launch clock path is decreased What happens for an ideal
▪ Delay of capture clock path is increased clocking structure?

References
2023.

GDS
Lecture 23
Static Timing Analysis – Part II
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Mechanism of Static Timing Analysis

Static Timing Analysis: Definitions
STA considers two types of paths: Data Path:
1. Data Path ▪ Timing startpoints: input ports or
2. Clock Path clock-pin of a flip-flop
▪ Goes through combinational circuit
elements
▪ Timing endpoints: D-pin of a flip-flop
or output ports
➢ Setup and hold checks are
performed at the timing
endpoints
Clock Path:
▪ Starts at clock source (specified in
constraints)
▪ Four data paths ▪ Passes through the combinational
circuit elements (buffers and
▪ Two clock paths inverters)
▪ Ends at a clock-pin of a flip-flop
Static Timing
Analysis
How it works

Timing Graph (1)
STA starts with building a Timing Graph for a given circuit
▪ Timing Graph: is a directed acyclic graph

➢ 𝐺 = (𝑉 , 𝐸), where 𝑉 is the vertex set and 𝐸 is the
edge set.
▪ The vertex 𝑣 ∈ 𝑉 corresponds to a pin or a port in the
circuit.
▪ An edge 𝑒 ∈ 𝐸 represents a timing arc in the circuit

➢ An edge 𝑒𝑖,𝑗 = (𝑣𝑖 , 𝑣𝑗 ) exists in 𝐸 if and only if there ▪ Each edge 𝑒𝑖,𝑗 has annotated
exists a timing arc between the corresponding pins information of delay 𝐷𝑖,𝑗
or ports in the circuit. (computed by Delay
Calculation)
Two types of edges:
▪ Cell Arc: Timing arc between two pins of the same cell ▪ Each vertex in the graph has
arrival time, required time,
▪ Net Arc: Timing arc between two pins of different cells slack, etc.
that are connected directly by a net

Timing Graph (2)
Source: vertices with no incoming
edges
▪ Timing startpoints (input ports,
clock-pin of FFs) and clock start
points treated as sources
Sink: vertices with no outgoing

edges
▪ Timing endpoints (output ports, D-
pin of FFs) treated as sinks

Delay Calculation: Stage
STA needs to know the delays for the timing arcs existing in the timing graph
▪ Retrieves it from a delay calculator
▪ Inbuilt or coupled with an STA tool
▪ Decomposes a given circuit into separate stages
▪ A stage is composed of a driving cell and its driven pins connected through wires.

Delay Calculation: Essential Components
Driver model: NLDM, CCS, ECSM
Interconnect:
▪ Zero capacitance models, parasitic
extraction
▪ Interconnect delay model: Lumped
Capacitance, Elmore, Asymptotic
Waveform Evaluation (AWE)
Receiver model: capacitance, or

more advanced
▪ Given a stage, we can compute the output waveform once we know the input waveform
▪ Delay calculation can be done in topological order (from input to output)

▪ Transition at input ports obtained using SDC or assumed by a tool
▪ Each edge 𝑒𝑖,𝑗 has annotated information of delay 𝐷𝑖,𝑗 and slew 𝑆𝑖,𝑗
Arrival Time Computation: Basic Concept
Arrival Time (AT): time at which a signal settles at a given vertex
When there is only one incoming edge: 𝐴𝑗 = 𝐴𝑖 + 𝐷𝑖𝑗
When there are multiple incoming edges:

▪ Can associate different arrival time for different
edges
▪ Value at a vertex can toggle multiple times before
settling
▪ A bound on the arrival time at a given vertex 𝑣𝑗 can

be computed if the arrival times at all its input
vertices 𝑣𝑖 are known:
▪ 𝑨𝒋,𝒎𝒊𝒏 = 𝑴𝒊𝒏(𝑨𝒊,𝒎𝒊𝒏 + 𝑫𝒊𝒋 )
▪ 𝑨𝒋,𝒎𝒂𝒙 = 𝑴𝒂𝒙(𝑨𝒊,𝒎𝒂𝒙 + 𝑫𝒊𝒋 )

Arrival Time Computation: Method
▪ Arrival Time (AT) is computed and stored at each vertex in a timing graph
▪ AT at input ports specified by constraints or assumed to be zero
▪ AT computation is done by Forward Traversal of Timing Graph
▪ AT computation starts from the vertices corresponding to input ports
▪ A vertex is chosen for computing AT such that:

▪ All the input vertices of the given vertex have their AT already computed
▪ AT can be computed in one traversal of the vertices and edges of the timing graph

Maximum Arrival Time Computation: Illustration
1
0 4 5
3 8 9
7
0 1 2 3 4
5
6 7 8 9
0 1
▪ Assume that delay of all the edges = 1 time unit ▪ Similarly, minimum arrival time
computation can be done
▪ Assume that AT is 0 at all sources

Arrival Time Computation : Complications
▪ Rise/Fall Delays:
▪ Separate AT is computed for rise/fall cases
▪ Dependence of delay on the input slew (rise/fall transition time)

▪ Slew is also propagated and stored at each vertex, in addition to delay

Required Time Computation: Basic Concept
Required Time (RT): time constraint for a given vertex to avoid setup/hold violation
▪ Setup/Late analysis: the maximum time by which a signal should arrive to avoid violation
▪ Hold/Early analysis: the minimum time after which a signal should arrive to avoid timing
violation
▪ Required time for a vertex 𝑣𝑖 can be computed

if required times at all its output vertices 𝑣𝑗 are
known:
➢ 𝑹𝒊,𝒉𝒐𝒍𝒅 = 𝑴𝒂𝒙(𝑹𝒋,𝒉𝒐𝒍𝒅 − 𝑫𝒊𝒋 )
➢ 𝑹𝒊,𝒔𝒆𝒕𝒖𝒑 = 𝑴𝒊𝒏(𝑹𝒋,𝒔𝒆𝒕𝒖𝒑 − 𝑫𝒊𝒋 )

Required Time Computation: Method
▪ At each vertex in the Timing Graph Required Time (RT) is computed and stored
▪ RT at output ports or timing end-points is specified or inferred from constraints
▪ RT computation is done by Backward Traversal of Timing Graph
▪ RT computation starts from the vertices corresponding to output ports
▪ A vertex is chosen for computing RT such that:

➢ All the output vertices of the given vertex have their RT already computed
▪ RT can be computed in one traversal of the vertices and edges of the timing graph
▪ Delay of cell/net arcs calculated during AT computation is reused in RT computation
▪ RT constraints primarily determined by clock period

Required Time Computation: Setup Analysis
8
7 9 10
8
11 12
10
2 3 4 5 6
7
8 9 10 11
6 7
▪ Assume that delay of all the edges = 1 time unit ▪ Similarly, required time for hold
analysis can be computed
▪ Assume that RT is 11 and 12 as shown at the sinks

Slack Computation
Setup or Late Analysis:
▪ 𝑆𝑙𝑎𝑐𝑘 = 𝑅𝑇 − 𝐴𝑇
▪ Slack is the time by which AT at a vertex can be increased without causing setup violation
➢ AT can be increased till slack becomes zero
Hold or Early Analysis:

▪ 𝑆𝑙𝑎𝑐𝑘 = 𝐴𝑇 − 𝑅𝑇
▪ Slack is the time by which AT at a vertex can be decreased without causing hold violation
➢ AT can be decreased till slack becomes zero
A negative slack implies that:

▪ Setup/Hold violation exists in the circuit
▪ Need to fix the circuit for proper operation

Slack Computation: Illustration
1
0 4 5
3 8 9
7
0 1 2 3 4
5
6 7 8 9
0 1
8
7 9 10
8
11 12
10
2 3 4 5 6
7
8 9 10 11
6 7
References
2023.
▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A
practical approach. Springer Science & Business Media, 2009.

GDS
Lecture 24
Static Timing Analysis – Part III
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Slew Propagation
▪ Accounting for Variations

Static Timing
Analysis
Slew
Propagation

Need for Slew Propagation
▪ For computing delays for a given stage, the slews at its inputs must be known.
➢ An STA tool must also propagate the slews in the timing graph
▪ The propagated slews can be different through different combinational paths.

Relationship between Slew and Delay
▪ Delay and the output slew are typically monotonically nondecreasing functions of the input
slew
▪ Allows computing, storing, and propagating only the minimum/maximum slews

➢ Can obtain the bounds on the delay and the output slews using the bounds on the input
slews.

Slew Propagation: Bound on Slew
▪ 𝐴𝑗,𝑚𝑖𝑛 = 𝑀𝑖𝑛 𝐴𝑖,𝑚𝑖𝑛 + 𝐷𝑖𝑗,𝑚𝑖𝑛
▪ 𝐴𝑗,𝑚𝑎𝑥 = 𝑀𝑎𝑥 𝐴𝑖,𝑚𝑎𝑥 + 𝐷𝑖𝑗,𝑚𝑎𝑥
▪ 𝑆𝑗,𝑚𝑖𝑛 = 𝑀𝑖𝑛 𝑂𝑆𝑖𝑗,𝑚𝑖𝑛
▪ 𝑆𝑗,𝑚𝑎𝑥 = 𝑀𝑎𝑥 𝑂𝑆𝑖𝑗,𝑚𝑎𝑥

Slew Propagation: Example (Maximum Case)
▪ 𝐴𝑦,𝑚𝑎𝑥 = 𝑀𝑎𝑥 100 + 50, 20 + 80 = 150 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 150 + 100 = 250

▪ 𝑆𝑦,𝑚𝑎𝑥 = 𝑀𝑎𝑥 10,30 = 30 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 20
▪ Graph-based Analysis (GBA): Safe Bound, Not tight (most popular)
▪ 𝐴𝑦,𝑚𝑎𝑥 = 150 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 180 ▪ 𝐴𝑦,𝑚𝑎𝑥 = 100 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 200

▪ 𝑆𝑦,𝑚𝑎𝑥 = 10 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 10 ▪ 𝑆𝑦,𝑚𝑎𝑥 = 30 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 20
▪ Path-based Analysis (PBA): Path-specific, computationally difficult

Static Timing
Analysis
Accounting
for Variations

Need to Account for Variations
▪ Behavior of transistors/circuit elements can differ from the nominal behavior due to
process-induced variations and fluctuations in temperature and voltage (PVT variations)
➢ Delay and other timing attributes change
➢ Can result in timing failure
▪ To tackle variations, different techniques are employed.

➢ Differ in accuracy, modeling effort, computational resource requirement, and design
effort.

Safety Margins
▪ Easiest technique
▪ Can convey margins to an STA tool using appropriate constraints
➢ Adjust the required time such that timing requirements become stricter
▪ Large Margin: overly pessimistic (loss in PPA)

▪ Small Margin: chance of timing failure, yield loss
▪ Need to consider these tradeoffs
▪ Typically employed in early stages of VLSI design flow

Multi-mode Multi-Corner (MMMC) Analysis
▪ Carry out STA at some discrete set
of scenarios to account for
variations
Scenarios are created by a

combination of:
▪ PVT corners for technology libraries:
accounts for global variations (worst,
best, typical, etc.)
▪ Multiple modes: using SDC files for
different modes such functional, test,
sleep, turbo, etc. ▪ Analyze multiple scenarios simultaneously using
▪ RC corners: extract multiple SPEF MMMC analysis
files to account for process-induced ▪ Efficiency:
variations in interconnects.
➢ Avoiding computation of the dominated
scenarios
➢ Exploiting parallel processing

On-Chip Variations (OCV) Derate
▪ Need to account for local variations in Late path derating factor = 1.1
the properties of devices and
Early path derating factor = 0.9
interconnects on the same die
➢ Specify OCV derate factors
Setup Analysis:
▪ Effective delay: obtained by multiplying ▪ Data path and clock launch path: 1.1
the nominal delay with the OCV derating ▪ Clock capture path: 0.9
factor
Hold Analysis:
Can define different OCV derating factors ▪ Data path and clock launch path: 0.9
based on:
▪ Clock capture path: 1.1
▪ Path bounds (early or late)
▪ Path type (data or clock) Demerit:
▪ Delay type (gate delay or interconnect ▪ Assumes perfect positive correlation
delay) among timing arcs of same group
▪ Corners (best, worst, typical, etc.) ▪ Assumes perfect negative correlation
among timing arcs of different group
▪ Overly pessimistic
References
2023.

GDS
Lecture 25
Constraints I
Sneh Saurabh
Engineering
IIIT Delhi
Lecture Plan
▪ Basics of constraints
▪ Clock constraints
▪ Input/Output constraints
▪ Timing exceptions

Constraints: Basics
Constraints are: create_clock -period 10 -waveform {5 10}
▪ Requirements of a design that needs to be [get_ports CLK]
honoured or attempted to be honoured by the set_clock_transition -rise 0.1 [get_clocks CLK]
CAD tools
set_clock_uncertainty 0.2 [get_clocks CLK]
▪ Information about a design that could
potentially be exploited by the CAD tools to set_input_delay -clock CLK 3.0 [get_ports
improve the PPA of the design INPA]
set_output_delay -clock CLK 3.0 [get_ports
▪ Constraints are normally specified in Synopsys INPA]
Design Constraints (SDC)
set_false_path –from [get_ports TE]
▪ ASCII format written in Tool Command
Language (TCL) set_multicycle_path –from [get_ports mult_out]

Constraints: Application
▪ Most of the constraints are related to timing of a design (also called timing constraints)
➢ Employed by implementation tool to gather information about the expected timing
behavior
➢ Employed by STA tool to verify timing

Constraints: What is the origin?
Constraints are normally manually written

▪ Designer have the knowledge of design goals and environmental constraints
▪ There are certain tools for automatic constraints generation
➢ Some user intervention is always required
It is important to write correct constraints

▪ Otherwise design implementation tools can produce unexpected results
▪ There should be consistency between different constraints
▪ Constraints should be consistent with design attributes

Constraints: Types
Clock signal
▪ Attributes of a clock signal such as frequency, duty cycle, skew, uncertainty and delay
Environment under which the design operates
▪ Attributes of external incoming signal and expected behavior of the signals produced by a
design
Functionality of the design (informative)
▪ Timing exceptions (paths that are false and paths that are allowed to behave differently
than traditional synchronous behavior), modes of design
Design rules and optimization constraints
▪ Maximum slew at the port, maximum capacitance at a pin, and soft constraints

Constraints
Clock Signal

Clock Constraints: Sources
Two types of clock sources
▪ Primary clock sources: waveform
independent of other clock sources
in that design
▪ Derived clock sources: waveform
depends on other clock sources
▪ Master clock: clock from which we

derive another clock is known as the
master clock of the derived clock
➢ CS1 is the master clock source
of CS2

Primary Clock Source Definition
create_clock: defines the primary clock source in a design
current_design MyComp
create_clock -name EXT_CLK -period 10 -waveform {0 4}
[get_ports clk_in]
create_clock -name INT_CLK -period 10 [get_pins CS1/clk_g]
-waveform: time when the clock edges occur, starting

from rise-edge

Derived Clock Source Definition
create_generated_clock: define derived clock sources
create_clock -name CLK -period 10 [get_pins

CS1/CLK]
create_generated_clock -name GCLK -divide_by 2
–source [get_pins CS1/CLK] [get_pins CS2/GCLK]

Attributes of Clock Signal: Latency
set_clock_latency: specify clock latency
create_clock -name CLK -period 200 [get_ports clk_port]

set_clock_latency 5 -source [get_clocks CLK]
set_clock_latency 10 [get_clocks CLK]

Attributes of Clock Signal: Uncertainty
set_clock_uncertainty: unpredictable deviation of the clock edges from the ideal value
Clock uncertainty can be used to model:
▪ Jitter: temporal variation
▪ Skew: spatial variation
▪ Safety margins

set_clock_uncertainty 15 -hold [get_clocks CLK]
set_clock_uncertainty 20 -setup [get_clocks CLK]

Attributes of Clock Signal: Transition
set_clock_transition: specify an estimated clock transition time

set_clock_transition 10 [get_clocks CLK]

References
2023.

RTL 2 GDS2

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VLSI DESIGN FLOW: RTL TO

▪ Designing vs. Fabrication

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Charles Babbage, On the Economy of Machinery and

“…sources of excellence in the work produced by machinery

The principle alluded to is that of COPYING, taken in its

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6

▪ Diffusion layer, implant layer,

▪ Above devices: interconnect

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7

Connect points A1 to A2 and B1 to B2 using wires.

▪ Wires cannot go outside the rectangle shown.

▪ The wires are constrained to be in the plane containing

What happens when the constraint of wires being in the

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

▪ Layers defined by mask and fabricated using photolithography

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

▪ Features marked on a glass plate with opaque

▪ For different layers of integrated circuits different

▪ Photolithography is carried out for each layer

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 11

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 12

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 13

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 14

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 15

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 16

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 17

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 18

Design and Fabrication:

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 20

inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

Basic Concepts of Integrated Circuit

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

▪ Methodology to design an IC such that it delivers the required functionality or behavior.

What decides VLSI Design Flow?

▪ The VLSI design flows depends on the type of integrated circuits:

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 5

Types of Integrated Circuit based on

Application Specific General Purpose Integrated

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6

Application Specific General Purpose Integrated

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

Full-custom Standard-cell Gate-array FPGA based

▪ FPGA: Field Programmable Gate Array

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9

▪ Huge design effort

▪ Very few designs are full-custom

▪ Analog mixed/signal designs

▪ High volume products such as microprocessors (some portion)

▪ Merit: design can be highly optimized

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

▪ Macros: complex cells such as full-adder,

▪ Allows high degree of automation

▪ Rows of standard cells with interconnection in between

▪ Custom blocks can also be embedded in a design

▪ Types, locations and interconnections of standard-cells are design specific

▪ Designer define only the interconnection between transistors: