Embedded Systems[18EC62]

ARM CORTEX M3 PROCESSORS

Presentation by
Mamatha NP
1.1 MICROPROCESSORS AND MICROCONTROLLERS
1.2. RISC AND CISC CPU ARCHITECTURES

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1.2. HARVARD & VON- NEUMANN CPU ARCHITECTURE

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 ARM Architecture
• Advanced RISC Machine(ARM)
• Reduced Instruction Set Computer
– Architecture
– Organization
– Advantages
– RISC Drawbacks

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 RISC Architecture
• A fixed (32)bit instruction Size. (CISC Processors have
variable length instruction sets with many formats.)
• A Load Store Architecture : Instructions that process
data, operate only on registers. Instructions that
access memory are separate.
• Thirty two registers , each of 32 bit, used for many
purposes. The load store architecture operates
efficiently.

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 RISC Organization
• Hardwired instruction decoded logic; (CISC
uses large microcode ROMS to decode their
instructions)
• Pipelined Execution; (CISC Allowed very little
overlap)
• Single cycle execution; (CISC took many clock
cycles to complete a single instruction)

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 RISC Advantages
• A smaller die size: fewer transistors and
less silicon area.
• A short development time
less design time, lower cost
• A higher performance due to high clock
rate with single cycle execution

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 RISC Draw backs
• RISCs have poor code density
• RISCs do not execute x86 instructions

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 Chapter 1 ARM CORTEX M3 Processors

• Greater Performance efficiency

• Low power consumption
• Enhanced determinism
• Improved code density
• Ease of use
• Lower cost solutions
• Wide choice of development tools

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Background of ARM and ARM Architecture

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 Architecture Versions:
• A Profile (ARMv7-A): Application processors which are
designed to handle complex applications such as high-end
embedded operating systems (OSs) Example products
include high-end mobile phones and electronic wallets for
financial transactions.
• R Profile (ARMv7-R): Real-time, high-performance
processors targeted primarily at the higher end of the real-
time1 market—those applications,
• M Profile (ARMv7-M): Processors targeting low-cost
applications in which processing efficiency is important and
cost, power consumption,.
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 ARM CODE DENSITY AND THUMB
• ARM Processor design is based on RISC
principles
• To increase the Code density ARM incorporates
a mechanism called THUMB Architecture
• Thumb instruction set is a 16 bit compressed
form of the original 32 bit ARM instruction set.
Thumb code density is better than CISC.

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 ARM Architecture
• Load Store Architecture
• Fixed Length 32 bit instructions
• Three address instruction formats
• Eg ADD R0,R1,R2; R0 = R1 + R2

• Eg of ARM : ARM7TDMI

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The Thumb-2 Technology and Instruction Set
Architecture:

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Architecture of ARM Cortex M3:

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 Processor Naming
ARM 7TDMI Processor, ARM 1136J(F)-S
T-Thumb instruction support
F –Floating Point Arithmetic Support
D- JTAG Debugging
M-Fast Multiplier
I –embedded In Circuit Emulator(ICE) module
E – Enhanced DSP instructions
26/36 – with cache and MMU
46- with MPU
J – Jazelle (Java support)
S- Synthesizable ( A synthesizable core design in HDL and can be
converted to a design netlist using synthesis software.
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 Evolution of ARM Processor Architecture
• ARM7TDMI : ARM v4T - T for Thumb Instruction
support
• ARM 926E-S : ARM v5E –Enhanced Digital Signal
Processing instructions
• ARM11 : ARMv6: included SIMD instructions. (ARMv6
architecture introduced a small set of SIMD
instructions, operating on multiple 16-bit or 8-bit
values packed into standard 32-bit general purpose
registers. This permits certain operations to execute
twice or four times as quickly, without implementing
additional. The idea is to load up multiple pieces of
data and perform an operation across all of the data at
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 Evolution of ARM Processor Architecture

• CORTEX M3: ARMv7: 3 architecture designs,

– A profile : high performance open application
– R profile: high end Embedded systems with real time
performance
– M profile: designed for deeply embedded microcontroller type
systems
• Key area of ARM v7 architecture:
– Programmers Model
– Instruction Set
– Memory model
– Debug Architecture
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Evolution of ARM Processor Architecture

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 CORTEX M Processor Family
M0,M0+,M1 : ARM v6-M Architecture
• Small instruction set
• Small size (12K gates 2 input NAND gates)
• Ideal for low cost microcontroller products
• Low power optimization

M3 and M4 : ARMv7-M Architecture

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 CORTEX-M PROCESSORS
• CORTEX M1 :
– designed for FPGA Applications.(Tightly Coupled
Memories)
– High Clock Frequency (Over 200MHZ)
• CORTEX M0 and M0+
– Excellent Energy Efficiency due to low gate count
– But takes more instructions and clock cycles for
complex data processing.

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 Differences between a Processor and a
Microcontroller
• ARM does not make microcontrollers
• ARM designs only processors component IPs
and licenses them to Microcontroller vendors

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Microprocessor and Microcontroller

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APPLICATIONS of the CORTEX M Processors

• For design of Microcontrollers:

• Low Cost,
• small memory size
• high performance
• high operation speed
• Automotive :
– great performance
– high energy efficiency
– Low interrupt Latency (for RTS), 240 interrupts
– Robust MPU(Mem Protection Unit)
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APPLICATIONS of the CORTEX M Processors

• DATA Communications: (Blue Tooth and

Zigbee)
– Low Power
– High Efficiency
– Thumb – 2 Technology
– Bit Field Manipulations

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APPLICATIONS of the CORTEX M Processors

• Industrial Control:
• Simplicity, Fast response and reliability
• Interrupt support Features
• Automated Nested Interrupt Handling
• MPU
• Enhanced Fault Finding
• Consumer Products:
Ability to use one or more Microprocessors
small, highly efficient and low in power

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APPLICATIONS of the CORTEX M Processors

Systems on Chip(SOCs) used in

Audio Processing, Power Management Systems
and in Finite State Machines(FSM)

Mixed Signal Designs:

Analog and Digital designs are converging.
Microcontrollers contain more analogue
components such as ADC, DAC , analog IC
sensors, Power Management IS(PMIC) and MEMS

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Chapter 2

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ARM CORTEX M3 ARCHITECTURE

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BLOCK DIAGRAM

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 ARCHITECTURAL BLOCK
1. Core of the Processor
2. Nested Vectored Interrupt Controller
3. SysTick Timer
4. Floating Point Unit(M4)
5. Internal Bus Systems
6. Memory Protection Unit(MPU)
7. Software Debug Components

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 FEATURES of CORTEX M3 and M4 Processors

1. Three stage pipeline design

2. Harvard Bus Architecture with Unified Memory Space:
Instruction and data in same address space
3. 32 bit addressing: supports 4 GB memory space
4. On-chip bus interface based on AMBA Technology
5. Interrupt Controller: NVIC( Nested Vectored Interrupt
Controller(supports 240 ints, 8 to 256 Priority levels)

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 FEATURES of CORTEX M3 and M4 Processors

6. Optional MPU(Memory Protection Unit)

7.Bit Data Access: Bit Banding(two memory Regions)
8. Single and Multiprocessor design. ISA (Instruction
Set Architecture provides wide range of instructions)
9. Memory Access Instructions support 8bit,
16 bit,32 bit and 64 bit data
10. Instructions for bit field processing

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FEATURES of CORTEX M3 and M4 Processors

11. Multiply Accumulate and Saturate

Instructions(MAC)
12. Instructions for branches, conditional branches
and function calls
13. Instructions for system control OS support etc
14. Sleep mode support and various low power
features

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 Difference between CORTEX M3 and M4
Processors
• In Addition CORTEX M4 Processor Supports:
– Single Instruction Multiple Data(SIMD)
– Additional fast MAC and multiply instructions
– Saturating Arithmetic instructions (for DSP
Applns)
– Optional Floating Point Instructions

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 ARM CORTEX M3 and M4
SUMMARY
• 32 bit RISC: 32 bit registers, 32 bit data path,
32 bit bus interface( can handle 8,1,32 and 64
bits)
• Three stage Pipeline design( Fetch Decode and
Execution)
• Harvard Bus architecture(Simultaneous
instruction fetches and data accesses)
• Memory 4GB address space( 32 bit address
bus)
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 LOAD STORE ARCHITECTURE
• Load Store Architecture: Data needs to be loaded
from Memory, Processed and written back to
memory. Eg to increment a data value stored in
SRAM.
• One instruction to read from memory to a register
• One instruction to increment the value of the
register
• One instruction to write the value back to
memory
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 Processor Architecture:
Architecture and Micro Architecture
• Architecture : ISA, Programmers model( what
the software sees) and debug
methodology( what the debugger sees)
• Micro Architecture: Implementation Specific
Details such as interface signals, Instruction
execution timing, Pipeline stages and Micro
architecture is processor design-specific

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 Instruction Set
• Thumb: Allows 16 bit and 32 bit instructions
High Code Density
High Efficiency

In classic ARM Processors such as 7TDMI two states were there :

32 bit Arm and 16 bit Thumb
Switching between ARM and THUMB Code:
1. Execution time increases
2. Instruction count increases.(BLX ,Branch, Link and Xchange)
3. Software compilation complexity increases

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 THUMB- 2 Technology in M3 and M4

• Thumb Instruction set has been extended to

support both 16 bit and 32 bit instructions
without switching.
• CORTEX M processors do not support 32 bit
ARM instructions at all, even interrupt
processing is handled entirely in THUMB State

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 SWITHCHING BETWEEN ARM AND THUMB
CODE

Switching between ARM Code and Thumb Code in Traditional ARM Processors Such as
the ARM7.

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 THUMB -2 Technology
• No state switching overhead, saving execution
time and instruction space.
• No need to specify ARM state or THUMB
State, making Software Development Easier
• Easier to get the best code density, efficiency
and performance at the same time.

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 Configurable Blocks
1. MPU-optional
2. Software Debug Components -optional
The number of hardware instruction break points
The number of Data Watch point comparators
3. The number of interrupt inputs
The number of interrupt priority levels

Reduces silicon area significantly

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 CORE OF THE PROCESSOR
• Programmers model

REGISTERS in the CORTEX M3 Processor

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 REGISTERS
• The Cortex-M3 processor has registers R0 through R15). R13 (the stack pointer) is
banked, with only one copy of the R13 visible at a time.
R0–R12: General-Purpose Registers
• R0–R12 are 32-bit general-purpose registers for data operations. Some 16-bit Thumb®
instructions can only access a subset of these registers (low registers, R0–R7).

R13: Stack Pointers

• The Cortex-M3 contains two stack pointers (R13). They are banked so that only one is
visible at a time.

Main Stack Pointer (MSP): The default stack pointer, used by the operating system (OS)
kernel and exception handlers

Process Stack Pointer (PSP): Used by user application code

• The lowest 2 bits of the stack pointers are always 0, which means they are always
word aligned.
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 REGISTERS
R14: The Link Register
• When a subroutine is called, the return
address is stored in the link register.
R15: The Program Counter
• The program counter is the current program
address. This register can be written to control
the program flow.

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 SPECIAL REGISTERS
• The Cortex-M3 processor also has a number of
special registers. They are as follows:
• Program Status registers (PSRs)
• Interrupt Mask registers (PRIMASK, FAULTMASK, and
BASEPRI)
• Control register (CONTROL)
• These registers have special functions and can be
accessed only by special instructions. They cannot
be used for normal data processing
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 Special Registers

Special Registers and Their Functions

Program Status Registers)(Slide No:78,79,80,81)
1. Application Program Status register (APSR)
2. Interrupt Program Status register (IPSR)
3. E xecution Program Status register (EPSR)
xPSR Provide arithmetic and logic processing flags (zero flag and carry flag), execution status,
and current executing interrupt number

PRIMASK : Disable all interrupts except the nonmaskable interrupt (NMI) and hard fault
FAULTMASK : Disable all interrupts except the NMI
BASEPRI : Disable all interrupts ofMAMATHA
specificNPpriority level or lower priority level
CONTROL : Define privileged status and stack pointer selection
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 OPERATION MODES
• The CORTEX –M3 processor has two modes and Two Privilege levels.
• Two Modes
– Thread mode: Running a main program(Not running an exception handler )
– Handler mode: running an exception handler
• Two Privilege levels or states :
– Privileged Level/State
– User Level/State
Privileged Level: when the processor is running a main program( thread mode) it can be
in a user state or privileged state. Exceptions can only be in a privileged state.
When the processor exits reset it is in thread mode , with privileged access rights.
Software in the privileged access level can switch program to the user access level using
the Control Register.
When an exception takes place, the processor will always switch back to the privileged
state and return to the previous state when exiting the exception handler.
Note: A user program cannot change back to the privileged state by writing to the
control register. It has to go through an exception handler that programs the control
register to switch the processor back to privileged access level when returning to thread
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Operation Modes

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 ADVANTAGES OF MODE SEPARATION

Separation of user and privilege levels:

Improves system reliability by preventing
system configuration registers from being
accessed by some untrusted programs.
Along with MPU , privilege levels protect
critical memory locations such as program and
data for OS.

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 The Built -In Nested Vectored Interrupt
Controller
• The Cortex-M3 processor includes an interrupt controller
called the Nested Vectored Interrupt Controller
• (NVIC). It is closely coupled to the processor core and
provides a number of features as follows:
• Nested interrupt support
• Vectored interrupt support
• Dynamic priority changes support
• Reduction of interrupt latency
• Interrupt masking

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 The Built -In Nested Vectored Interrupt
Controller
• Nested Interrupt Support
The NVIC provides nested interrupt support. All the
external interrupts and most of the system exceptions
can be programmed to different priority levels.
When an interrupt occurs, the NVIC compares the
priority of this interrupt to the current running
priority level. If the priority of the new interrupt is
higher than the current level, the interrupt handler of
the new interrupt will override the current running
task.
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 The Built -In Nested Vectored Interrupt
Controller
• Vectored Interrupt Support
When an interrupt is accepted, the starting
address of the interrupt service routine (ISR) is
located from a vector table in memory.
• Dynamic Priority Changes Support on the fly
• Priority levels of interrupts can be changed by
software during run time.

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 The Built -In Nested Vectored Interrupt
Controller
• Reduction of Interrupt Latency
• The Cortex-M3 processor also includes a
number of advanced features to lower the
interrupt latency.
• These include automatic saving and restoring
some register contents, reducing delay in
switching from one ISR to another, and
handling of late arrival interrupts.

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 The Built -In Nested Vectored Interrupt
Controller
• Interrupt Masking
• Interrupts and system exceptions can be
masked based on their priority level or masked
completely using the interrupt masking
registers, BASEPRI, PRIMASK, and FAULTMASK.
• They can be used to ensure that time-critical
tasks can be finished on time without being
interrupted.

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 Interrupt and Exception Support
• NVIC: Programmable and its registers are
memory mapped. The Address Location is
fixed and programmer’s model is same for all
Cortex M-Processors.
• System Exceptions : eg NMI, exceptions for
MPU etc.

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 Memory System
• M3/M4 do not have program memory,
SRAM, or cache but come with a generic on
chip bus interface.
• Memory added by vendors:
– Program Memory typically flash
– Data memory typically SRAM
– Peripherals

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 Memory System
• 4 GB addressable Memory Space
• Predefined memory map consistent across all
Cortex M processors. (Porting easy)
– Interrupt controller and debug components can be
accessed easily.
– Highly optimized for speed
– Ease of integration in SOC designs
• Optional Bit Band feature: Two bit addressable areas
– SRAM
- Peripheral Memory

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CORTEX M3, Predefined Memory MAP

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 BUS INTERFACE
• The bus interfaces in CORTEX M3 allows
instruction fetches and data accesses at the
same time. The main bus interfaces are:
• Code memory buses: I-Code and D-code Buses
• System bus: SRAM, peripherals, external RAM,
external devices and parts of the system level
memory.
• Private Peripheral Bus(PPB): Private peripherals
mainly debugging components
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 Bus Interfaces
• I-Code: Primarily for program memory;
Instruction fetch and Vector fetch for address 00h
to 1FFFFFFFh. Based on AMBA 3.0 AHB Lite Bus
Protocol
• D-Code: Primarily for program memory; Data and
Debugger accesses for address 00h to 1FFFFFFFh.
Based on AMBA 3.0 AHB Lite Bus Protocol
• System: Primarily for RAM and Peripherals; Any
Access from address 20000000h to FFFFFFFFh
apart from PPB regions. Based on AMBA 3.0 AHB
Lite Bus Protocol
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 Bus Interfaces
• PPB – External Private Peripheral Bus(PPB). For
private debug components on system level from
address E0040000h to E00FFFFFh. A 3.0 APB
protocol
• DAP – Debug Access Port(DAP) interface: For
debugger accesses generated from the debug
interface module to any memory locations
including system memory and debug components.
Based on the ARM Coresight debug architecture

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 Memory Protection Unit
• Applications can divide the memory space into
a number of regions and define access
permission for each of them. When an access
rule is violated a fault exception is generated.
• An OS can set up the MPU to protect data used
by the OS kernel and other privileged tasks
preventing untrusted user programs from
corrupting them
• MPU by default is disabled
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 LOW POWER FEATURES
• Low power designs because of the low gate
count.
• It has power saving mode support(SLEEPING
and SLEEPDEEP) Multiple Sleep Modes
• Integrated Architectural Clock Gating
Support( Clock deactivated when section not
in use)
• Wake Up Interrupt Controller(WIC)

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 DEBUG SUPPORT
Debug events can be break points, watch points, fault
conditions or external debugging request input signals. When
a debug event takes place Cortex M3 processor can either
enter halt mode or execute debug monitor exception handler
• Debug features
– Program Execution Controls (Halting and Stepping)
– Instruction Breakpoints
– Data Watch Points and Trace(DWT)
– Register and Memory Accesses
– Traces(indicates the flow of execution of a program)
A debug interface module is decoupled and bus interface Debug
Access Port (DAP) is interfaced at the core level. Control of this bus
interface is through Serial Wire JTAG Debug Port (SWJ-DP)
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 DEBUG SUPPORT
Through DAP external debuggers can access
• Control registers to debug hardware and
System Memory on the fly.
Embedded Trace Macrocell(ETM): for instruction
trace. Trace information is output via Trace port
Interface Unit(TPIU)

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Flash Patch and breakpoint Debug Feature

• Provides a simple breakpoint function or

• Remap an instruction access from Flash to
different location in SRAM
• All interfaces through DAP and all trace
informations output through TPIU.

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 Debug Support
• 8 hardware comparators for break points
• 4 hardware data watch point comparators in
the Data Watch Point and Trace(DWT)
• Embedded Trace Macrocell(ETM)
• Debugging can be handled by a JTAG
connection or a two wire interface called a
Serial Wire Debug.

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 Examples of Powerful instructions
1. UFBX,BDI,BFC: Bit field extract, insert and clear
instructions
2. UDIV,SDIV : Unsigned and Signed Divide
Instructions
3. SEV, WFE, WFI : Send-Event, Wait-For-Event ,
Wait-For-Interrupts – These are used for task
synchronization on multiprocessor systems or
enter sleep mode.
4. MSR,MRS: For access to special registers
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 Interrupts and Exceptions
A higher Priority handler can override or
preempt a lower priority interrupt handler.
The interrupt features in Corte-M3 is
implemented in NVIC.
M3 supports a number of fault handling
exceptions.
Supports NMI and 240external interrupts.

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Cortex M3 Exception Types

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THANK YOU

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 CHAPTER 3
CORTEX M3 BASICS

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 Registers
General Purpose Registers R0 through R7
• The R0 through R7 general purpose registers are also called
low registers. They can be accessed by all 16-bit Thumb
instructions and all 32-bit Thumb-2 instructions. They are all
32 bits; t
• General Purpose Registers R8 through R12
• The R8 through R12 registers are also called high registers.
They are accessible by all Thumb-2
• instructions but not by all 16-bit Thumb instructions. These
registers are all 32 bits; the reset value is
• unpredictablehe reset value is unpredictable.
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Regisers in CORTEX M3

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STACK POINTER SP-R13

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STACK OPERATIONS

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 STACK OPERATION
• In general, stack operations are memory write or read
operations, with the address specified by an SP.
• Data in registers is saved into stack memory by a PUSH
operation and can be restored to registers later by a POP
operation. The SP is adjusted automatically in PUSH and POP so
that multiple data PUSH will not cause old stacked data to be
erased.
• The function of the stack is to store register contents in memory
so that they can be restored later, after a processing task is
completed. For normal uses, for each store (PUSH), there must
be a corresponding read (POP), and the address of the POP
operation should match that of the PUSH operation
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STACK OPERATION

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MULTIPLE STACK OPERATION

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 LINK REGISTER R14
• R14 is the link register (LR). Inside an assembly program, you can write it as either
R14 or LR.
• LR is used to store the return program counter (PC) when a subroutine or function
is called—for example,
when you’re using the branch and link (BL) instruction:
main ; Main program
...
BL function1 ; Call function1 using Branch with Link instruction.
;PC = function1 and
; LR = the next instruction in main
...
function1
... ; Program code for function 1
BX LR ; Return

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 Program Counter R15
• Program Counter R15
• R15 is the PC. You can access it in assembler
code by either R15 or PC. Because of the
pipelined nature of the Cortex-M3 processor,
when you read this register, you will find that
the value is different than the location of the
executing instruction, normally by 4. For
example:
• 0x1000 : MOV R0, PC ; R0 = 0x1004
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 SPECIAL REGISTERS
• Program Status registers (PSRs)
• Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)
• Control register (CONTROL)

Special registers can only be accessed via MSR and MRS instructions; they do not have memory addresses:
– MRS <reg>, <special_reg>; Read special register
– MSR <special_reg>, <reg>; write to special register

• Program Status Registers

The PSRs are subdivided into three status registers:
1. Application Program Status register (APSR)
2. Interrupt Program Status register (IPSR)
3. E xecution Program Status register (EPSR)

The three PSRs can be accessed together or separately using the special register access instructions
• MSR and MRS. When they are accessed as a collective item, the name xPSR is used.
• You can read the PSRs using the MRS instruction. You can also change the APSR using the MSR
instruction, but EPSR and IPSR are read-only. For example:

• MRS r0, APSR ; Read Flag state into R0

• MRS r0, IPSR ; Read Exception/Interrupt state
• MRS r0, EPSR ; Read Execution state MAMATHA NP
• MSR APSR, r0 ; Write Flag state 18EC62
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Program Status Register

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 CONTROL REGISTER
• The control register is used to define the privilege level and the SP
selection. This register has 2 bits,
• CONTROL[1]
In the Cortex-M3, the CONTROL[1] bit is always 0 in handler mode.
However, in the thread or base level, it can be either 0 or 1.
• This bit is writable only when the core is in thread mode and
privileged. In the user state or handler mode, writing to this bit is not
allowed. Aside from writing to this register, another way to change this
bit is to change bit 2 of the LR when in exception return. CONTROL[0]
• The CONTROL[0] bit is writable only in a privileged state. Once it
enters the user state, the only way to switch back to privileged is to
trigger an interrupt and change this in the exception handler.

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CONROL REGISTER

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EXCEPTIONS AND INTERRUPTS

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VECTOR TABLE DEFINITION AFTER RESET

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PREDEFINED MEMORY MAP : 32GB
• The Cortex-M3 processor has a total of 4 GB of
address space. Program code can be located in the
code region, the Static Random Access Memory
(SRAM) region, or the external RAM region.
• However, it is best to put the program code in the
code region because with this arrangement, the
instruction fetches and data accesses are carried
out simultaneously on two separate bus interfaces.

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• The SRAM memory range is for connecting internal
SRAM. Access to this region is carried out via the system
interface bus.
• In this region, a 32-MB range is defined as a bit-band
alias. Within the
• 32-bit‑band alias memory range, each word address
represents a single bit in the 1-MB bit-band region. A
data write access to this bit-band alias memory range
will be converted to an atomic READ-
• MODIFY- WRITE operation to the bit-band region so as to
allow a program to set or clear individual data bits in the
memory. The bit-band operation applies only to data
accesses not instruction
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• Another 0.5-GB block of address range is allocated
to on-chip peripherals. Similar to the SRAM
• region, this region supports bit-band alias and is
accessed via the system bus interface. However,
• instruction execution in this region is not allowed.
The bit-band support in the peripheral region makes
• it easy to access or change control and status bits of
peripherals, making it easier to program peripheral
• control.
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• Two slots of 1-GB memory space are allocated
for external RAM and external devices. The
difference
• between the two is that program execution in
the external device region is not allowed, and
there
• are some differences with the caching
behaviors.

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• The last 0.5-GB memory is for the system-level components, internal peripheral
buses, external
• peripheral bus, and vendor-specific system peripherals. There are two segments
of the private peripheral
• bus (PPB):
• • Advanced High-Performance Bus (AHB) PPB, for Cortex-M3 internal AHB
peripherals only; this
• includes NVIC, FPB, DWT, and ITM
• • Advance Peripheral Bus (APB) PPB, for Cortex-M3 internal APB devices as well
as external
• peripherals (external to the Cortex-M3 processor); the Cortex-M3 allows chip
vendors to add
• additional on-chip APB peripherals on this private peripheral bus via an APB
interface

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• The remaining unused vendor-specific
memory range can be accessed via the system
bus interface.
• However, instruction execution in this region is
not allowed.
• The Cortex-M3 processor also comes with an
optional MPU. Chip manufacturers can decide
• whether to include the MPU in their products.

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 PREDEFINED MEMORY MAP

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 Bus Architecture
• The bus interfaces of M3 and M4 are 32 bit and based
on Advanced Microcontroller Bus Architecture(AMBA)
standard
• AMBA: contains several bus protocol specifications.
AMBA has low hardware cost, good efficiency and
openness.
• AHB: The Main bus interface protocol is Advanced
High-performance Bus(AHB) used in program memory
and system bus interfaces.
• AHB is a pipelined bus protocol, allowing high
operation frequency and low hardware costs
• Advanced Peripheral Bus (APB) interface used in the
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 Bit Banding
• Fast single-bit manipulation: 1MB 32MB
aliased regions in SRAM & Peripheral space

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 SysTick
• System timer, SysTick
• The processor has a 24-bit system timer, SysTick,
that counts down from the reload value to zero,
reloads, that is wraps to, the value in the
SYST_RVR register on the next clock edge, then
counts down on subsequent clocks.
• Note
• When the processor is halted for debugging the
counter does not decrement.
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THANK YOU

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