Effect of Surface Texture On Pinhole Formation in Sio - Based Passivated Contacts For High-Performance Silicon Solar Cells

Effect of Surface Texture on Pinhole Formation in
SiOx-Based Passivated Contacts for High-
Performance Silicon Solar Cells
Harvey Guthrey,a* Caroline Lima Salles de Souza,a,b Abhijit S. Kale,a,b William Nemeth,a
Matthew Page,a Sumit Agarwal,b David Young,a Mowafak Al-Jassim,a Paul Stradinsa
aNational Renewable Energy Laboratory, Golden, Colorado, 80401, United States
bColorado School of Mines, Golden, Colorado, 80401, United States
KEYWORDS
silicon solar cell, passivating contact, pinholes, EBIC, surface texture
ABSTRACT
High-efficiency silicon solar cells rely on some form of passivating contact structure to reduce
recombination losses at the crystalline silicon surface and losses at the metal/Si contact interface.
One such structure is polycrystalline silicon (poly-Si) on oxide, where heavily doped poly-Si is
deposited on a SiOx layer grown directly on the crystalline silicon (c-Si) wafer. Depending on the
thickness of the SiOx layer, the charge carriers can cross this layer by tunneling (< 2 nm SiO x
Pursuant to the DOE Public Access Plan, this document represents the authors' peer-reviewed, accepted manuscript.
The published version of the article is available from the relevant publisher. 1
thickness) or by direct conduction through disruptions in the SiOx, often referred to as pinholes, in
thicker SiOx layers (> 2 nm). In this work, we study structures with tunneling- or pinhole-like SiOx
contacts grown on pyramidally textured c-Si wafers and expose variations in the SiOx layer
properties related to surface morphology using electron-beam-induced current (EBIC) imaging.
Using EBIC, we identify and mark regions with potential pinholes in the SiOx layer. We further
perform high-resolution transmission electron microscopy on the same areas, thus allowing us to
directly correlate locally enhanced carrier collection with variations in the structure of the SiO x
layer. Our results show that the pinholes in the SiOx layer preferentially form in different locations
based on the annealing conditions used to form the device. With greater understanding of these
processes and by controlling the surface texture geometry there is potential to control the size and
spatial distribution of oxide disruptions in silicon solar cells with poly-Si on oxide-type contacts;
usually, this is a random phenomenon on polished or planar surfaces. Such control will enable us
to consistently produce high-efficiency devices with low recombination currents and low junction
resistances using this contact structure.
INTRODUCTION
Crystalline silicon solar cells currently dominate the global photovoltaic (PV) market, with
industrially produced silicon PV devices achieving efficiencies greater than 20%. A major driver
for the efficiency improvements over the last decade has been passivation schemes implemented
to reduce recombination losses at the front and back interfaces.1 The effort to reduce interface
recombination has driven the increase in PV conversion through developing various device
architectures. Passivated emitter rear contact (PERC) and passivated emitter rear totally diffused
(PERT) structures have successfully reduced recombination losses within the active device
regions; but recombination at metal contacts to n+ and p+ silicon layers remains a concern.2 Silicon
heterojunction (SHJ) and polycrystalline silicon on oxide (POLO) interdigitated back-contact
(IBC) architectures have been used to produce silicon solar cells with conversion efficiencies
greater than 26%.3, 4 One feature common to all of these technologies is some form of passivating
contact structure. Heterojunction cells rely on amorphous silicon (a-Si) to passivate the c-Si
surfaces whereas in the highly efficient mainstream p-PERC cells, SiNx and Al2O3 are used to
passivate the back surface of the p-type wafer with selective back-surface-field contacts. Tunneling
oxide passivated contact (TOPCon), PERT, and POLO devices use thin SiO x layers to passivate c-
Si surfaces, yielding efficiencies up to 25.7%.5 All recent devices with champion cell efficiencies
have used some variant of passivating contacts.
In both TOPCon and POLO devices recombination at the metal contacts is reduced because the
metal is in contact with the heavily doped poly-Si layer instead of the c-Si surface.6 The use of
poly-Si contacts originated with the work of Yablonovitch in 1985, and several years later Gan and
Swanson also reported very low recombination current (J0) values (10–50 fA/cm2) for poly-Si
emitters with no additional passivation of the poly-Si/metal interface.7, 8 The latter result has driven
the recent developments of TOPCon and POLO-type devices. More recently, J0 values as low as 1
and 5 fA/cm2 have been reported for n+ and p+ poly-Si/SiOx/c-Si, respectively.9 These low
recombination current densities result from the high-quality interface produced by chemical
passivation of the c-Si surface by the thin SiOx layer, and due to the field-effect passivation induced
by the heavily doped poly-Si layers.10 The interfacial oxide is critical to this passivation because
heavily doped poly-Si directly on c-Si results in J0 values several orders of magnitude higher.9, 11
The thickness of the SiOx layer determines what transport processes are dominant. Thin SiOx
layers (< 2 nm) in TOPCon structures allow tunneling of charge carriers.12 These passivating
contacts exhibit uniform charge collection over the contact area, unless extended defects are
present within the underlying c-Si material.13 This makes studying the junction properties
relatively straightforward. In contrast, thicker (> 2 nm) SiOx layers in POLO contacts rely on
charge-carrier transport via disruptions in the SiOx (often referred to as pinholes) because the oxide
is too thick to allow for efficient tunneling.8, 14 This transport mechanism accurately explains the
low emitter saturation current densities and the low junction resistance values observed
experimentally.15 We note that when pinholes are present in thin oxide layers both tunneling
transport and transport via pinholes can occur. The ratio of these processes depends on both the
precise thickness of the SiOx layer and temperature.14 Regions where the poly-Si and c-Si are in
direct contact experience large recombination currents, but only a tiny pinhole-area fraction is
needed (~10-4) for carrier transport if the pinhole size is in the 10‒100-nm range.13 Of course, the
impact on device parameters differs based on the density and size of pinholes. Additionally, the
critical density of pinholes above which significant increases in J 0 are observed differs for n+ and
p+ poly-Si/SiOx/c-Si structures. For p+ poly-Si junctions, J0 values exhibit large increases for
pinhole densities > 108 cm-2, whereas this number decreases to 107 cm-2 for n+ poly-Si junctions.9
The breakup of interfacial oxides by thermal annealing has been observed by several groups
using high-resolution transmission electron microscopy (TEM) in poly-Si emitter bipolar
transistors as well as PV devices.9, 16, 17 TEM imaging results from Peibst et al. show that the
microstructure of the poly-Si layer may influence changes in the SiO x thickness upon high-
temperature annealing.9 Oxide thinning was observed near grain interiors whereas thickening, or
balling up, was observed near grain boundaries. However, the lack of statistics of these
observations makes the connection between microstructure and pinhole formation inconclusive.
Determining the location, densities, and structural properties of pinholes of the interfacial oxide
layers in POLO-type device structures is difficult for several reasons. 1) The interfacial oxide is
located between the c-Si and poly-Si layers and cannot be directly accessed without removing the
poly-Si layers. This makes it difficult to identify pinhole location without destructive techniques.
2) The pinholes in a well-performing POLO contact are microns apart; thus, they are difficult to
locate non-destructively for further microscopy.9, 13 3) The size of pinholes is on the order of a few
to 10s of nanometers, limiting what characterization techniques can be used to study those with
very high spatial resolution.9 Scanning probe techniques such as conductive atomic force
microscopy (cAFM) and scanning Kelvin probe force microscopy (SKPFM) have been used to
identify pinhole locations, although this requires removal of the poly-Si.18, 19 3) The density of
pinholes in devices with good performance (107 cm-2 or less) makes identification with TEM a
low-probability endeavor.9 Romer et al. have used an “extensive oxide break-up step” to increase
the density, making it possible to capture regions where the SiOx was compromised within a
randomly selected region analyzed by TEM imaging. 11 However, such an “extensive oxide break-
up” diminishes device performance.
One successful method of identifying pinhole locations is to exploit the etching selectivity of
tetramethylammonium hydroxide (TMAH).20-22 Because the etch rate of Si is much higher than
SiOx, TMAH preferentially etches off the poly-Si and then etches into the c-Si while leaving the
SiOx layer predominantly undisturbed. This creates an etch pit at locations where there is no SiO x
layer, thus revealing regions where local breakup of the SiO x layer has occurred. Although
effective at exposing the location pinholes, this destructive process makes it impossible to extract
information about the structure of pinholes or to study the electronic properties of these features.
It is also unclear whether very small pinholes, or “pinholes” represented by a locally thinner SiO x,
can be visualized this way, because the SiO2 layer might be etched away before an etch pit is
formed.
In previous works, we have shown that electron-beam-induced current (EBIC) imaging can be
used to identify pinhole locations in a complete POLO device structure based on local increase in
EBIC collection.13, 19 EBIC imaging uses excess charge carriers excited by the electron beam in a
scanning electron microscope (SEM) to probe the spatial distribution of charge-carrier collection.
The collection of charge carriers, excited by the electron beam, through the transport pinholes has
been described in our previous publication.13 We confirmed that the increases in EBIC signal were
due to local decreases in the SiOx thickness by performing EBIC within the focused ion beam
(FIB) to directly target regions with increased EBIC signal for TEM specimen preparation. This
procedure reduced the uncertainty in the position of pinholes and enabled the direct correlation of
increased EBIC collection with local thinning of the SiO x layer. In thicker (> 2 nm) SiOx layers,
the EBIC current is preferentially collected through pinholes, whereas in tunneling oxide layers (<
2 nm), the EBIC collection is more uniform over the device area. An example of EBIC images
collected from POLO-type devices on polished c-Si surfaces is shown in Figure 1.
Figure 1. (a,b) SEM and (c,d) EBIC images from devices on polished Si using a 1.5-nm tunneling
oxide (a,c) and a thicker 2.2-nm oxide (b,d) for surface passivation. Reprinted with permission
from reference 24. Copyright 2019 IEEE.
Based on these previous EBIC imaging results, pinholes in SiO x grown on polished or saw-
damage-etched (SDE) c-Si appear to be randomly distributed. Kale et al. showed that in
pyramidally textured devices, enhanced EBIC collection is correlated with valleys between
adjacent pyramids, although the collection differs from valley to valley.23 The EBIC results in that
work suggested that variations in the SiOx thickness at these valleys were responsible for the
enhanced EBIC signal, but this was not proven microscopically. In this work, we present EBIC
analysis of devices with POLO contact structures using a 1.5-nm tunneling SiOx layer and a thicker
2.2-nm SiOx layer on pyramidally textured c-Si in both plan-view and cross-section orientations.
The results of cross-section EBIC imaging are used to guide preparation of TEM specimens such
that here we provide a definitive correlation between the electronic properties and the nanoscale
structure. The devices with 2.2-nm SiOx layers received an additional high-temperature anneal to
induce local breakup of the interfacial oxide. We find the spatial distribution of regions
experiencing breakup of the SiOx layer is quite sensitive to the annealing process schedule and
annealing temperatures.
EXPERIMENT
The structures analyzed consist of double-side randomly textured phosphorous-doped Si (100)
wafers with resistivities of 1–5 Ω-cm. The wafers were cleaned using piranha, RCA-1, and RCA-
2 processes prior to dry thermal oxidation using a 6:1 N2-to-O2 gas flow ratio to produce either a
1.5 or 2.2 (±0.05)-nm-thick SiOx layer (see 24 for more details). Using plasma-enhanced chemical
vapor deposition (PECVD), doped or intrinsic a-Si:H was deposited on both sides of the oxidized
c-Si wafers in separate steps with thicknesses varying over the sample from 10-15 nm (measured
with TEM imaging). The dopant concentrations in the n-type and p-type poly-Si layers range
from 5 x 1020 to 2 x 1021 cm-3, for both phosphorus and boron. The corresponding free carrier
concentrations measured by Hall effect range from mid- 1019 to approximately 1 x 1020 cm-3.
Test cells with the n+ poly-Si/SiOx/n-Si/SiOx/p+ poly-Si structure were formed via annealing this
layer stack in N2. The wafer with the 1.5 SiOx layers was annealed with a ramp from 200°C to
850°C over 180 minutes and held at 850°C for 30 minutes. This will be referred to as Sample A.
One sample with and 2.2-nm-thick SiOx layer was subjected to the same ramp rate as Sample A,
however the final temperature was then increased to 1025°C (together constituting a single
process) to induce breakup of the 2.2 nm SiOx layer. This sample will be referred to as Sample
B. Another sample with a 2.2-nm-thick SiOx layers was subjected to the same crystallization
anneal as Sample A. Then in a separate step the sample was rapidly annealed to a final
temperature of 1100°C. This will be referred to as Sample C. The samples were metallized with
thermally evaporated Al after a hydrogen-induced passivation step, via 15 nm AlOx deposition
followed by forming gas anneal for 1h in 9:1 N2:H2, to create a 4-cm2 back-junction cell. SiNx
was deposited on the front n+ poly-Si layer as an anti-reflection coating. Device parameters for
these three samples are given in Table 1.
Table 1. Device parameters for the two test structures studied.
Sample Voc (mV) Jsc (mA/cm2) Fill Factor (%) Efficiency (%)
A - 1.5-nm SiOx 708 37.7 71.9 19.2
B - 2.2 (±0.05)-nm SiOx 632 34.6 76.6 16.7
C - 2.1 (±0.05)-nm SiOx 627 32.8 51.6 10.6
EBIC measurements were performed using a JEOL JSM-7600F FESEM and Mighty EBIC
quantitative EBIC system. Scanning electron microscopy images and EBIC images were acquired
simultaneously. An electron-beam accelerating voltage of 5 kV and ~1-nA beam current were used
for the EBIC measurements in both plan-view and cross-section orientations. Cross-section
samples were prepared by ion milling using 4-kV Ar+ ions resulting in a smooth surface. Samples
were prepared for TEM analysis by the FIB lift-out technique using a Nova 200 Nanolab Dual-
Beam FIB.25 Regions imaged in cross-section orientation using the quantitative Mighty EBIC
system were carefully mapped by comparing with surface texture. This allowed the same region’s
images with cross-section EBIC to be identified in the FIB based on SEM images of the surface
texture. One side of the intended TEM samples had already been liberated from the bulk (via the
cross-section preparation process), and ion milling in the FIB occurred primarily from the opposite
side of the exposed face from where the EBIC images had been collected. The face of the cross-
section corresponding to the EBIC images only received 5-keV ion milling to remove material
redeposited from milling the opposite side of the sample. Less than 50 nm of material was removed
from this surface. Thus, the TEM imaging results correspond directly to the regions represented in
the cross-section EBIC images. Phase-contrast TEM imaging were acquired using FEI Tecnai F20
TEM operated at 200 kV. TMAH etching was performed on Samples B and C for additional
confirmation of pinhole locations. The conditions were 5% TMAH at 60ºC to remove the poly
layer and etch the c-Si under the pinhole locations.
Simulations of the energy deposited by the electron beam during the EBIC measurements were
performed using the Monte Carlo simulation software CASINO 26. These simulations were
performed using a silicon sample with a uniform pyramid geometry as shown in Figure 4. No SiOx
layer was included in the simulation structure as a few nanometers of SiOx has a negligible effect
on the amount and distribution of energy deposited by the electron beam.
RESULTS
The plan-view-oriented SEM and EBIC images in Figure 2 reveal significant differences in
charge collection for Samples A and B which have different SiOx thicknesses. The low collection
(darker regions) at the apex of pyramids and the increased collection (brighter regions) at the
valleys is similar for both 1.5- and 2.2-nm-thick SiOx devices. This contrast between valleys and
tips is somewhat related to the measurement geometry and will be discussed later. Although
similar, in Sample B, the reduced collection at the tips of pyramids and the increased collection at
the valleys is much more diffuse than for Sample A. Additionally, there is great variation from
valley to valley in Sample B, whereas the valleys in Sample A all exhibit EBIC signals of very
similar line definition and brightness.
Figure 2. (a,b) SEM and (c,d) EBIC images in the plan-view orientation from silicon devices with
passivating contacts on pyramidal textured surface (a,c) Sample A and (b,d) Sample B. The length
scale shown in the SEM images is the same for the corresponding EBIC images. The current scale
for the EBIC images is shown directly below the EBIC images. Images for Sample A are
reproduced in part with permission from reference 23. Copyright 2019 American Chemical
Society.
To reveal the microscopic origins of the carrier transport and collection in Samples A and B, we
prepared cross-section specimens by cleaving the sample and polishing the cross-sectional face
using 4-kV Ar+ ions. In samples polished by ion milling, the majority EBIC signal results from
charge collection in the depletion region due to increased recombination at charged or neutral
surface defects relative to a cleaved surface.27 This is sufficient in the context of this work where
we are interested in the microscale transport properties of the poly-Si/c-Si junction and not its
passivation-dependent properties such as diffusion length. We chose to image the p-n junction
between the p+ poly-Si/n-type c-Si due to its larger EBIC signal as compared to the n+ poly-Si/n-
type c-Si high-low junction. There is a green line in the lower portion of the EBIC images shown
in Figures 3c and 3d. This line corresponds to the EBIC signal integrated over about 250 nm
parallel to the Si/SiNx interface visible in the SEM images (Figures 3a and 3b). The EBIC signal
in the 1.5-nm SiOx sample (Figure 3c) exhibits some decrease in collection near the pyramid tips,
whereas the signal in other regions (including the valleys) is quite uniform. This confirms that the
well-defined, high-brightness EBIC signal from the pyramid valleys in the plan-view map of
Figure 2c is simply a result of enhanced energy deposition there. This is further supported by
simulation results later in this work. In contrast, Sample B sample exhibits enhanced EBIC
brightness in pyramid valleys, even in the cross-sectional geometry (see Figure 3d). Similar to the
plan-view results in Figure 2d, not all of the valleys exhibit the same increase in collection, e.g.,
there is a not-as-bright valley in between the two brightest valleys.
Figure 3. (a,b) SEM and (c,d) EBIC images in the cross-section orientation from silicon devices
with passivating contacts on a pyramidal texture for (a,c) Sample A and (b,d) Sample B. The length
scale shown in the SEM images is the same for the EBIC images. The current scale for the EBIC
images is shown directly below the EBIC images. The green lines in the EBIC images represent
the EBIC signal averaged over an ~ 300-nm width parallel to the surface to show the variation in
current collection. The scale for the green lines is the same, with the same units, as the scale for
the overall EBIC images.
It is interesting to note the similarity of the EBIC image in Figure 2c for the n+ poly-Si/1.5-nm
SiOx/c-Si junction with that of previously reported results for a diffused emitter. 28 The diffused
emitter does not contain a SiOx passivation layer, and the c-Si is heavily doped in the few microns
near the surface. EBIC images for both of these junction types only show variations in carrier
collection dominated by artifacts of surface texture as shown by the CASINO simulations. The
likely reason for the similarity is that the 1.5-nm thin SiOx layer does not impede carrier transport
across the device area. Krugener et al. have shown that dopants easily diffuse through SiOx layers
with thicknesses as great as 2.6 nm,29 further homogenizing the carrier transport in various
locations. The dopant profiles reported by Krugener et al. are similar to those of a diffused emitter,
and such a profile may be present in Sample A that would result in similar charge collection at this
junction.
To understand the effect that the surface texture has on EBIC signal, e.g. image brightness, we
have simulated the energy deposited by the e-beam during these EBIC measurements on pyramid-
textured surfaces in both plan-view and cross-section geometries (see Figure 4) using the CASINO
Monte Carlo simulation software.30 The geometries used for the plan-view and cross-section
simulations on a textured Si surface are shown in Figures 4a and 4b, respectively. The x, y, and z
directions are consistent for both orientations. The yellow line in Figure 4a shows the e-beam
scanned in the x-direction through the middle of the textured pyramidal geometry, such that the
beam crosses each pyramid tip and valley. The beam direction for simulation of plan-view
scanning is along the z-axis. The absorbed energy map in Figure 4c is proportional to the number
of excess carriers generated in this structure as the e-beam scans along the yellow line. The map
in Figure 4c is shown as a 2D slice in the xz-plane that intersects the position of the yellow line in
Figure 4a. The deposited energy map in Figure 4c shows that less energy is deposited by the e-
beam at the tips and more at the valleys. This is shown in more detail in the inset at the right of the
image. The sharpness of the increase and decrease indicates that this nonuniformity is governed
by the sample geometry. The similarity of our simulations (see Figure 4c) with the experimentally
measured EBIC image in Figure 2c indicates that in Sample A the variations in the EBIC signal
are due to surface texture and not differences in charge-carrier collection related to the SiOx layer.
In contrast, the diffused dark and bright regions across Sample B and the highly variable brightness
in the pyramid valleys indicate that additional factors, such as properties of the SiOx layer, govern
charge-carrier collection in these regions in Sample B. The absorbed energy map in Figure 4d for
the cross-section orientation, where the beam is oriented along the y-axis, normal to the cross-
section face, is quite uniform. This means that any variation in EBIC signal in the cross-section
images is due to actual variations in the charge collection probability and not due to surface texture.
Figure 4. Schematic of the geometry used for simulating the spatial distribution of energy
deposited by the electron beam during the (a) plan-view and (b) cross-section EBIC measurements.
Energy deposited by the e-beam in (c) plan-view and (d) cross-section EBIC measurements. Note
that the map in (c) represents a slice through the structure along the yellow line in (a).
The EBIC images in Figures 2d and 3d as well as simulations of the energy deposited by the
electron beam in Figure 4 confirm that there is enhanced carrier collection at the pyramid valleys.
This suggests that carrier transport across the SiOx layer is more prevalent near the valleys. To
relate carrier transport across the SiOx layer to its structural properties, we performed TEM
analysis of the same region visible in the cross-section EBIC image of Sample B shown in Figure
3d. The sample preparation and analysis are discussed in the experiment section. Figure 5b shows
a higher magnification of the rightmost bright valley in Figure 3d. The red numbers in Figure 5b
indicate the corresponding locations of the TEM images in Figures 5a,c‒e. The phase-contrast
images in Figures 5a,c‒e show the region containing the p+ poly-Si/SiOx/c-Si layers. Within the
TEM images in Figures 5a and 5c, showing the faces of the adjacent pyramids, the SiO x layer is
clearly visible. This is expected due to processing steps followed for making the poly-Si/SiOx/c-
Si contact structure. However, in the bottom of the valley (Figures 5d and 5e), the SiOx layer is no
longer visible. The yellow dashed lines indicate the expected position of the SiOx layer based on
tracking the layer position in TEM images from the adjacent region. Furthermore, the identical
lattice fringes on either side of the yellow dashed lines indicated that the c-Si material acted as a
template for solid-phase epitaxial growth of the p+ poly-Si layer, likely during the high temperature
(1025°C) annealing process.
Figure 5. Phase-contrast TEM images (a,c‒e) of the c-Si/SiOx/poly-Si interfaces from different
positions on the right “bright” valley in Sample B shown in Figure 3d. This region is shown in
higher magnification in (b), and the red numbers in (b) show the approximate corresponding
positions for the various phase contrast TEM images. The yellow lines in d and e indicate the
expected location of the SiOx layer.
Based on the bright valleys in the plan-view EBIC image of Sample B (Figure 2d) it is likely
that instead of isolated pinholes like those shown in Figure 1d, the SiO x layer could be missing
along the length of certain valleys. To test this hypothesis we etched through the poly-Si layer
using TMAH. TMAH is a highly selective etch for silicon relative to SiO x and this etching process
will produce etch pits where there are disruptions in the SiOx layer. Figure 6c shows an SEM image
of Sample B after etching with TMAH. There is a widening of valleys between pyramids (white
ovals) as a result of the etching process, confirming the lack of SiO x in these locations. We also
note that no etch pits are observed on the pyramid facets or tips. The etching was performed in the
n+ side of Sample B as it is easier to etch through the n-type poly-Si than the p-type poly-Si layer.
We also confirmed that this side of the device exhibited the same enhanced EBIC signal in the
valleys as the p+ side shown in Figure 2d. The plan-view SEM and EBIC images from the n+ side
of Sample B are shown in Figures 6a an 6b, respectively. The images in Figure 6 show that for
Sample B, the properties of the SiOx layer and the annealing process used for crystallization of the
a-Si, breakup of the SiOx layer occurs preferentially, and only, in the valleys between pyramids in
the surface texture.
Figure 6. a) SEM image, b) EBIC image, and c) SEM image after TMAH etching for the n + side
of Sample B.
To confirm that the lack of a SiOx layer in the pyramid valley was a result of the high-temperature
(1025 ºC) anneal and not a consequence of nonuniform SiOx growth, we fabricated another sample
with a structure consisting of a 2.2-nm SiOx layer and intrinsic a-Si on a textured c-Si wafer. In
contrast to the 1025 ºC crystallization anneal used for Sample B , this structure was annealed only
to 850ºC using the same schedule described for Sample A in the experimental section to allow
crystallization of the a-Si, without inducing breakup of the oxide layer. This makes it easier to
distinguish the SiOx layer in phase-contrast TEM images. Using this sample, we prepared a TEM
specimen from a random region containing several valleys. Figure 7 shows phase-contrast TEM
images from these valleys. The SiOx is clearly visible in these images, confirming that the missing
SiOx in Figures 5d and 5e was a result of the high-temperature anneal.
Figure 7. Phase-contrast TEM images (a-d) of several valleys between pyramids in a structure
with a thick (~2-nm) SiOx layer and poly-Si layer crystallized with the same annealing schedule
used for Sample A.
The SiOx layer in Sample B exhibits clear preferential breakup in valleys between pyramids in
the surface texture. However, if different annealing processes are used the spatial distribution of
SiOx breakup can change significantly. The crystallization anneal to high temperature (1025ºC)
for Sample B was performed in one step. In another sample (Sample C) with the same structure as
Sample B the crystallization anneal and high temperature anneal required to breakup the SiOx layer
were performed separately. Details of the different annealing schedules are given in the
experimental section. The final temperature for Sample C (1100ºC) was also higher than that for
Sample B (1025ºC). These differences produced a very different distribution of SiO x breakup than
observed in Sample B. The EBIC image in Figure 8b shows isolated bright spots on the facets of
the pyramids. No bright valleys similar to those in Figure 2d are observed in this EBIC image.
This sample was also etched with TMAH and the SEM images after etching (Figure 8c) shows
that in Sample C pinholes in the SiOx are formed preferentially, and only, on pyramid facets. No
widening of the valleys, similar to that in Figure 6c, was observed for Sample C.
Figure 8. a) SEM image, b) EBIC image, and c) SEM image after TMAH etching for the n +
side of Sample C.
DISCUSSION
Using simulations, EBIC, and TEM, we have a definitive correlation of enhanced EBIC
collection with locations where SiOx breakup occurs for pyramidally textured silicon surfaces. The
preferential SiOx breakup in the valleys of Sample B might be related to stress in the SiOx film
when grown on a non-planar surface.31-33 Because SiOx grows perpendicular to the Si surface,
concave or convex surface morphologies can cause either compressive or tensile stress in the SiO x
film, respectively. The preferential SiOx breakup on the facets of Sample C may have a similar
cause. We have previously shown that the facets of surface texture pyramids are not perfectly flat,
but exhibit atomic-scale roughness.23 This roughness can also introduce nonuniformities in the
SiOx layer that could drive the breakup process. Furthermore, mechanical stress in the SiOx layer
can affect the diffusivity of oxygen.34 Both of these factors can affect the SiOx breakup
phenomenon at high temperatures, during which the O and Si atoms need to rearrange so as to
relieve stress and reduce the overall free energy of the system.35
The results of TMAH etching on Sample B show that in contrast to the pinholes that form in
oxide layers on polished or otherwise flat Si surfaces, oxide breakup on textured surfaces can
create much larger regions where the poly-Si and c-Si are in contact. This could explain the much
lower open-circuit voltage (Voc) for Sample B (see Table 1). Despite this, it is important to realize
that the definitive correlation of enhanced EBIC signal with SiO x breakup in the valleys between
pyramids in the surface texture provides an opportunity to control the spatial distribution—and
thus, density—of disruptions in the interfacial oxide layer. This is of course only true if the SiOx
breakup is restricted to certain locations such as the valleys between pyramids. The EBIC and
TMAH etching results for sample C show that the spatial distribution of pinholes is very sensitive
to the properties of the SiOx layer and the annealing schedule and temperatures used to fabricate
devices with thick SiOx. The reason for preferential breakup in different locations is not clear based
on the current work. However, defining the mechanism of pinhole formation in terms of annealing
times and temperatures is critical to guide optimization of device fabrication. The work of Peibst
et al. has clearly shown that there is a range of optimum density (which is also size-dependent) of
pinholes that results in low recombination current while maintaining low junction resistance.9
With a detailed understanding of mechanism of pinhole formation in terms of annealing times and
temperatures it should be possible to empirically optimize the high-temperature anneal to produce
the correct size and density of disruptions in the SiO x layer. Additionally, using wafers with
uniform-texture geometry could potentially provide much more control over the density and size
of oxide disruptions. For example, if SiOx breakup can be confined to valleys between pyramids,
one could use c-Si wafers with v-groove or inverted-pyramid texture schemes to control the
distribution of favorable sites for pinhole formation. In future work, we plan to expose the
relationship between processing conditions, surface texture, and SiO x breakup so that device
fabrication can be optimized by controlling the size and density of pinholes. This will allow
minimization of the junction resistance and the recombination current required to produce high
efficiency photovoltaic devices.
CONCLUSIONS
We have built on our previous results using EBIC to expose nonuniform charge-carrier
collection in silicon photovoltaic devices with POLO-type junctions. Here, we have shown—
through a definitive correlation by cross-section EBIC imaging, phase-contrast TEM imaging, and
TMAH etching—that pinholes, or disruptions in the SiOx passivation layer, occur preferentially in
different locations based on the properties of the interfacial SiOx layer and the annealing times and
temperatures used to fabricate photovoltaic devices. On pyramidally textured c-Si, we observed
exclusive pinhole formation in valleys between pyramids for one sample, while in another sample
pinholes were exclusively formed on pyramid facets. At present, the underlying reason that this
occurred is not clear. However, our findings provide a promising direction for obtaining greater
control over the formation and distribution of oxide disruptions. It should be possible to finely tune
surface-texturing methods to produce a more uniform size and distribution of texture features—
and thus, preferential locations for oxide disruptions—that result in the highest efficiencies of
photovoltaic devices once the appropriate parameter space is defined.
ACKNOWLEDGMENT
This work was authored in part by Alliance for Sustainable Energy, LLC, the manager and
operator of the National Renewable Energy Laboratory for the U.S. Department of Energy (DOE)
under Contract No. DE-AC36-08GO28308. Funding provided by U.S. Department of Energy
Office of Energy Efficiency and Renewable Energy Solar Energy Technologies Office. The views
expressed in the article do not necessarily represent the views of the DOE or the U.S. Government.
The U.S. Government retains and the publisher, by accepting the article for publication,
acknowledges that the U.S. Government retains a nonexclusive, paid-up, irrevocable, worldwide
license to publish or reproduce the published form of this work, or allow others to do so, for U.S.
Government purposes.
AUTHOR INFORMATION
Corresponding Author
*Harvey Guthrey
15013 Denver West Pkwy, Golden, Colorado, United States 80401
harvey.guthrey@nrel.gov
Author Contributions
The manuscript was written through contributions of all authors. All authors have given approval
to the final version of the manuscript
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Effect of Surface Texture On Pinhole Formation in Sio - Based Passivated Contacts For High-Performance Silicon Solar Cells

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Effect of Surface Texture On Pinhole Formation in Sio - Based Passivated Contacts For High-Performance Silicon Solar Cells

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Effect of Surface Texture on Pinhole Formation in

SiOx-Based Passivated Contacts for High-

Performance Silicon Solar Cells

aNational Renewable Energy Laboratory, Golden, Colorado, 80401, United States

bColorado School of Mines, Golden, Colorado, 80401, United States

silicon solar cell, passivating contact, pinholes, EBIC, surface texture

properties related to surface morphology using electron-beam-induced current (EBIC) imaging.

resistances using this contact structure.

have used some variant of passivating contacts.

using high-resolution transmission electron microscopy (TEM) in poly-Si emitter bipolar

up” diminishes device performance.

collected from POLO-type devices on polished c-Si surfaces is shown in Figure 1.

from reference 24. Copyright 2019 IEEE.

The structures analyzed consist of double-side randomly textured phosphorous-doped Si (100)

thermally evaporated Al after a hydrogen-induced passivation step, via 15 nm AlOx deposition

these three samples are given in Table 1.

Table 1. Device parameters for the two test structures studied.

A - 1.5-nm SiOx 708 37.7 71.9 19.2

B - 2.2 (±0.05)-nm SiOx 632 34.6 76.6 16.7

C - 2.1 (±0.05)-nm SiOx 627 32.8 51.6 10.6

layer and etch the c-Si under the pinhole locations.

on the amount and distribution of energy deposited by the electron beam.

similar line definition and brightness.

there is a not-as-bright valley in between the two brightest valleys.

the overall EBIC images.

(1025°C) annealing process.

expected location of the SiOx layer.

the surface texture.

SiOx in Figures 5d and 5e was a result of the high-temperature anneal.

used for Sample A.

temperatures it should be possible to empirically optimize the high-temperature anneal to produce

efficiency photovoltaic devices.

temperatures used to fabricate photovoltaic devices. On pyramidally textured c-Si, we observed

photovoltaic devices once the appropriate parameter space is defined.

under Contract No. DE-AC36-08GO28308. Funding provided by U.S. Department of Energy

15013 Denver West Pkwy, Golden, Colorado, United States 80401

to the final version of the manuscript

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