Smart CutTM Technology Provides Excellent Layer Uniformity

for Fully Depleted CMOS

N. Daval, W. Schwarzenbach, C. Moulin, O. Bonnin, V. Barec, O. Kononchuk, C. Maddalon,
T. Robson, B.-Y. Nguyen, C. Mazure & C. Maleville,
Soitec, Parc Technologique des Fontaines, 38190 Bernin, France.

INTRODUCTION
Planar Fully Depleted SOI is emerging as a CMOS solution for
post 28 nm nodes, extending further the possibility to benefit from
scaling, while traditional bulk planar transistors can no longer meet
the perf/area requirements in a cost effective manner and low power
FinFETs are not yet ready. Due to true undoped channel operation
and great electrostatics, FDSOI transistors currently allow a 28nm
technology to have a gate length of 24nm [1], which comes with low
gate capacitance and therefore AC benefits. Advanced research
studies also show the scaling path for a FDSOI transistor down to
Lg = 15nm, which is suitable for a 10nm CMOS node [2], this
combined with clear demonstration of performance booster solutions
[3], make FDSOI CMOS a very competitive technology for future
process nodes.
Fig 2. Volume SOI thickness distribution for FDSOI wafers
Today, variability is a central issue for scaling transistors, which
often manifests itself as high leakage on the device. The future of FDSOI substrate thickness is measured at the wafer scale with
CMOS will rely on variability sources limitation and control. In that ellipsometry, as shown on Fig. 3. In addition, AFM measures the
context, Planar FDSOI with undoped channel suppresses RDF, a surface height, and assuming a flat BOX/SOI interface, one can
major variability source, and at the same time because it is planar compute silicon thickness at the device scale. However current
keeps the variability low due to channel dimensional variations. This FDSOI wafer roughness has reached such low levels that it is a
paper reports the latest achievements in state of the art thickness and serious issue for AFM to demonstrate adequate repeatability,
roughness control, which is enabling very low variability fully reproducibility (R&r) and tool matching. A new technique is
depleted technologies today. introduced to complement AFM, based on optical microscopy. This
technique uses an optimized wavelength depending on the SOI/BOX
SMART CUT™ TECHNOLOGY stack thickness, in order to have the intensity of the signal just a
AND UNIFORMITY CONTROL function of the top silicon thickness, which is read out as a contrast
variation on the final microscope picture. Optimized wavelength is in
the green spectrum for a 12nm Si / 25nm BOX stack. Due to this
A Planar Fully depleted transistor VT is a function of the silicon
thickness between the gate and the BOX (Buried Oxide). After green wavelength, the resolution of this technique is around 500 nm.
Other benefits include fast acquisition time, direct silicon thickness
optimization of the device process, this silicon thickness variability is
exactly the same as the top SOI layer of the wafer. To keep TSi measurement as opposed to surface-limited AFM, and great potential
for R&r and tool matching.
related VT variability negligible, previous work has concluded that
the layer control should be +/- 5 A [4]. To keep things in perspective,
this means less than 5 silicon interatomic distances over a 300mm
wafer. No thickness measurement method in production has atomic
level resolution. The metrology always involves an average over
some area. Typically, ellipsometry will average over a 50µm² area,
AFM will be in the nm² range.

Fig 3. Thickness wafer map with 6ı = 6.72Å

FDSOI wafers are manufactured with the same process flow

Fig 1. SOI Smart Cut process flow
(Fig.1) as Partially Depleted (PDSOI) wafers which are in mass
production. The improved uniformity has been obtained through an
optimization of the process steps. Fig 2 shows SOI layer thickness
control over the last year of manufacturing well within +/- 5A. Fig 4
shows high uniformity of the layers throughout the entire process
flow, with the example of one wafer in the median of the distribution

978-1-4673-3082-4/13/$31.00 ©2013 IEEE

taken at different steps of fabrication showing the thickness maps.
Oxidation of the initial substrate forms the oxide layer that will
become the BOX and whose uniformity will be critical because it
will influence the implantation depth of the H+ and the resulting
cleaving plane. High uniformity is kept post splitting and through the
finishing steps until the SOI wafer is finished.
Fig 4. Layer thickness maps of the same wafer at different
stages of the process: after oxidation (top), after splitting
(middle) and on the final SOI wafer (bottom).
ROUGHNESS CONTROL
During the finishing step of the process flow shown in Fig. 1, the
silicon thickness is thinned down to the desired final thickness and
the roughness is dramatically improved. The smoothing process to
reach the Fully Depleted requirements has been revisited and several
options have been explored, using Thermal Anneal, CMP or other
more disruptive options. Fig 5 shows the best 2Å local range
obtained on FDSOI, with the roughness performance measured by
optical microscopy. Extremely low device scale thickness variation
has been demonstrated.
Cross section
PV = 2 Å
Fig 5 : Optical Microscopy local SOI thickness.
Best uniformity results: 2Å Peak to Valley.
FDSOI DEFECTIVITY
Wafers are inspected by laser scanning to count and categorize
defects on top and beneath the surface. Scattered light intensity is
translated into defect size; the whole surface is inspected and defects
are detected when scattered light reaches a certain threshold.
According to the ITRS roadmap, FDSOI material is inspected with a
SP3 tool @ 50nm sensitivity. Fig. 6. Shows SOI defect maps of 2
different wafers, and the corresponding bulk wafer used to
manufacture them. SOI and Bulk defectivity levels are similar.
Current SOI median defect count @50nm is 13 defects.
Fig 6: Bulk VS SOI defect maps @ 50nm.
CONCLUSION
Now that silicon product results are becoming available, and that
the FD-SOI substrates hit the required uniformity to enable such
products. It can now be said that Planar FDSOI is a credible
manufacturing technology at 28nm. Furthermore, the technology is
in place and has been proven to enable further scaling to at least the
10nm node.
The main objective was to successfully manufacture a FDSOI
substrate with a SOI layer control at +/- 5 A for all points all wafers.
This has been achieved by integrating a near perfect wafer scale
uniformity together with an optimized extremely low roughness
process. Further innovations have been identified to improve this
process even further in the future.
REFERENCES
[1] N. Planes et al, VLSI Symp. 2012
[2] O. Faynot et al, IEDM 2010
[3] A. Khakifirooz et al, VLSI Symp. 2012
[4] A. Khakifirooz et al, VLSI-TSA 2010