Substrate Engineering Using Smart CutTM and Smart StackingTM for
Next-Generation Advanced LSIs
Makoto Yoshimi1), Xavier Cauchy2), Eric Desbonnets2), Ionut Radu2), and Christophe Maleville2)
1) Soitec Japan, Otemachi First Square, 1-5-1, Otemachi, Chiyoda-ku, Tokyo 100-0004, Japan
Email: makoto.yoshimi@soitec.com
2) Soitec, Parc Technologique des Fontaines, 38926 Bernin, Crolle Cedex, France
Abstract
Substrate engineering using Smart CutTM and
Smart StackingTM for advanced LSIs is overviewed. For
digital CMOS applications, planar fully-depleted (FD)
SOI structure provides a realistic solution to bridge the
technology gap between bulk CMOS and
three-dimensional FD structures. Production of planar
FD-SOI will be started soon in 28nm technology. RF
applications, on the other hand, are the areas where
substrate engineering is bringing unique values in
performance enhancement with cost efficiency. Adoption
of high-resistivity SOI in front-end module (FEM) is
rapidly in progress. Meanwhile, bonded SOS has been
proven to provide excellent RF performance with its
ideal Si crystal-quality and insulating substrate. Smart
CutTM is also extending applications in power electronics,
photonics, and MEMS applications, with its wide range
of flexibility in Si and BOX thicknesses. By combining
Smart StackingTM and Smart CutTM, various circuit
layers can be bonded onto another circuits, constructing
innovative multi-functional 3D devices, such as
intelligent image sensors, logic-memory stacked devices,
advanced photonics circuits, etc..
1. Introduction
For ever-increasing demand of high-speed data
processing and power reduction, it is now obvious that
the conventional bulk-Si CMOS technology can no
longer provide adequate solution with suppressing short
channel effect and process variability.
Among the various fully-depleted (FD) structures,
FinFETs and multi-gate structures are gaining support as
the solution [1]. However, there is still high barrier in
jumping from conventional planar technology to
three-dimensional structures in terms of development
cost and time. In this respect, planar fully-depleted (FD)
MOSFETs [2] are quite attractive to bridge this gap. By
using planar FD, the fabrication process can be
significantly simplified, bringing about efficient cost
reduction with offsetting the initial wafer cost of SOI.
Suppression of the body-floating effects in planar
FD-SOI brings minimized disruption in circuit design
when porting bulk-Si circuits to SOI. Production of
planar FD-SOI technology is about to be started in 28nm
node [3].
On the other hand, mobile communication product
978-1-4673-2475-5/12/$31.00 ©2012 IEEE
segment has recorded unprecedented growth in these
several years, associated with increasing data
communication by mobile handsets, and tablet
computers. The requirement in mobile RF components is
becoming more and more severe and complex as the
generation proceeds. In this presentation, substrate
engineering is shown to provide unique solutions in
radio-frequency front-end modules (RF-FEM).
On the other hand, the advantage of Smart CutTM
has been recognized in rather thick Si applications as
well, where Si is several hundreds of nanometers to
microns thick. These include power devices, photonics,
and MEMS applications, where strict control of Si
ensures stable device operation as well as enlarged
process margin. In this talk, recent progress of photonics
and future prospect are presented.
In the last part, extension of wafer bonding and
Smart CutTM to three-dimensional (3D) integration is
presented. Smart StackingTM enables low-temperature
(< 400 deg C) bonding between SiO2/SiO2, and Cu/Cu
layers. By using circuit layer transfer, various
multi-function stacked devices, which cannot be realized
by two-dimensional circuit layout.
2. Planar FD-SOI MOSFET technology
Recent benchmark [3] on 28nm technology using
representative IP blocks, showed that planar FD-SOI
consistently outperforms bulk CMOS in both low-power
and general-purpose applications. The process steps can
be saved by approximately 10% in planar FD-SOI due to
its simplified device structure, which well offsets the
cost overhead of SOI wafers. As for circuit design,
SPICE models for planar FD-SOI have been developed
and integrated in all major commercially available
simulators. Under this situation, it is easy to port the
design platform of bulk CMOS to that of planar FD-SOI.
Tuning or redesigning is only limited to a small number
of circuits, such as analog, and IOs. Back-biasing in
planar FD-SOI realizes multiple threshold voltages that
can be changed in a dynamic manner independently for
each circuit block. Moreover, it should be noted that the
option of co-integrating FD-SOI with bulk Si by
removing Si-film and BOX, allows for full utilization of
bulk-Si circuit IPs. The above discussion can be applied
to 20nm, and expectedly to 14nm.
SOI wafers for these planar FD-SOI technologies
have been developed and are now ready to support mass
production of LSIs. Fig.1 shows the technology roadmap
of SOI wafers for digital applications, where evolution
of planar FD-SOI (FD-2D) wafers and that for FinFET
structures (FD-3D) are shown.
3. Substrate engineering for RF front-end module
(FEM) applications
Due to the stringent requirements of 3G and 4G
standards, FEM of these generations consists of the best
choices of substrate chips in terms of RF performance
and cost-efficiency. GaAs has been the state-of-the-art
material for low-noise amplifier, but adoption of
high-resistivity (HR) SOI by Smart Cut is rapidly
increasing for switch applications in recent years.
Improvement on linearity, RF loss, etc., has been made
by using HR-SOI, while stability of the resistivity of the
substrate during device process has also been improved.
As compared with GaAs, HR-SOI provides a
cost-efficient solution, while its extendibility to system
integration on the Si platform is also very attractive.
On the other hand, bonded-SOS, is another option
when ideal isolating substrate is preferred. Wafer
bonding, made by Smart Stacking of Si layer onto a
sapphire substrate, realizes higher mobility and RF
performance than conventional SOS technology [4].
6. Summary
Substrate engineering by using Smart CutTM and
Smart StackingTM is extending the limit of state-of-art
technologies by providing atomic-level thickness control
and affluent options for material and circuit-layer
combination. They will go on playing an important role
in future electronics, where multi-functionality,
increasing data width, parallel processing, etc., are more
and more required.
Acknowledgments
The authors would like to thank Ms. Jocelyne
Wasselin, Mr.Keith Ito, and Mr. Thomas Piliszczuk,
Soitec, for their collaboration to this presentation.
References
[1] E.Karl et al.; Tech. Abst. of ISSCC, p.230 (2012)
[2] O.Faynot et al.; Tech. Abst. of IEDM, p.50 (2010)
[3] P.Flatresse et al.; http://www.soiconsortium.org/
[4] G.P. Imthurn et al.; Tech. Abst. of IEEE SOI Conf., p.1
(2011)
Soitec FD-3D
Soitec FD-3D Wafer wafers

Top Silicon Layer

Buried Oxide (BOx)

4. Substrate structures for Si Photonics

Base Silicon

FinFET G

As compared with digital applications, Si

D
Soitec FD-2D
SoitecFD-2D Wafer wafers

photonics uses rather thick Si (0.25–1um) and BOX

S
Ultra-Thin Top Silicon Layer
Ultra-Thin Buried Oxide Buried Oxide

(1-2um) to confine the photon signals in the waveguide. Base Silicon Base Silicon

Planar FDSOI
Nonetheless, control of Si thickness is strictly required to Undoped fully
depleted channel
S G D Foundry offering

realize stable propagation of the signals. To achieve Base Silicon

more efficient photonics system, efforts on hybridization Traditional

Planar bulk
First products expected at 28nm

of Si, Ge and III-V materials are under way to integrate S

G
D

Severe limitations at 28nm and 20nm End of life

all the functions in the system, including lasers, 40nm 28nm 20nm 14nm 10nm
modulators, filters, and detectors, etc..
Fig.1 SOI wafer roadmap for digital applications.
5. 3D integration by low-temperature wafer-to-wafer
bonding
With approaching limit of 2D-scaling, 3D •
•
Efficient pre- bond surface t reat m ent s
High bonding st rengt h at low t em perat ures
integration is now the inevitable technology for • Best in class W2W alignment accuracy at wafer level
• Com pat ible wit h TSV last t echnology for vert ical int erconnect ions
continuing performance improvement of LSIs, realizing • Compat ible wit h convent ional BEOL (Al, Cu, W, Ti); F2F and F2B st acking
more band-width, with minimized RC delay and the • Support ed by advanced m et rology (pre and post bonding)

form factor. Smart Stacking offers low-temperature ( <

400 deg C) wafer-to-wafer bonding for various 3D Bond/Align + Anneal

structures. BOX layer of SOI acts as efficient etch

CMOS

CMOS
Thin + TSV CMOS

stopper for multiple-layer stacking. By utilizing Oxide Dep + Planarization

TSV

TSV

SiO2-to-SiO2, or Cu-to-Cu bonding, various structures,

oxide
oxide
oxide
oxide oxide

such as sensor-to-logic, logic-to-logic, memory-to-logic, CMOS CMOS CMOS

MEMS-to-logic, can be realized, with sufficient bonding

energy and alignment accuracy, as shown in Fig.2. It
should be noted that combination of Smart CutTM and
Smart StackingTM brings about 3D-integration that
enables strict control of thicknesses by using various
materials, as well as vertical interconnection.
Fig.2 3D stacking by using oxide-oxide bonding, which
enables 3D integration with accurate wafer-to-wafer
alignment and vertical interconnections using TSV.