M

onolithic IC - Resistor Fabrication

Another diffusion technique is also used for the growth of IC resistors. It is
basically a thin-film technique. In this process a metal film is deposited on a
glass or Si02 surface. The resistance value can be controlled by varying
thickness, width and length of the film. Since diffused resistors can be
processed while diffusing transistors. This technique is more economic and
less time consuming and therefore, the most widely used.

 Capacitors

 Capacitors

The figure below shows the P and N-regions forming the capacitor plates. The dielectric of
the capacitor is the depletion region between them.

All P-N
junctions have capacitance so capacitors may be produced by fabricating junctions. The amount of
change in the reverse bias varies the value of junction capacitance and also the depletion width. The
value may be as less as 100 picoFarads.
 Usi
ng the silicon dioxide as a dielectric may also be a way to fabricate capacitors. One plate of the
capacitors is formed by diffusing a heavily doped N-region. The other plate of the capacitor is formed
by depositing a film of aluminium on the silicon dioxide dielectric on the wafer surface. For such a
capacitor, a voltage of any polarity can be used, and when comparing a diffused capacitor with such
a capacitor the diffused capacitor may have very small values of breakdown voltage.

Diodes

They are also fabricated by the same diffusion process as transistors are. The only difference
is that only two of the regions are used to form one P-N junction. In figure, collector-base
junction of the transistor is used as a diode. Anode of the diode is formed during the base
diffusion of the transistor and the collector region of the transistor becomes the cathode of the
diode. For high speed switching emitter base junction is used as a diode.

M
onolithic IC - Diode FabricationTransistors

The fabrication process of a transistor is shown in the figure below. A P-type substrate is first
grown and then the collector, emitter, and base regions are diffused on top of it as shown in
the figure. The surface terminals for these regions are also provided for connection.
 Monoi
lithic IC - Transistor Fabrication

Both transistors and diodes are fabricated by using the epitaxial planar diffusion process that
is explained earlier. In case of discrete transistors, the P-type substrate is considered as the
collector. `But this is not possible in monolithic IC’s, as all the transistors connected on one
P-type substrate would have their collectors connected together. This is why separate
collector regions are diffused into the substrate.

Even though separate collector regions are formed, they are not completely isolated from the
substrate. For proper functioning of the circuit it is necessary that the P-type substrate is
always kept negative with respect to the transistor collector. This is achieved by connecting
the substrate to the most negative terminal of the circuit supply. The unwanted or parasitic
junctions, even when reverse-biased, can still affect the circuit performance adversely. The
junction reverse leakage current can cause a serious problem in circuits operating at very low
current levels. The capacitance of the reverse-biased junction may affect the circuit high-
frequency performance, and the junction break down voltage imposes limits on the usable
level of supply voltage. All these adverse effects can be reduced to the minimum if highly
resistive material is employed for the substrate. If the substrate is very lightly doped, it will
behave almost as an insulator.

Step 1: First we choose a substrate as a base for fabrication. For N- well, a

P-type silicon substrate is selected.

Substrate
Step 2 – Oxidation: The selective diffusion of n-type impurities is
accomplished using SiO2 as a barrier which protects portions of the wafer
against contamination of the substrate. SiO2 is laid out by oxidation process
done exposing the substrate to high-quality oxygen and hydrogen in an
oxidation chamber at approximately 10000c

Oxidation
Step 3 – Growing of Photoresist: At this stage to permit the selective etching,
the SiO2 layer is subjected to the photolithography process. In this process,
the wafer is coated with a uniform film of a photosensitive emulsion.

Growing of
Photoresist
Step 4 – Masking: This step is the continuation of the photolithography
process. In this step, a desired pattern of openness is made using a stencil.
This stencil is used as a mask over the photoresist. The substrate is now
exposed to UV rays the photoresist present under the exposed regions of
mask gets polymerized.
 Masking of
Photoresist
Step 5 – Removal of Unexposed Photoresist: The mask is removed and the
unexposed region of photoresist is dissolved by developing wafer using a
chemical such as Trichloroethylene.

Removal of
Photoresist
Step 6 – Etching: The wafer is immersed in an etching solution of
hydrofluoric acid, which removes the oxide from the areas through which
dopants are to be diffused.
 Etching of SiO2
Step 7 – Removal of Whole Photoresist Layer: During the etching process,
those portions of SiO2 which are protected by the photoresist layer are not
affected. The photoresist mask is now stripped off with a chemical solvent
(hot H2SO4).

Removal of
Photoresist Layer
Step 8 – Formation of N-well: The n-type impurities are diffused into the p-
type substrate through the exposed region thus forming an N- well.
 Formation of N-
well
Step 9 – Removal of SiO2: The layer of SiO2 is now removed by using
hydrofluoric acid.

Removal of SiO2
Step 10 – Deposition of Polysilicon: The misalignment of the gate of a CMOS
transistor would lead to the unwanted capacitance which could harm
circuit. So to prevent this “Self-aligned gate process” is preferred where
gate regions are formed before the formation of source and drain using ion
implantation.
 Deposition of
Polysilicon
Polysilicon is used for formation of the gate because it can withstand the
high temperature greater than 80000c when a wafer is subjected to
annealing methods for formation of source and drain. Polysilicon is
deposited by using Chemical Deposition Process over a thin layer of gate
oxide. This thin gate oxide under the Polysilicon layer prevents further
doping under the gate region.
Step 11 – Formation of Gate Region: Except the two regions required for
formation of the gate for NMOS and PMOS transistors the remaining portion
of Polysilicon is stripped off.

Formation of Gate
Region
Step 12 – Oxidation Process: An oxidation layer is deposited over the wafer
which acts as a shield for further diffusion and metallization processes.
 Oxidation Process
Step 13 – Masking and Diffusion: For making regions for diffusion of n-type
impurities using masking process small gaps are made.

Masking
Using diffusion process three n+ regions are developed for the formation of
terminals of NMOS.
 N-diffusion
Step 14 – Removal of Oxide: The oxide layer is stripped off.

Removal of Oxide
Step 15 – P-type Diffusion: Similar to the n-type diffusion for forming the
terminals of PMOS p-type diffusion are carried out.
 P-Type Diffusion
Step 16 – Laying of Thick Field oxide: Before forming the metal terminals a
thick field oxide is laid out to form a protective layer for the regions of the
wafer where no terminals are required.

Thick Field oxide

Layer
Step 17 – Metallization: This step is used for the formation of metal
terminals which can provide interconnections. Aluminum is spread on the
whole wafer.
 Metallization
Step 18 – Removal of Excess Metal: The excess metal is removed from the
wafer.
Step 19 – Formation of Terminals: In the gaps formed after removal of
excess metal terminals are formed for the interconnections.

Formation of
Terminals
Step 20 – Assigning the Terminal Names: Names are assigned to the
terminals of NMOS and PMOS transistors.
Photolithography is the process of transferring geometric shapes on a mask to the
surface of a silicon wafer. The steps involved in the photo-lithography process are
wafer cleaning barrier layer, formation photo-resist applications soft baking, mask
alignment, exposure and development and hard baking.
Wafer cleaning, Barrier formation and photo-resist application :
In the first step, the wafers are chemically cleaned to remove particulate matter on
the surface as well as any traces of organic, ionic and metallic impurities.
After cleaning, silicon dioxide, which serves as a barrier layer is deposited on the
surface of the wafer.
After the formation of the Sio2Sio2 layer, photo resist is applied to the surface of the
wafer.
High speed centrifugal whirling of silicon wafers is the standard method for applying
photo-resist coatings in MEMS manufacturing.
This technique known as "spin coating" produces a thin uniform layer of photo-resist
on the wafer, surface.
Positive and Negative photoresist :
There are two types of photo-resist : Positive and Negative.For positive resist the
resist is exposed with UV light wherever the underlying material is to be removed. In
these resists, exposure to the UV light changes the chemical structure of the resist
so that it becomes more soluble in the developer. The exposed resist is then washed
away by the developer solution, leaving windows of the bare underlying material.
Negative resists behave in just the opposite manner. Exposure to the UV light
causes the negative resist to become polymerized and more difficult to dissolve.
Therefore the negative resist remains on the surface. Wherever it is exposed and the
developer solution removes only the unexposed portions masks used for negative
photo-resist, therefore contain the inverse of the pattern to be transferred.
Soft - Baking :
Soft - baking is the step during which almost all of the solvents are removed from the
photo-resist coating. Soft baking plays a very critical role in photo imaging. The
photoresist coatings become photosensitive, or imageable only after soft baking
oversoft - baking will degrade the photo-sensitivity of resists by either reducing the
developer solubility or actually destroying a portion of sensitizer.
Under soft-baking will prevent light from reaching the sensitizer. Positive resists are
incompletely exposed if considerable solvent remains in the coating. This under soft-
baked positive resists then readily attacked by the developer in both exposed and
unexposed areas causing less etching resistance.
Mask alignment and exposure :
One of the most important steps in the photo-lithography process is mask alignment.
A mask or "photo mask" is a square glass plate with a patterned emulsion of metal
film on one side. The mask is aligned with the wafer, so that the pattern can be
transferred onto the wafer surface. Each mask after the first one must be aligned to
the previous pattern once the mask has been accurately aligned with the pattern on
the wafers surface, The photo-resist is exposed through the pattern on the mask with
a high intensity UV light.
There are 3 primary exposure methods:
Contact, proximity and projection.
Development :
At low exposure energies the negative resist remains completely soluble in the
developer solution. As the exposure is increased above a threshold energy move of
the resist film remains after development. At exposures two or three times the
threshold energy, very little of the resist film is dissolved. For positive resist, the
resist solubility in its developer is finite even at zero exposure energy. The solubility
gradually increases until, at some threshold, it becomes completely soluble.
Hard - Baking:
Hard - Baking is the final step in the photolithography process. This step is
necessary in order to harden the photo-resist and improve adhesion of photo-resist
to the wafer surface.