6th IEEE International Test Conference India (ITC India) - 2022

TSV BIST Repair: Design-For-Test Challenges and

Emerging Solution for 3D Stacked IC’s
Akkapolu Sankararao Vaishnavi G Sandya Rani Malige
AMD India Pvt. Ltd. AMD India Pvt. Ltd. AMD India Pvt. Ltd.
Bengaluru, India Bengaluru, India Bengaluru, India
Sankararao.Akkapolu@amd.com VAISHNAVI.G@amd.com sandyarani.malige@amd.com

Abstract—The efficient methodology to increase the yield and in TSV are due to inappropriate manufacturing process at lower
performance of 3D Stacked Integrated-Circuits (3D SICs) using technology nodes[7]. Common other defects such as –
2022 IEEE International Test Conference India (ITC India) | 978-1-6654-9962-0/22/$31.00 ©2022 IEEE | DOI: 10.1109/ITCINDIA202255192.2022.9854518

TSV BIST Repair mechanism is addressed in this paper. This misalignment, height variation, induced thermal stress causing
technique provides a promising solution to overcome power and delamination, isolation leakage between the different substrate,
interconnect congestion issues encountered during TSVs pre-bond inappropriate copper fillings, impurities between TSV pillar and
and post-bond tests of 3D stacked ICs. The proposed TSV BIST stacking surface (micro-bump), etc.[8][9].
Repair approach has the ability to identify short, open, pin-hole,
void and break defects in TSV bonding. In response to these In this paper, we provide brief in-sight on the requirement of
defects, the repair mechanism will provide redundancy analysis 3D-Stacked ICs and their challenges. Further, an overview on
and repairable features to defective TSVs. Finally, the complete how effective the existing test solutions and need for the new
analysis of the proposed TSV BIST repair methodology shows test methodology to address those challenges are discussed. This
significant improvement of 14.5% yield and test cost by potentially paper is organized as below – In Section II, we walk through the
recovering all eminent defective chips. existing TSV based 3D Stacked ICs test technique challenges.
In Section III, detailed architecture of the proposed methodology
Keywords—3D ICs, Stacked ICs, TSV, BIST, void, redundancy. for TSV BIST Repair in 3D Stacked ICs are discussed and yield
I. INTRODUCTION analysis, test time results from proposed methodology are
reported in Section IV. Section V gives the challenges and future
The semiconductor industry has huge scope for scope of the paper and finally concludes in section VI.
miniaturization due to shrinking technology node. As per
Moore’s law, the semi-conductor industry has been II. MOTIVATION FOR TESTING 3D IC
manufacturing efficient dies and their application has great The standard available process for TSV fabrication has
market in electronic gadget. Due to reduced technology node relatively low yield compared to standard 2D processes [10].
and doubling of the transistor count, there is test cost and When designers embrace TSV-based 3D IC technology, the
performance challenge on connecting wires in the dies or unwanted loss in yield and performance occur if via fails to
stacked ICs [1][2]. To overcome these challenges, three make proper connection. Thus, the test techniques and design
dimensional integrated circuits (3D ICs) have been the intact for testability (DFT) solutions as mentioned in fig.1 for TSV-
solution. This urges to integrate multiple functionality IP Cores based 3D ICs design have become hot topic in research
on one die which is called System-on-Chip (SoC), many chips industry[2]-[5].
or dies mounted in one package which is called Multi-Chip-
Package (MCP). With the help of through-silicon-vias (TSV’s)
these ICs have high chance of reducing interconnect delay but
also result in increased area overhead. Stacking die vertically
and inter-connecting the stacked die using TSVs, helps achieve
extremely high chip-to-chip bandwidth with shorter
interconnect length[3]. Stacking using TSV’s completely
eliminates the need for wire-bonding and helps drive increased
package density, tighter package design and smaller package
body[4].
In fact, the interconnection of various tiers/layers using
TSVs intend to result in high interconnect bandwidth and
performance while decreasing manufacturing cost and reduced
power dissipation [5][6]. Due to increased scaling rate and
design complexity, there is high chance of manufacturing
defects at TSV levels. TSVs can be compared like a silicon
which has data transmission lines inside them. Anyhow, some Fig. 1. Flow chart of Stacked 3D IC
defects like void formation, open and short fault due to leakage

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A. Pre-bond TSV Test
A Pre-bond (known-good-die) test is for single die or wafer
before it goes under stacking process. This technique is effective
in providing yield result of individual dies [9][11]. KGD test
mainly targets on testing of TSV logic where interconnect bond
occurs between dies. In addition, this test urges to target logic of
die and various clock networks and power connections [12]. It
is required to assure the die is fault-free because a faulty die will
unlikely result in discarding of entire stacked IC with huge hit
on test cost. This test is intended to detect all the TSV related
defects caused during manufacturing process such as void
formation or inappropriate impurities in TSVs. Pre-Bond test is
referred as a screening process which provides fault-free wafer
or dies as the inputs to stacking ICs[13]-[15].
In addition to detection of faulty dies, pre-bond test provides
diagnosis of defects and local repair of fault are performed
before TSV bonds with other dies [16]. As TSVs play an
important role in connecting two dies, there are high chance for
pre-bond defects which aggressively affects the functionality of
the chip. Some of the common reasons for the TSV failures at
early stage are microvoid, pinhole, electromigration, thermal
and physical stress[17]. These defects might cause high power
consumption and high thermal condition which results in large
physical stress in TSVs. Early screening of these defects is
important and should be part of the KGD test.
Pre-bond test has various challenges with respect to test
accessibility due to limited TSV pitch and test probe diameters.
Multiple BIST techniques are introduced in pre-bond test
techniques, but they take back seat as this BIST architecture are
not effective in detecting the TSV faults near or at end of the-
active device layer of interconnect[18]. This is due to bulk
placement of TSVs closest to each other in the BIST
architecture. Furthermore, the circuits of parametric test are not
highly calibrated in BIST techniques as they vary with
parameters resulting in large hit on yield accuracy of the dies.
B. Post-bond TSV Test
A Post-bond (known-good stack) testing is crucial when
TSV interconnects between to wafer dies. In manufacturing
process known-good-stack (KGS), bonding technology is
incorporated during die stacking. There might be high chance
for TSVs bonding to fail during fabrication, resulting in discard
of multiple stacked dies. This hits severely on SoC cost and
trade-off occurs between yield and number of dies stacked. As
technology node shrinks, the size of TSV will become quite
bigger than other SoC devices. This results into different defects
in TSV such as – void formation, in-appropriate metal filling,
breakage in TSV due to stress and various factors. More the
number of stacked dies, there is high chance for TSV to fail due
to manufacturing defects.
When all the dies or wafers to be vertically stacked are all
known-good-dies, then it will be easy to report the failures
caused on the stacked dies. Statistical data from below graph
provides detailed analysis on impact of yield due to variable
defective TSVs identified during post-bond test [19]. This will
be mainly due to the inappropriate TSV bonding between the
dies or defect in the TSV itself during metal etching process.
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However, taking into consideration of test cost the
reasonable solution will be to repair the failing bond between
dies as small amount of TSV would fail on stacked ICs. Repair
mechanism improves the yield and test cost of the stacked ICs
[19]. This paper proposes TSV BIST Repair mechanism which
efficiently identify the defects and repair detected defective
TSVs with quite area overhead , improved test cost and yield
improvement [20].
III. PROPOSED TSV BIST REPAIR MECHANISM
In this section we discuss the new proposed methodology of
TSV BIST and Repair mechanism. The proposed architecture
for TSV BIST Repair mechanism as shown in the below fig.2.
Here we considered in 3D Stacked IC the bottom die acts as
master die, and the dies on the top of bottom die acts as slave
dies or stacked dies. So, the TSVs are placed in between master
and stacked dies.
The TSVs are designed in such way that it is consisting of
separate transmitter (TX) and Receiver (RX) parts of TSVs. To
reduce the testing complexity, cost and increase the yield of
TSVs we need to group the TSVs and then tested, the grouping
methodology reduces the test time and cost by targeting all the
TSVs in a group at a time. The size of the TSV group depends
on the number of TSVs present in individual blocks and physical
location of the TSVs. Usually, TSVs in the same block grouped
and tested together. In proposed methodology the TSV read or
write groups consists of 50-75 TSVs in each group. If there any
faulty TSV identified by TSV BIST, it could be repaired by TSV
BIST Repair mechanism. In this proposed methodology, we
include up to 2 redundant TSVs for each group.
The Proposed TSV BIST architecture consists of TSV BIST
master on the master die and TSV BIST slave on the stacked
dies. The TSV master controls the complete execution and has
all the data generation and comparators. The TSV slave also
have the data generators, but there are no comparators on it.
Always the data comparison happens in master die. The master
TSV BIST and slave TSV BIST controllers communicate to
each other and always synchronized by using control signal
(TSVBIST_CONTROL) going from base die to stacked dies.
Since the TSV needs to be tested at-speed, if there are multiple
clock domains, one or more TSV BIST masters needed for each
clock domain.
For each TSV macro 2 MUXs are added, one at Transmitter
side and another one at Receiver side to Shift the signals to next
TSV when any one of the TSV failed. These Mux’s are called
Repair MUX’s. To overcome the timing effect and capturing the
 Fig. 2. Proposed Architecture for TSV BIST Repair in 3D Stacked IC’s

BIST responses a pair of flops and buffers are added to each based on the contents of a shift register, that is as wide as the
TSV and connected as a chain. All the signals are passing width of the read group. The Read paths traversing from stacked
through original TSVs when there is no TSV failed. When a die to base through the TSV BIST data muxs and flops as shown
TSV is failed, it is replaced with Redundant TSV by shifting all in fig.3
signals between failing TSV and Redundant TSV.
In this proposed methodology, we created 2 types of TSV
groups - TSV Read groups and TSV Write groups. Read groups
are ones that drive the data from stacked (slave) die to the base
(master) die. Write groups drive data from the base die to the
stacked die. Here one group will be tested and repaired at a time
before moving to the next group until all groups have been tested
and repaired. Within a group, different data patterns are applied
to expose different potential faults. The testing of read group and
write group TSVs are different, and it was explained in detail in
below sub-section.
The TSV BIST master and redundance units identify the
failing TSVs and calculates the repair signature and stored it into
the fuse controller. The fuse controller consisting of read only Fig. 3. TSV Read Group data path in 3D SIC’s
memory device and stores all the TSVs repair signature
information. TSV BIST enables the TSV fuse repair distribution After applying all the data patterns to the read group, if there
mechanism to distribute the repair information to the redundant are any failures, the TSV BIST pauses the execution and
TSV locations. TSV BIST controller also provides the Redundancy Analysis unit calculates the repair signature and it
mechanism to select the TSV group between different layers of will be stored in Fuse Controller of the TSV BIST. The fuse
stacked dies. There are some diagnostic capabilities provided by controller accumulates all the repair information and sends the
TSV BIST that are like memory BIST bitmapping. Spare TSVs repair information to TSV master to repair the failing TSVs by
are only tested if they are needed for a repair, otherwise they replacing the failing TSV with Redundant TSV in that particular
remain untested. group. The TSV BIST master is notified if a repair is needed or
A. TSV Read Group Test not based on repair status register values.
TSV Read groups are formed based on the TSVs which The fig.4 shows the basic read operation performed for the
sends the data from Stacked dies to Base die. The TSV BIST read groups based upon the number of layers. Here we
data mux on the stacked die takes the TSV BIST data and sends considered 3 different scenario of stacked dies, one layer, two
the data through one flop and buffer on the stacked die, and layers and four layers stacked dies. For each scenario the read
similarly other buffer and flop on the Base die before comparing operation will execute from stacked die to base die for different
it with the expected BIST response data. In this read path there groups is represented with arrow paths.
are 2 flops in the data chain and total of four data patterns applied
and compared. Here these four basic data patterns are applied
multiple times until all the potential defects identified in the read
group. There can be inversions applied to the basic data pattern

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Fig. 4. TSV Read Group data path in multi-layer 3D SIC’s Fig. 5. TSV Write Group data path in multi-layer 3D SIC’s

The repair status register consists of two bits per group. Similar to Read group testing, after applying all the data
Group 0 would occupy bits 1:0, group 1 would occupy bits 3:2 patterns to the Write group, if there are any failures, the TSV
and so on up to the maximum number of groups. BIST pauses the execution and Redundancy Analysis unit
calculates the repair signature. The fuse controller accumulates
TABLE I. TSV BIST REPAIR STATUS REGISTER all the repair information and sends the repair information to
Repair Status TSV master to repair the failing TSVs by replacing the failing
Description
Register Value TSV with Redundant TSV in that group.
2'b00 No repairs
2'b01 One repair The diagram referring to fig.5 shows the basic write
2'b10 Two repairs operation in 3D Stacked IC’s. Here we considered 3 different
2'b11
Non-Repairable: more than two repairs needed scenario of stacked dies, one layer, two layers and four layers
stacked dies. For each scenario the write operation executed
from base die to stacked die and reading back to the base die for
This register applies to all the layers in stacked dies. In this different groups is represented with arrow paths.
grouping mechanism we are using 2 redundant TSVs for each
group, so up to 2 repairs are possible per group. If the number of
failing TSVs exceeds more than 2, then a fatal error will be
generated and those TSVs are non-repairable TSVs. The lower
order bits of the repair status register belong to the read groups,
while the upper order bits apply to the write groups. The table-
I shows the meaning of the 2-bit repair status register for each
group.
B. TSV Write Group Test
Once all the TSV read groups testing completed, the TSV
BIST moves on to test the write groups. Since the TSV write
groups are formed based on the TSVs which sends the data from
base dies to stacked die and read back to the base die. Here the
TSV BIST data mux on the base die takes the TSV BIST data Fig. 6. TSV Read Group data path in 3D SIC’s
generated by TSV master data generator and sends the data to
stacked dies through flops, and the stacked dies loops back this The fig.6 shows how the write paths traversing from base die
data down through read group to the base die. There are total of to stacked die and loopback to the base die through the TSV
4 flops in this path and the data generator cycles over four BIST data muxs and flops.
different data patterns so that the TSV master comparator will 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
be lined up with the correct expected data once it has traversed Repair Signature [20:31] TSV Group ID [11:19] TSV Group Column [0:9]
through the loopback path back to the base die. The testing of Fig. 7. TSV BIST Fuse Register
write groups includes the read group also, since the same set of
data patterns are applied as in testing the read groups. If there The generalized fuse register shown in the fig.7. The master
are more write groups than read groups, some read groups will die consists of the Fuse Controller, and it has all the stored fuse
be utilized more than once in testing the write groups. The read values, and those fuses are burned once the system is powered
groups are paired with write groups to feedback the write group
on. Each fuse register consisting of 32-bit data, and it has
data to the base die.
different subgroups in order to identify the specific TSV group,
redundant element and corresponding repair signature.

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 IV. RESULTS TABLE II. YIELD ANALYSIS

In this paper, the performance of proposed TSV BIST Repair
mechanism test structure w.r.t different layers of 3D stacked ICs
are analyzed. The yield analysis was performed and compared
with help of industrial results between the proposed TSV BIST
Repair methodology and standard TSV BIST approach. Here,
we considered the dies which are going for stacking are fault
free die, since it was already tested during pre-bond testing. One
of the reasons for yield loss in 3D stacked ICs is due to the faults
existing during TSV bonding process. There are various 3D
DFT test methods developed for detecting and repairing faulty
TSVs for yield improvement in 3D Stacked ICs. Further, we
have observed a significant yield improvement w.r.t the
proposed method, grouping (TSV read group and write group)
and testing of TSV’s based on the data transmission between
dies.
Currently, the proposed methodology is implemented in our
design production and the dies which are stacked in SoC’s are
heterogenous and belongs to different technology nodes.
Whereas the standard TSV BIST approach was implemented
previously and here the stacked dies are homogeneous and are
from same technology node. The cost and test complexity of
heterogenous 3D stacked dies from different technology node is
very high and expensive. The experiments are performed and
analyzed on 4 layers and 6 layers of 3D Stacked IC’s and
compared the yield and test time results of proposed TSV BIST
Repair method with standard TSV BIST Repair approach. The
proposed TSV read or write groups consisting of an optimal
number 50-75 TSV’s per group.
The data has been analyzed in two sets of 3D stacked IC’s,
one for 50K stacked dies and the other for 100K stacked dies,
which have been tested in ATE at post-bond testing time after
completion of the pre-bond or KGD test.
With the Proposed TSV BIST Repair approach for testing of
50K stacked IC’s the yield is 95% and 91% w.r.t 4 layers and 6
layers stacked dies. For the same number of stacked IC’s, the
conventional TSV BIST Repair method gives yield of 81% and
76% w.r.t 4 layers and 6 layers stacked dies. Similarly, the
industrial results are compared for 100K stacked ICs, the
proposed TSV BIST Repair approach gives 89% and 86% w.r.t
4 and 6 layers of stacked ICs. Whereas in case of standard TSV
BIST method gives 74% and 68% w.r.t 4 and 6 layers of stacked
dies. The detailed yield analysis results are summarized in table-
II. The industrial results proven that a significant improvement
in the design yield, the average yield improvement is 14.5%.
Stacked No. of Stacked dies tested
Yield
Die 50000 100000
Standard 4 layers 81% 74%
Approach 6 layers 76% 68%
Proposed 4 layers 95% 89%
Approach 6 layers 91% 86%
The proposed TSV BIST Repair approach also improves the
average testing time of a staked die. The standard approach takes
on an average of 1.42sec to test complete stacked IC, where the
proposed methodology completed the test with average of 1.18
sec., so the average test time reduction is ~17%.
V. CHALLENGES AND FUTURE SCOPE
The main challenges encountered in the proposed TSV BIST
Repair mechanism are mainly, the area overhead issue observed
due to additional BIST logic insertion for TSV test and also
requirement of additional dedicated memory for TSV repair
signature storage in Fuse logic. During verification of TSVs at
pre-silicon stage, requirement of stacked testbench creation and
additional boot-up sequence for TSV test in 3D stacked device
is another potential drawback. Currently semiconductor industry
research trend is moving towards addressing TSV test
challenges.
VI. CONCLUSION
In this paper, we proposed a novel 3D stacked IC testing and
Repair mechanism. This architecture focus on detecting all the
possible defects during the TSV bonding process, diagnosing,
and repairing all the defects of TSVs in 3D stacked ICs. In this
methodology we introduced a novel TSV grouping, and testing
approach based on Read and Write operations. The test results
performed with new proposed TSV BIST Repair methodology
are analyzed. As a result, a significant improvement in the 3D
stacked IC yield with minimal area overhead is observed. On
ccomparison with conventional approach, the proposed
methodology gives an average of 14.5% hike in yield. The
proposed approach not only targets the yield improvement, but
also provides the great impact in test time reduction of 17%
compared to conventional approach.
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