Professional Documents
Culture Documents
Physical Design
Ganesh Prabhu C
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WARNING !!
report timing
Write netlist
Technology Information
S
Logic Diagram
Truth Table A
A B S Z
1 0 0 1 S S Z
1 0 1 0
Logic Equation B
Z = S.A + S.B
endmodule
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A Sequential Design
M1 D Q
C
A
S S Z D Q MOut
M2 D Q
C C
B
MSel D Q
MClk C
VDD N N
Source
Gate
P – Well
Drain
A Z
Gate
Drain Source Drain
Gate
Source P P
VSS N – Well
Source
VDD
VDD
N
Gate
Source
P – Well
Gate
A
N
Drain
A Z
Drain
Drain
Z
Drain
Gate
Source
P
Gate
VSS
N – Well
Source
VSS
Source
Gate
Drain
A Z A Z A Z
Drain
Gate
Source
VDD
Source Source
VDD
Gate
A Source
B Drain Drain
Z B
Drain
A Gate
Z
Source A Source Drain
B Gate VSS
Source
VSS
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MUX Layout
A VDD
B VDD
VDD A
Source Drain
Source Drain
B
VSS
VSS
A
Source Drain
Source Drain
VSS
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Need for Floorplan
Bed Room 1
Kitchen
Living Room
Entrance Exit
Bed Room 2
Verilog Netlist
Timing Constraints
Floorplanning Floorplan
Library Abstract Views
DEF
Library Timing Views
Technology Information
Why floorplanning is required
Exit
Kitchen Bath Toilet
Logic Gates Logic
Bedroom 2 Gates
Dining Hall
Hall
Bedroom 1 Memories
IOs
Entrance
cells = 0.25
⚫ Site Name
⚫ What is a Site Name ?
Site defines the placement site in
a design
Eg : Core Site / IO Site / Macro Site
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Pre-Placement Steps
⚫ Row Creation
⚫ Pin Placement
⚫ Macro Placement
⚫ Halo and Blockage creation
⚫ Power Planning
⚫ Boundary Cell / Endcap Cell Placement
⚫ Well Tap Placement
3 Sites
Verilog Netlist
Timing Constraints
Library Abstract Views
Power Floorplan
Planning DEF
Library Timing Views
Floorplan DEF
Technology Information
Power Distribution Network
⚫ Function of Power Distribution Network
Cary current from pads to transistors
on chip
Maintain stable voltage with low noise
Provide average and peak power
demands
Provide current return path for signals
Avoid electromigration
Consume little chip area and wire
Easy to create layouts
VDD
⚫ How Power Distribution Network is VSS
created ?
PG Ring
PG Stripes
VDD
VDD
PAD
Reference : https://www.synopsys.com/glossary/what-is-electromigration.html
Supply
Ground
P+ N+ N+ P P N
N–Well
P – Substrate
Gate A Gate
VSS VDD
Z
P+ N+ N+ P P N
R-Well
R-sub
N–Well
P – Substrate
E C
B
C
B
Data
D Q D Q Data Out
C C
Clock
Clock Net
Data
D Q D Q Data Out
Clock
Launch Clock
Min Delay Max Delay
Capture Clock
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Different Clock Parameters
⚫ Clock Skew
Difference in clock arrival time at Q1
two different flops
Clock
⚫ Clock Jitter
Difference in clock period Q2
Clock arrival
reduced timing path
at Q1
Skew
reduced timing path
Clock arrival
at Q2 Clock Jitter
Ideal clock arrival at Q1 and Q2 Flops t1 t2
t1 = t2
Why do clock skew and jitter arise
⚫ Clock Generation
⚫ Clock Distribution Network
Cells in clock network
Variation in transistors in
clock network
Wire length
Coupling effects
Load effects
⚫ Environment Variation
Temperature
Supply Voltage
Launch Clock
Capture Clock
Launch Clock
Capture Clock
with +ve skew
+ve Skew
⚫ Clock networks are huge and they are responsible for large portion
of total chip power
⚫ Standard Approach:
Try to build a balanced tree
Clock tree elements are not
balanced evenly
PLL
⚫ Hence:
We will pre-route the clock nets during CTS
Use higher and thicker metals for clock routing
Offers low resistance
Offers less cap with the substrate
Apply shielding to clock nets
Consider adding DECAPs close to clock buffers
A Track 4
Source Drain
Reference : Signoffsemi.com
tcombo
Q D Q
tcq tsu
C C
Launch Path
Clock Net
Capture Path
D Q D Q
Launch Path C C
Clock Net
Capture Path
Setup Checks :
Data Path with max delay + derate factor ⚫ Applying CRPR limits the pessimism
Clock Launch Path with min delay + derate factor of OCV
Clock Capture Path with min delay – derate factor
Hold Checks : ⚫ This removes the derating from the
Data Path with min delay – derate factor clock path shared by both lauch and
Clock Launch Path with min delay - derate factor
Clock Capture Path with max delay + derate factor
capture paths
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