12-1
Non-Gaussian Distribution of SRAM Read Current and Design Impact
to Low Power Memory using Voltage Acceleration Method
Joseph Wang, Ping Liu, Yandong Gao, Pankaj Deshmukh, Sam Yang, Ying Chen, Wing Sy, Lixin Ge, Esin Terzioglu,
Mohamed Abu-Rahma, Manish Garg, Sei Seung Yoon, Michael Han, Mehdi Sani, and Geoffrey Yeap
Qualcomm Inc, 5775 Morehouse Drive, San Diego, CA 92121
Abstract
SRAM read current tail distribution beyond 6σ was studied
using Voltage Acceleration Method (VAM). For the first time,
non-Gaussian distribution of SRAM and ROM read current
was confirmed with direct measurements on actual silicon.
Data shows that conventional assumption of Gaussian
distribution in read current is inaccurate especially at low Vdd
and cold temperature conditions for low power memory in
28nm and beyond technology nodes. In 28nm, this inaccuracy
would lead to 2x bit access delay penalty.
Introduction
SRAM Vccmin has been one of the most critical challenges
in silicon technology scaling. The impact of process variation
on static noise margin (SNM) and write margin (WRM) has
been extensively studied [1, 2]. However, SRAM Vccmin is
limited not only by SNM and WRM, but also by read current
(Iread) distribution for a given sense amp design and
performance (CV/Iread) target. Due to the ever increasing
SRAM bit count in mobile SOC design, 6σ design margin is
required to achieve high manufacturing yield. Accurate
prediction of Iread distribution at 6σ and beyond is critical to
SRAM design. The conventional approach [3] assumes Iread
follows Gaussian distribution so that Iread (6σ) can be
extrapolated as (μIread – 6*σIread) where σIread and μIread are
measured from limited sample sizes [4]. Fig.1 shows that it is
inceasingly more difficult in following conventional design
approach especially in 28nm and beyond. Iread (6σ) is so small
that bit access delay (CV/Iread) becomes not only very large,
but also extremely sensitive to variation in sigma. Setting
design margins in this case becomes extremely challenging.
Even though earlier simulation study [5] indicates the
conventional approach underestimates Iread, it was never
verified on actual silicon. In this work we used VAM to
measure Iread at 6 σ from actual silicon, and studied their
impact to low power memory design.
Measuring Iread at Six Sigma and beyond
Directly measuring 6σ Iread on silicon is very difficult
because one would need to measure Iread of each individual bit
cell from a very large array (>64Mb). However, the series
connected SRAM PG and PD transistors can be treated as a
single transistor with very small DIBL and having effective Vt,
Vteff. Thus Vteff can be considered independent of Vdd. Local
Iread variation is dominated by Vt mismatch and can be treated
as a function of gate overdrive, ‫ܫ‬௥௘௔ௗ ൌ ݂൫ܸௗௗ െ ܸ௧௘௙௙ ൯. One
important implication from the equation is that, lowering Vdd
has the same effect on Iread as increasing Vt. For example, 6σ
Iread can be written as,
‫ܫ‬௥௘௔ௗ ሺܸௗௗ ǡ ͸ߪሻ ൌ ݂ൣܸௗௗ െ ܸ௧௘௙௙ ሺ͸ߪሻ൧ ൌ ݂ൣሺܸௗௗ െ οܸሻ െ
ܸ௧௘௙௙ ሺ͵ߪሻሿ ൌ ‫ܫ‬௥௘௔ௗ ሺܸௗௗ െ οܸǡ ͵ߪሻ, (1)
where οܸ ൌ ܸ௧௘௙௙ ሺ͸ߪሻ െ ܸ௧௘௙௙ ሺ͵ߪሻ ൌ ͵ߪܸ௧௘௙௙ .
Eq. (1) means that 3σ Iread measured at (Vdd - 3σVteff) equals
6σ Iread measured at Vdd. This is the basic idea of VAM for
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measuring high σ tail distribution of Iread. It is well known that
Vt follows Gaussian distribution. As shown in Fig. 2, at high
Vdd, Iread is linearly related to ܸௗௗ െ ܸ௧௘௙௙ and thus also
follows Gaussian distribution. But when ܸௗௗ െ ܸ௧௘௙௙ is small
and transistors approache subthredshold domain, Iread vs.
ܸௗௗ െ ܸ௧௘௙௙ becomes exponential, and Iread distribution will
become non-Gaussian.
This theory was verified using 1Kbit serial addressible
SRAM & ROM array to collect Iread from 1024 bitcells in a
28nm low power SOC process [6]. Iread was measured at
multiple Vdd from 0.7 to 1.1V, at 25C and -30C. Data was also
collected from silicon with different Vt splits. Monte Carlo
(MC) simulation was performed using VAM and result was
compared to Si and simulation using ISMC method [5].
Silicon Results and Impact to Design
Silicon result comfirmed our analysis. As shown in Fig. 3, at
lower Vdd, Iread distribution is no longer Gaussian, rather it
approaches Log-Normal distribution. Only at higher Vdd it
remains close to Gaussian distribution. This is the first time
non-Gaussian Iread distribution has been confirmed on Si. The
non-Gaussian distribution of Iread becomes more prominent at
lower Vdd, because of reduction in Vdd-Vt. Lower temperature
results in lower Iread (Fig 4). In cumulative probability plot
(CPP) of Iread (using Gaussian scale with sigma as unit) at
different Vdd, ΔVdd/Δσ are a constant (Fig. 3). In this
experiment, ΔVdd=50mV, Δσ=2.0, and ΔVdd/Δσ=25mV,
which matches closely with σVteff of 24.6mV measured from
Si. As shown in Fig. 5, we constructed a single Iread CPP at
0.95V by shifting Iread CPP at each Vdd in y-axis by
(0.95-Vdd)/0.025 sigma. The result is a perfectly overlaped
single Iread CPP up to 12 sigma. Similar result was observed
for ROM (Fig. 5 insert). Data from different Vt splits (Fig 6)
show that constant Vt shift results in constant shift in σ value of
Iread distribution. Fig. 7 shows MC simulation result using
VAM matches very well with that using ISMC simulation. Fig.
8 shows silicon Iread distribution matches closely with result
from MC simulation using VAM. The small difference
between them is due to Si Vt offset.
Fig. 9 shows that if we assume Gaussian distribution for Iread,
6σ design would have 2x as much CV/Iread delay as necessary
resulting in unecessary performance/power/area penalty.
Another important finding is that actual Iread decreases much
slower over sigma than predicted by Gaussian distribution. As
a result, CV/I is much less sensitive to Vt variation at higher σ,
giving room for low power memory design to achieve better
performance even at very low Vdd.
Conclusion
We have developed a novel method (VAM) to measure read
current distribution beyond 6 sigma and confirmed the
non-Gaussian distribution for the first time on silicon. VAM
provides a method to accurately set design margin to achieve
best performance/power/area in low power memory design.
2011 Symposium on VLSI Technology Digest of Technical Papers
 References 15
�� 1
[1] M. Suzuki et al., VLSI Tech Symp., p. 191, 2010. � 20
����� � � ��
[2] Y. Li et al., IEEE Trans. on Semi. Manufacturing, p. 509, 2010.
10 28nm � � ���� � �� �
[3] T. Fischer et al., IEEE Int. Conf. on Microelectronics Test

CV/I (a.u.)
15

Iread (uA)
Structures, p.63, 2007. 45nm
[4] C.H. Hsiao & D.M. Kwai, IMW, p. 140, 2005. 10
5 -30C Non linear
[5] T.S. Doorn et al., ESSCIRC, p. 230, 2008.
[6] C. Chidambaram et al., IEDM, p. 608, 2010. 65nm 5

0 0
0 2 4 6 8 0.0 0.2 0.4 0.6 0.8 1.0
No. of Sigma Vdd (V)
Fig.1 CV/Iread vs. sigma under Fig.2 Iread vs.Vdd showing
Gaussian assumption at different linear relation only when
technology nodes. In 28nm CV/Iread
Vdd>>Vt.
approaches ∞ at ~7σ

-30C

Δσ=2.0
ΔVdd=50mV

Fig.3 The cumulative probability plot (CPP) of Iread distribution at

different Vdd. Δσ between each adjacent plot is a constant.
Fig.4 Temperature dependancy of Iread distribution. -30C shows lower
Iread than 25C.

Δσ2
Δσ1

ROM Iread
Distribution
Δσ remain the same for
the same Vt split.

Fig. 5 Iread distribution at 0.95V created from Iread distribution at

lower Vdd, showing significant deviation from Gaussion (dotted line) Fig.6 Iread distribution under varias Vt splits. Constant Vt shift results
at high sigma. Insert shows ROM Iread distribution is also in constant sigma shift. Center line is TT split.
non-Gaussian. 16 12
0.95V
-30C 10
0.95V 12
Si 8
-30C Overdesign
Iread (uA)

CV/I (ps)

0.95V 8 6
-30C
MC 4
Grey: VAM
simulation 4
Black: ISMC
2

Fig.7 MC simulation of Iread
distribution using VAM matches
well with that using ISMC.
0 0
0 2 4 6 8 10 12
Fig.8 Iread distribution from Si Sigma
matches closely with MC
simulation using VAM. Fig. 9 Iread & CV/I vs. sigma. Gaussian assumption (dotted line)
results in 2x CV/Iread penalty compared to VAM (solid line).

2011 Symposium on VLSI Technology Digest of Technical Papers 221

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