Si-Vision Academy Analog Labs Lab 05

Simple vs Low Compliance Cascode

Current Mirror
PART 1: Sizing Chart
3) Schematic to generate sizing charts for NMOS and PMOS devices is as follows:

with parameters set under Variables Table in SAE as follows:

VGS was arbitrarily set to 1 V just to conduct OP analysis to calculate V TH,N and VTH,P, to
serve in upper bound calculation for VGS during conducting DC sweep.

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5) Thus, VGS was DC swept from 0 to |-0.411770| + 0.4 ~ 0.82. V* and V_OV for both
NMOS and PMOS were expressed as highlighted in the following snippet from save.txt
file:

6) Below are curves for V*N and VOV,N, and V*P and VOV,P, all vs VGS overlaid:

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7) VGSQ,N and VOVQ,N for NMOS are determined to be 607 mV and 202 mV respectively at
sweetspot of V*N = 200 mV

while VGSQ,P and VOVQ,P for PMOS are determined to be 607 mV and 196 mV
respectively at sweetspot of V*P = 200 mV.

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8) Instead of plotting ID, gm and gds vs VGS, we will instead use V*N and V*P for x-axis,
yielding curves as follows:

We get the following:

NMOS PMOS
IDX (A) 47.1 µ 12 µ
gmX (S) 471 µ 120 µ
gdsX (S) 3.71 µ 931 n

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9) We obtain WN,Q and WP,Q (and gmN,Q, gmP,Q, gdsN,Q and gdsP,Q in point 10) through charts
obtained via highlighted expressions in save.txt file:

WN,Q and WP,Q are determined to be 4.25 µm and 16.6 µm respectively.

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10) Through curves generated by aforementioned expressions in save.txt file,

we see that gmN,Q = gmP,Q = 200 µS, gdsN,Q = 1.58 µS, gdsP,Q = 1.55 µS.

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Si-Vision Academy Analog Labs Lab 05

PART 2: Current Mirror

Testbench for the 2 current mirror types was conducted in following configuration:

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1) Below are schematics of wide-swing cascode and simple current mirrors with their DC
node voltages annotated, with IB,out node voltage clearly shown to be Vout = VDD/2 = 0.9
by schematic magnification

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2) There were failed attempts to export OP report as .csv file to lay out a table in document,
so a screenshot showcasing all necessary parameters of all transistors will suffice:

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3) All transistors have |VGS,Q| ≥ 607 mV as calculated in part 1. Reason for observed VGS
values as high 767 mV are due to body effect. Values for g m,Q are very close to 200 µS
calculated in part 1; the only expections being for PMOS device “M19” in simple current
mirror and for PMOS devices M19 and M20 in wide-swing cascode current mirror (due
to 2X WP). gds values are mostly higher than gdsN,Q = 1.58 µS, gdsP,Q = 1.55 µS; with most
striking cases being for PMOS “magic battery” device “M4” in wide-swing cascode
current mirror (due to 6X LP).
4) All transistors are indeed in saturation, as evidence by “2” flag under “region”.
5) Below are IB,out for simple and wide-swing current mirror vs Vout overlaid, highlighting
which current mirror arrangement is better at reproducing 2X Ibias:

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Si-Vision Academy Analog Labs Lab 05

We see that low compliance cascode arrangement in wide-swing cascode current mirror is
better at tracking IB,in than for simple current mirror, evidenced by Iout = 40 uA for Vout
range from 0 to ~ 1.42 V.
IB,out of simple current mirror is just able to perfectly track 2X I B,in at Vout ~ 1.2 V.
Incidently, this is when |VDS| across M19 ~ 0.609 V, which is meant to track |VGS| of M17.
|VGS| of M17 = 0.609483 V, as shown using operating point annotation.

6) % error of simple vs wide-swing current mirrors tracking 2X IB,in is shown by 2 overlaid

curves:

These were obtained through following expressions:

Wide-swing CM has error < 1% throughout most of Vout range, till we reach ~ 1.42 V; after
which error starts to increase (due to M19 getting into triode). Simple CM on the other hand
starts with > 9% error that decreases till it reaches its minimum at ~ 1.22 V (when |V DS|
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across M19 ~ 0.609 V). After that, M19 gets into triode, ruining current tracking and
increasing error once again.
7) Rout curves for both simple and wide-swing CM configurations vs Vout are overlaid as
follows:

We see that Rout definitely changes with Vout for both circuits. As Vout is increased, |VDS|
across PMOS transistors supplying IB,out is/are being ‘squeezed-out’, thereby driving
transistor from the deep end of saturation closer towards edge between saturation and triode.
Once |VDS| has been ‘squeezed-out’ enough to become lower than |VOV|, PMOS devices enter
triode and have their ro’s dropping significantly, hence Rout drops.
Needless to say, wide-swing CM has much higher Rout than simple CM due to cascode
boosting ro by gmro factor. However, its PMOS devices enter triode earlier, having its Rout
drop earlier than for simple CM. This is because of increased voltage headroom
consumption.
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8) Rout,simple CM = 𝑔 = 1/3.15945µ = 317 kOhm (3sf)
𝑑𝑠

1 1+(𝑔𝑚20 +𝑔𝑚𝑏20 )
Rout,wide-swing CM = 𝑔 ∗ = (1/3.18342µ)/(1+(0.39451+0.118213)m/14.2934µ)
𝑑𝑠20 𝑔𝑑𝑠19
= 11.6 MOhm (3sf)
Analytical Calculations Simulations
Rout,simple CM (Ohm) 317 k 317 k
Rout,wide-swing CM (Ohm) 11.6 M 11.7 M

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