Si-Vision Academy Analog Labs Lab 01

LPF Simulation and MOSFET

Characteristics
PART 1: Low Pass Filter Simulation (LPF)
1. Transient Analysis
1. For 1st order LPF to have τ = 1 ns, C must be 1 pF. Schematic is shown Fig. 1 below:

Fig. 1 LPF with input voltage as a clock

2. Square wave input was applied using “vpulse” cell, with pulse width, period, T rise and
Tfall parameterized as shown in Fig. 2 to have their values input in SAE.

Fig. 2 Parameterizing square wave properties through "Property Editor"

3. From SAE, parameters were “copied from design” and had their values plugged in
accordingly. “Vin” (red) and “Vout” (magenta) – as the wiring was labelled in cellview
– were then plotted across 2 periods for the transient analysis via “netlist and run”
option; as shown in Fig. 3:

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Fig. 3 LPF transient analysis

4. Tfall and Trise for Vout were calculated using Custom Compiler’s “Measure Tool”; using
“Rise/Fall Time” utility under “Time Domain”, having “H” and “L” margin thresholds
as 90 and 10 respectively, choosing “either” for trigger type. As annotated in Fig. 3, Tfall
= 2.18 ns, Trise = 2.2 ns. The discrepancy in that they do not equal each other arises from
simulation limitations of time step being 0.2 ns. A smaller, more “conservative” step size
should have yielded results converging on T fall = Trise.
5. Analytical calculation of Tfall and Trise is obtained from capacitor charging and
discharging equations:
𝑡
𝑉 (𝑡) = 1 − exp (− )
τ
To calculate Trise, we use above charging eqn. and plug in V(t) = 0.1, calculating t1, then
plug in V(t) = 0.9 and calculating t2; subtracting t1 from t2. We arrive at Trise ~ 2.20 ns
(3sf).
𝑡
𝑉 (𝑡) = exp⁡(− )
τ
Following suit with Tfall from above discharging eqn., we also get Tfall ~ 2.20 ns (3sf).
Trise (ns) Tfall (ns)
Simulated 2.2 2.18
Theoretical 2.20 2.20
6. To perform parametric sweep for resistance of “res” instance, its 1 kOhm value is
replaced with “R”, and from SAE, “R” was “copied from design”, to have “1k:1k:5k”
inserted for value.

Fig. 4 LPF transient analysis for parametric sweep across R

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Results in Fig. 4 show that as R is increased (from light mauve to yellow), τ increases and
charging capacitor takes longer. Yet, average of charging and discharging curves is always equal
to average of square wave value. So with Voltage1 = 0 and Voltage2 = 1 (DC components
passed by LPF), average is 0.5 V.

2. AC Analysis
1. To report Bode plot in AC analysis, have change our voltage source to not be a “vpulse”
instance: i.e., not a function of time. So instead, we replace it with a “vsource” instance,
ensuring pulse width, period, Trise and Tfall remain parameterized (when “pulse” is
chosen as source type) as copied from design in SAE. For AC analysis, in Property
Editor, we ensure source type is set to dc, and input “1” for “AC Magnitude”. We
disable transient analysis and retain R as 1 kOhm. We choose “ac” from “Create
analyses”, declaring sweep type as “decade”, having start at 1 Hz and stop at, say, 1
GHz (much higher than 1/(2π*1k*1p)), with “10” as an appropriate number of points.
Bode plots of magnitude and phase response are shown below:

Fig. 5a LPF magnitude response

Fig. 5b LPF phase response

Both plots show characteristic frequency response of LPF, with magnitude decreasing by 20
dB/dec once pole is reached and having a corresponding phase of -45°.

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2. DC gain of LPF is always 0 dB, and can be readily deduced by bode plot inspection. 3
dB BW can calculated from “Measure Tool” by accessing “Lowpass” utility under
“Frequency Domain”, choosing “Auto Detect” to automatically determine DC gain,
and then ensuring we have “-3” for offset. This gives us BW ~ 159 MHz as shown:

Fig. 6 3dB BW
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3. 3dB BW calculated analytically through formula: 𝐵𝑊 = 2𝜋τ
With τ = 1 ns we see simulation results matching our analytical calculation to 3sf.
3dB BW (MHz)
Simulated 159
Theoretical 159
4. In SAE, value for R is put as “1k,10k,100k,1000k”, hence resuming parametric sweep
nested in AC analysis. Bode plots for magnitude and phase response are shown
accordingly.

Fig. 7a LPF magnitude response with varying R

Fig. 7b LPF phase response with varying R

Once can see as R is swept from 1 kOhm (magenta) to 1000 kOhm (grey), pole occurs at earlier
frequencies, decreasing 3dB BW. So in magnitude response, one can see a higher magnitude at,
say, 1 GHz for LPF with R = 10 kOhm than for R = 100 kOhm. Similarly for phase response, -
45° happens earlier as pole occurs earlier as R is swept to increasing values; giving us higher
phase at, say, 10 MHz for LPF with R = 10 kOhm than for R = 100 kOhm. It is noted, however,
that all phases tend to -90° as frequency approaches infinity.

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3. [Optional] Pole Zero Analysis

Find out how Pole Zero analysis is done on Synopsys’ Custom Compiler or with HSPICE
commands

Part 2: MOSFET Characteristics

1. ID vs VGS

Fig. 8 DC sweeping VGS and -VGS for short and long channel NMOS and PMOS devices respectively

As shown in Fig. 8, this setup was used to sweep VGS at VDS = 1.8 V and register drain current;
mirroring operation for PMOS by taking the negative of every terminal voltage used for NMOS.
We arrive at IV characteristics for NMOS and PMOS in Fig. 9a and 9b respectively. The
absolute of IDS was taken when plotting IV characteristics for PMOS.

Fig. 9a Drain current for short channel (red) and long channel (magenta) NMOS devices

2. We observe a lower current at a given VGS for short channel (red) NMOS compared to
long channel (magenta). This is because with NMOS’ high µn, VDSsat is bound to occur

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much earlier than VOV, entering the device into velocity saturation, a region where
current no longer has quadratic dependence on VGS (and no dependence on L!), but rather
linear, as seen in Fig. 9a.

Fig. 9b Drain currents for short channel (green) and long channel (yellow) PMOS devices

In Fig. 9b however, we do not observe same trend. Due to PMOS’ lower µp, |VDSsat| is not
reached before |VOV|, hence the quadratic IV characteristic of pinch-off saturation for both
curves. Short channel (green) is bound to generate more current than long channel (yellow) due
to lower L, with current being inversely proportional to L, hence more readily affected by Early
effect.
3. We note that for either long or short channel scenarios, NMOS devices always give a
higher current for a given VGS than PMOS devices.
An attempt was made to find ratio between NMOS and PMOS currents through the
“Mixed-Signal Equation Builder”. Expression as follows was entered to be evaluated:
i(/MNS/D)/abs(i(/MPS/D))
Only to be met by following warning message.

Another attempt was made by entering i(/MNS/D)/abs(i(/MPS/D)) and

i(/MNL/D)/abs(i(/MPL/D)) for short and long devices respectively at “Outputs” at
“SAE”. Plots of short (magenta) and long (light mauve) PMOS/NMOS current ratios
aim to capture how µn/µp varies with VGS. In short channel devices, as VGS increases,
vertical electric field increases, making µn decrease faster than µp, hence explaining ‘dip’
in magenta curve, that is not present in light mauve curve.

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Fig. 9 Mobility ratios of short and long NMOS/PMOS devices

NMOS is much more affected by short-channel effects; due to its higher µn.

2. 𝑔𝑚 vs VGS
1. A “save.txt” file was created with contents as follows:

This allows for gm and ro (1/gds) calculation of short and long channel NMOS and PMOS
devices.

Fig. 10 gm of long (light mauve) and short (magenta) channel NMOS

2. In long light mauve channel NMOS, right after VGS passes VTH ~ 0.4 V we see gm as a
linear function of VGS (except at higher voltages > 1.4 V, where mobility degradation
takes place). This is because gm is the derivative of ID with respect to VGS. Derivative of a
quadratic relation yields a linear one. In short magenta channel NMOS, gm is linear for a

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brief range of VGS after VTH, after which it saturates. This is because device entered
velocity saturation, and now ID is linearly dependent on VGS.

3. ID vs VDS
1. I was unable to run the nest DC sweep for VDS = 0:10m:VDD and VGS = 0:0.2:VDD. So
instead, DC swept VDS (as it has the finer step), while conducting parametric analysis for
VGS. Results for short and long channel NMOS are shown below.

Fig. 11a ID vs VDS curves for different VGS values for short channel NMOS

Fig. 11b ID vs VDS curves for different VGS values for long channel NMOS

2. As to be expected, for a given VGS, long channel devices deliver more current in saturation
region. We note that in saturation region, long channel device’s current seemingly
plateaus, while in short channel device, it still exhibits a slope, i.e. it is a weak function of
VDS. This is because of the Early effect: λ ∝ 1/L. The shorter L is, the higher λ, the less
VA gets, the more pronounced the Early effect appears, making I D a weak function of VDS
and thus exhibiting a slight slope even in saturation.

4. [Optional] 𝑔𝑚 and 𝑟𝑜 in Triode and Saturation

1. To obtain VTH, an attempt at OP analysis was made, choosing “Voltage” for format.
From schematic view > Utilities > Annotate Operating Point > it was discovered that an
“OP file” is needed, making one doubt whether this is a viable course of action to
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determine VTH. So, the “poor man’s” method of resorting to I D vs. VTH curve was enlisted
to estimate VTH. One tried to find derivate of curve, arguing that as soon as g m is not 0,
VTH has been exceeded and can be determined easily. To do this, one tried to “Add
Monitor”, choosing it to be derivative; to no success: couldn’t figure out how it worked.
So, I resorted to estimating VTH from ID vs. VTH curve by “handwaving” that is ~ 441
mV, yielding ID ~ 2.68 µA (gm ~57.2 µS in derivative monitor).

Fig. 12 gm vs VDS for long channel NMOS

2. gm is initially linear with VDS. ID’s equation in triode region is as follows:

𝑊 𝑉𝐷𝑆 2
𝐼𝐷 = µ𝑛 𝐶𝑜𝑥 ((𝑉𝐺𝑆 − 𝑉𝑇𝐻 )𝑉𝐷𝑆 − )
𝐿 2
Differentiating with respect to VGS shows that gm is linearly dependent on VDS.
gm is (nominally) meant to saturate in saturation region due to equation ID’s equation in
saturation region having no VDS term (neglecting channel length modulation). In analog
design; we want to operate in saturation region to obtain constant gm, hence constant
gain.
3. Following curve captures ro change with VDS:

Fig. 123 Long channel NMOS ro change with VDS

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Well into saturation region, ro does not appear to entirely saturate. I.e. It has a dependency on
VDS. ro = ΔVDS/ΔIDS, and hence is equal to 1/slope of ID/VDS curve. So long as there exists
(decreasing) slope as VDS increases in ID/VDS curve, ro will continue increasing slightly.
Obviously, one needs to bias well into saturation region (high V DS) to sustain large ro for
increased intrinsic gain (g mro) in analog design. Biasing at edge of saturation results in low r o, not
suited for large gains required in analog design, and can make ro susceptible to decrease further if
voltage variations happen to decrease VDS.

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