Question Bank:

Module 1 and Module 2

1. Explain NAND as Universal GATE (i.e. as NOT, AND, OR , NOR, XOR

and XNOR GATE)
2. Explain NOR as Universal GATE (i.e. as NOT, AND, OR , NAND, XOR
and XNOR GATE)
3. (a) Minimize the following boolean function using K-map -
(a) F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
(b) F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 6, 15)
(c) F(x,y,z) = xy + x’yz + xyz + xy’z’
(d) F(A,B,C,D) = A’B’C’ + B’CD’ + A’BCD’ + AB’C’
4. Describe 8X3 encoder with proper truth table, block diagram and circuit
diagram.
5. Describe 3X8 decoder with proper truth table, block diagram and circuit
diagram.
6. Describe 4X2 priority encoder with required truth table and circuit diagram.
7. Explain 1:8 MUX with proper truth table, block diagram and circuit
diagram.
8. Explain 8:1 DEMUX with proper truth table, block diagram and circuit
diagram.
9. Design a 4:1 MUX using a minimum number of 2:1 MUX with proper
explanation.
10. Design (a) Full adder and (b) Full Subtractor by providing all the required
details.
11. Design Adder-Subtractor using select line by providing all the required
details.
12. Convert (110001101010)2 to grey code.
13. Convert (110001101010)2 to binary.
14. Design a 2 bit Magnitude Comparator using truth table and K-map.
15. Design a 3 bit Magnitude Comparator using logical method only.
16. Define Fan-in, Fan-out and Gate Delay with proper example.
17. Explain Hazarads in combinational circuits.

Module 3

18. What do you mean by mono-stable and bi-stable elements.

19. Explain construction and working of uncontrolled (a) SR Latch and (b) D
Latch using NAND GATE with proper Truth Table and Characteristic Table.
20. Explain construction and working of uncontrolled (a) SR Latch and (b) D
Latch using NOR GATE with proper Truth Table and Characteristic Table.
 21. Explain construction and working of controlled (a) SR Latch and (b) D
Latch using NAND GATE with proper Truth Table and Characteristic Table.
22. Explain construction and working of controlled (a) SR Latch and (b) D
Latch using NOR GATE with proper Truth Table and Characteristic Table.
23. Explain construction and working of (a) SR Flip Flop and (b) D Flip Flop
using NAND GATE with proper Truth Table and Characteristic Table.
24. Explain construction and working of (a) SR Flip Flop and (b) D Flip Flop
using NOR GATE with proper Truth Table and Characteristic Table.
25. Explain register in brief with schematic diagram for SISO, SIPO, PISO and
PIPO type register.
26. Explain working of 3 bit (a) up and (b) down synchronous counter.
27. Explain working of 3 bit up-down synchronous counter.
28. Describe working of 3 bit (a) up and (b) down asynchrounous counter .
29. Describe working of 3 bit up-down asynchrounous counter.

MODULE – 4
30. List the different types of memories and explain with diagram and example.

31. Compare RAM and ROM.

32. Design a combinational circuit using (a) ROM (b) PAL and (c) PLA that accept a
3-bit number and outputs a binary number equal to the square of the input number.

33. Implement the following Boolean expression using PROM, PAL and PLA
F1(a, b, c, d)= ∑m(1, 2, 4, 5, 6, 8, 10, 12, 14)
F2(a, b, c, d) =∑ m(2, 4, 6, 8, 10, 11, 12, 14, 15)

34. Implement the following Boolean expression using PROM, PAL and PLA
F1(A,B,C,D) = ABC + ABD’
F2(A,B,C,D) = A’B’C’ + A’BCD’ + AB’C’

35. Implement the following Boolean expression using PROM, PAL and PLA
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 6, 15)
MODULE -5
36. Explain, in detail, concept of Moore state machine with required block diagram
and example.

37. Explain, in detail, concept of Mealy state machine with required block diagram
and example.

38. Design Mealy state machine using D flip flop for given state diagram
39. Design Moore state machine using D flip flop for given state diagram

40. Design state diagram for (a) SR flip flop and (b) D flip flop.

41. Design state diagram and state machine using D-flip flop for given state table.

42. Deduce state diagram and state machine using D-flip flop for given state table.