PRIYADARSHINI COLLEGE OF ENGINEERING, NAGPUR

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Question Bank:
UNIT-I
1.State and prove Demorgans Ist & 2nd Theorem
2. Why NAND & NOR Gate is called as Universal Gate
3. a. Explain standard SOP and standard POS forms of Boolean equation. Also explain Min
terms and Max terms concept
b. Convert the following expression into standard SOP form and find out minterms &
maxterms i) f (A, B, C,D) = A+B'C'+ABD'+ABC
ii) f (A, B, C,D) = AB+AC'+C+AD
4. Convert the following expression into standard POS form
f (A, B, C) = A'B+BC+AC'.
5. Implement the following function using K-map Simplification 7
i) f (W,X,Y,Z) = Ʃm(0, 2, 3, 5, 7, 11, 12,15)+d(4,6,13)
ii) f (P,Q,R,S) =ΠM(1, 3, 4, 6, 7, 9, 10,13,15)+d(8, 12)
iii) ) f (A,B,C,D) = Ʃm(0,1,4,5,9,11,14,15)+d(10,13)
iv) f (A,B,C,D) = Ʃm(2,5,6,9,10,12,13,14)+d(3,7,11,15)
v) f (A,B,C,D)= ΠM(0,1,3,4,5,7,9,10,11,13,14,15)
UNIT-II
1. ) Design full adder using two half adders and OR-gate and explain it.
2.Design a Full adder & Full substractor and draw a truth table
3. Design a Full adder ckt and Implement using NAND gates only
4. Design a magnitude comparator to compare the magnitude of two, 2 bit binary numbers
and draw the logic diagram
5. i)Design a 4 bit binary to Gray code converter and implement using Ex-OR gates only
ii) Design a 3 bit binary to Gray code converter and implement using Ex-OR gates only
iii) Design a 3 bit Gray to binary code converter and implement using Ex-NOR gates only
iv) Design a 4 bit Gray to binary code converter and implement using Ex-OR gates only
v) Design a 3 bit odd parity & Even generator and implement with NAND gates
vi) Design a logic ckt using NAND gates which accepts 2-bit Input numbes A=A1A0 and
B=B1B0 and gives a 4-bit output P=P3P2P1P0 which is a product of A&B.
6.Explain EVEN and Odd parity Checker

UNIT-III
1. ) Implement the following function using 8: 1 multiplexer.
F = Ʃm (0, 1, 2, 3, 11, 12, 14, 15).
2. Implement the following function using 8: 1 multiplexer F(A,B,C,D) = Ʃm
(0,2,3,6,7,11,13,14,15) Connect A,B and C to control lines.
3. . Implement the following function using 8: 1 multiplexer
F(A,B,C,D)= A'BD'+ACD+B'CD+A'C'D
4.Implement a full adder using 4:1 MUX
5 Implement a full adder using only one 4:1 MUX and NAND Gates
6)Implement 16:1 multiplexer using 4: 1 multiplexers.
7) Implement 32:1 multiplexer using 16:1 mux and 4: 1 multiplexers
8)Design a 32 : 1 MUX using 2 : 1 MUX
9. Implement 16:1 multiplexer using 2: 1 multiplexers
10) Design 1:32 demultiplexer using 1:8 demultiplexers
11) Design 1:16 demultiplexer using 1:4 demultiplexers
12) Implement the following using 3:8 decoder circuit.
f1 (ABC)= Ʃm(4,5,6,7)
f 2(A,B,C)= Ʃ m (0,1,2,4)

13.Design or relize 3:8 decoder using logic gates

14. What is the difference between encoder & decoder? Explain priority encoder
15.Design a BCD to 7 segment decoder circuit.
16.Design 8:3 Encoder ckt
17.Explain Priority Encoder
18.

19.

UNIT-IV:
1.Explain SR,and JK, master JK flip flop .
2.Convert 1) SR to JK ii) JK to SR iii) SR to D iv) T to D
v)T to SR vi) T to JK vii)JK to T viii) D flip flop to T flip flop
3.Explain Race around condition

UNIT-V:
1.Explain SISO ,SIPO and PISO shift register
2.Explain Ring , Twisted Ring and ripple Counter
3.Design MOD -5 and MOD-8 synchronous counter using suitable flip flop
4.Design a Lock free sysnchronous counter which goes to the following states
4 6 7 3 1 4

5.Design a lock free synchronous counter using D flip flop that goes through following states:.
7--4--6—0--5—7
6. Difference between Synchronous and asynchronous counter.
7.design 3 bit up down counter
UNIT-VI
1.Draw and explain block diagram of ATMEGA328P

2.Explain the different flag register of ATMEGA328P

3.Explain the general purpose registers of ATMEGA328P

4.Draw and Explain the pin diagram of ATMEGA328P

5. Explain addressing modes of ATMEGA328P