Si-Vision Academy Analog Labs Lab 02

Common Source Amplifier

PART 1: Sizing Chart
1. CS amplifier configuration (without load just yet) to characterize VGS vs V* is as follows
on schematic editor:

PMOS device is present to generate its sizing chart to serve in action item 4 (Gain
linearization) of part 2.
It is noted that for ee214b_hspice.sp, we are required to have VDS = 1.8 V, and
subsequently gain = -8 V/V.
2. L and W are parameterized as being L µm and W µm long respectively. From SAE, they
are copied as variable for design, and set at 2 µm and 10 µm respectively. L being 2 µm
long, makes it a relatively long device to minimize ro’s effect on equivalent Rout.
𝑉𝑅𝐷 0.9
4. 𝑅𝐷 ~ ~ ~9 𝑘𝑂ℎ𝑚𝑠
𝐼𝐷 100µ
2∗𝑉𝑅𝐷 2(0.9)
5. 𝑉𝑄∗ = |𝐴𝑉 |
= = 0.225
8
8. Creating a .txt file with following hspice commands:
.probe dc gm = gmo(M0)
.probe dc id = id(M0)
.probe dc vth = vth(M0)
.probe dc vstar = ‘2*id/gm’
.probe dc vgs = vgs(M0)
.probe dc vov = ‘vgs-vth’
we can plot VGS vs V* and VOV overlaid as shown in figure below:

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Si-Vision Academy Analog Labs Lab 02

9.

10. Setting Y-value for horizontal cursor at 225 mV, we pinpoint VGSQ = 618 mV. Setting X-
value for vertical cursor at 618 mV, we pinpoint VOVQ = 235 mV.
11.

IDX 29.4 µA
gmX 261 µS
gdsX 1.46 µS
12.
W ID
10 µm 29.4 µA
34 µm 100 µA

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Si-Vision Academy Analog Labs Lab 02

W gm 13.
10 µm 261 µS
34 µm 887.4 µA

W gds
10 µm 1.46 µS
34 µm 4.964 µA
1
𝐴𝑉 = −𝑔𝑚 (𝑅𝐷 ||𝑟𝑜 ) = 887.4µ ∗ (9k| | ) = −7.65 (3𝑠𝑓)
4.964µ
Interestingly, this does not meet the required spec of -8. We either need to increase gm or
RD. Increasing RD, it will need to be 9.44 kOhm to just barely meet the gain spec. We
reflect on this RD value in part 2.

PART 2: CS Amplifier
1. OP and AC Analysis
1. CS amplifier in schematic view is as shown below

With VGSQ, RD, L and W as follows:

2. Key operating points are printed out after an OP analysis, as shown below:

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Si-Vision Academy Analog Labs Lab 02

Chart Design-Based Value Simulator Value

VGSQ 618 mV 618 mV
VOVQ 235 mV 234.44 mV
IDQ 100 µA 100.137 µA
gmQ 887.4 µA 889.224 µS
gdsQ 4.964 µA 5.01078 µS
We consider simulator values mostly agreeing with chart design-based values obtained through
cross-multiplication, given that ID, gm and gds and directly proportional to W. Any discrepancies
could be due to 10 mV step size in VGS sweep, and owing to the fact that we intentionally
increased RD to meet gain spec.

3. 𝑟𝑜 = 1⁄𝑔𝑑𝑠𝑄 ~ 200 𝑘𝑂ℎ𝑚 (3𝑠𝑓). This is much higher than 𝑅𝐷 = 9.44 𝑘𝑂ℎ𝑚. Hence, we
are justified to neglect ro from Av calculation. However, for min L, ro could become
comparable to RD, requiring its inclusion as parallel to RD in Rout calculation.
889.224
4. |𝑔𝑚 𝑟𝑜 | = 5.01078 ~177 (3𝑠𝑓). We thus see it is much larger than amplifier gain
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5. |𝑔𝑚 (𝑟𝑜 ||𝑅𝐷 )| = 889.224µ ∗ ( ||9.44𝑘)~ 8.02 (3𝑠𝑓). |Av| << |gmro|.
5.01078µ
6. An AC analysis was run from 1 Hz to 1 GHz with a linear scale in mind instead of db20.

DC gain is shown to be 8.02, agreeing with our analytical calculation, and more importantly,
meeting spec of DC gain >= 8.

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Si-Vision Academy Analog Labs Lab 02

2. Gain Non-linearity
1. Vout mapped with DC swept Vin is as follows:

2. Relation is highly nonlinear, except for brief Vin range. This is because from 0 < Vin
< VTH, M0 is OFF (in subthreshold, really) and barely any current passes through,
making Vout ~ VDD. For the region slightly before Vin > VDD/2 onwards, M0 is at
edge of saturation, entering triode where gm drops, hence gain drops, hence
nonlinearity.
3. Av = - gmRD, where gm = f(Vin), hence inherent nonlinearity!

5. Result cannot be showcased due to VNC connectivity and lag issues. But gm varies
with Vin (itself a sinusoidal, amplitude varying in time). This means that small signal
gain itself varies with time.
6. Amplifier is definitely not linear, as seen by Vin-Vout large signal VTC, small signal
gain variations with swept Vin, and gm variations with time. This is all enabled by the
fact that gm = f(Vin).