Microelectronics Journal 114 (2021) 105141

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Nanosheet field effect transistors-A next generation device to keep Moore’s

law alive: An intensive study
J. Ajayan a , D. Nirmal b, ∗ , Shubham Tayal a , Sandip Bhattacharya a , L. Arivazhagan c ,
A.S. Augustine Fletcher b , P. Murugapandiyan d , D. Ajitha e
a
SR University, Warangal, Telangana, India
b
Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d
Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

A R T I C L E I N F O A B S T R A C T

Keywords: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire
FinFET (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which lim-
Gate-all-around (GAA)
its their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance
Nanosheet (NS)
up to a feature size of 7 nm. The research community is expecting that GAA NW-FETs will take over FinFET
RC Delay
Sub-7-nm node
technology from 7 nm to 5 nm. However, further shrinking of feature size to 3 nm will impose severe challenges
TreeFET to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community
Work function (WF) needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the
FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability
to scale down even below a feature size of 5 nm with negligible short channel effects. Therefore, in this review
article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate mate-
rial effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain
(S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promis-
ing solution for future digital/analog integrated circuit applications due to their outstanding capability to keep
Moore’s Law alive.

1. Introduction
Modern processors embedded with billions of transistors are one
of the most complex systems in the world. To fulfill the fast-changing
consumer demands for tiny and high-performance gadgets, the tran-
sistor density in processors along with their performance needs to be
enhanced. In other words, Moore’s law needs to be kept alive, that
is, downscaling of transistors must be continued. The semiconductors
giants like Intel, Samsung, and TSMC have already succeeded in devel-
oping ICs with 7 nm technology node and working towards 5 nm tech-
nology node. FinFET technology was a breakthrough in achieving a
7 nm technology node [1–3]. However, at future lower technology
nodes such as 5 (or 3) nm, FinFET technology will face some critical
challenges like self-heating effects, severe short channel effects, transis-
tor performance, patterning, cost, and layout, etc. Another limitation
with FinFET technology is that its gate covers only the three sides of
the rectangular Fin due to which the bottom side of the Fin comes in
contact with the substrate. This results in a high leakage current even
the transistor is in off-state. To overcome this limitation, the gate-all-
around (GAA) FETs were investigated by the semiconductor industry
[4–6].
The better electrostatic channel control and reduced SCEs even for
sub-7 nm technology node made GAA nanowire (NW) FETs one of the
most promising solutions for future devices. However, the low drive
current in GAA NW-FETs caused by the lower ratio of effective chan-
nel width (Weff ) to layout foot print (LFP), i.e. Weff /LFP, limits their
switching performance. To get rid of this problem, NWs can be stacked
in a vertical manner. Further, these vertically stacked NWs result in
large parasitic capacitance of the device which is another severe chal-
lenge. The nanosheet (NS) transistors are the best solution to overcome

∗ Corresponding author.
E-mail addresses: j.ajayan@sru.edu.in (J. Ajayan), dnirmalphd@gmail.com (D. Nirmal).

https://doi.org/10.1016/j.mejo.2021.105141
Received 21 March 2021; Received in revised form 2 June 2021; Accepted 2 June 2021
Available online 16 June 2021
0026-2692/© 2021 Elsevier Ltd. All rights reserved.
J. Ajayan et al.
Fig. 1. 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NS-
FET.
these challenges because of their higher Weff /LFP and lower parasitic
capacitances as compared to FinFET and GAA NW-FETs which in turn
will provide high drive current [7–9]. The computing world always
aligns towards the advancement of transistors for better performance.
The compatibility of NS-FETs with different materials like Ge, InGaAs,
InAs, InSb, SiGe, and GeSn, etc. makes it suitable for high computing
needs. Consequently, there is no doubt that these NS FETs will lead the
semiconductor device industry in the years to come.
2. Impact of nanosheet width/thickness scaling
The concept of GAA NS-FET is first introduced by IBM research
group in 2015 [1]. In 2017, IBM research group experimentally demon-
strated the first ever horizontally stacked GAA NS-FET which is consid-
ered as a serious contender to replace FinFET technology at the 5-nm
node and beyond [2]. Large Weff /LFP ratio is the major advantage of
GAA NS-FETs. The first ever fabricated horizontally stacked GAA NS-
FET had a gate length (LG ) of 12 nm and contacted poly pitch (CPP)
of 44/48 nm [2]. The 3-D view of FinFET, NW-FET and NS-FETs are
shown in Fig. 1. In FinFET, three sides of the Fins are covered by
the gate (Fig. 1 (a)). Therefore, at lower technology nodes, the elec-
trostatic control is not as good as NW-FETs and NS-FETs. The aggres-
sive miniaturization of FinFET leads to the reduction of contact area,
fin depopulation and increase of sub-Fin leakage current which causes
the severe degradation of its DC/RF performance. In Fig. 1 (b), the
nanowires are stacked horizontally and vertically to improve the drive
current of GAA NW-FETs. The limited effective width of the channel
(nanowire) is the only disadvantage of NW-FETs. In NS-FETs, width of
the nanosheet (WNS ) is not limited by Fin quantization and Fin pitch,
therefore, the device designers will get maximum freedom to increase
WNS to achieve higher drive current [3]. Beyond 7-nm technology node,
quantum mechanical effects comes into picture. Therefore, ballistic cur-
rent in FinFET, GAA NW-FET and GAA NS-FET usually decreases with
reduction in channel width. The ballistic current (Iballistic ) can be com-
puted as [4].
Iballistic = q.Ninv .vinj (1)
where q, Ninv and vinj represent electron charge, inversion charge den-
sity and injection velocity respectively.
D. Jang et al. [3] reported that the vinj in p-type SiGe NS-FET can be
enhanced significantly by reducing the WNS , however, vinj in n-type Si-
NS-FET does not depend on WNS . Channel strain also enhances the vinj
in NS-FETs. A lower nanosheet thickness is required to achieve low SS
and DIBL in NS-FETs because reducing the nanosheet thickness helps to
improve the gate control over the nanosheets. In 2018, Chun-Lin Chu et
al. [5] experimentally demonstrated the first ever horizontally stacked
p-channel and n-channel type Ge based GAA NS-FETs. The major bene-
fit of using Ge as a channel material is that it has higher charge mobil-
ity compared with Si and SiGe materials. LPCVD (low pressure chem-
ical vapour deposition) process was used to fabricate the horizontally
stacked Ge-GAA NS-FET. Sooner, Yu-Shiang Huang et al. [6] reported
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Microelectronics Journal 114 (2021) 105141
the experimental demonstration of first ever vertically stacked p-type
GeSn GAA NS-FET using CVD process. GeSn has a higher hole mobility
than Ge, therefore, GeSn have recently emerged as a channel material
for p-type GAA NS-FETs. The introduction of Sn into Ge helps to reduce
the effective mass of holes which in turn leads to the improvement of
hole mobility. At 7-nm technology node NS-FETs exhibits relatively low
RC delay and higher ION (ON current) compared with FinFETs [7]. RC
delay (intrinsic delay) can be computed as [8].
RC = Cgg .Vdd ∕ION (2)
where Cgg and VDD represents gate capacitance and operating voltage
respectively. This indicates that at sub-7 nm technology node, NS-FET
outperforms FinFETs and exhibit outstanding potential to aggressively
scaling down as well as performance improvement compared with Fin-
FETs for future analog/digital integrated circuit applications [9–14].
The process of release of channel by selective sacrificial layer etch-
ing is the key difference in fabrication of vertically stacked NS-FET
compared to FinFET. Sacrificial layer is nothing but the layer inserted
between the nanosheets in the vertically stacked NS-FETs. Usually SiGe
is used as the sacrificial layer in Si-NS-FETs. Techniques such as chem-
ical dry etching [11] and vapour HCl [12] are widely used for SiGe
etching process and these techniques have a limited selectivity to sil-
icon and there is a possibility of unintentional etching of nanosheet
channels that may results in the variation in nanosheet channel thick-
ness. It will also create an issue of different WNS in vertically stacked
NS-FETs with in a single substrate. In 2020, Sihyun Kim et al. [13]
investigated the impact of WNS on the electrical behaviour of stacked
lateral Si-NS-FET with 3 stacked nanosheets and found that a low WNS
is required for achieving high electron density in the channels (Fig. 2
(a)), lower threshold voltage and higher ION (Fig. 2 (b)). Stacked lateral
NS-FETs with lower WNS exhibits reduced SS due to better gate con-
trol. Sihyun Kim et al. also observed that a higher WNS results in the
increase of threshold voltage and SS due to poor gate controllability.
When WNS was scaled down from 75 nm to 25 nm, CGS (gate-source
parasitic capacitance) was found to be increased by 8.31% [13]. WNS
also affects the Dit (interface trap density) in stacked lateral NS-FETs
due to the induction of Ge diffusion into the Si-nanosheets during the
thermal processes carried out before the process of releasing the chan-
nel. Dit of narrow channel NS-FET is found to be smaller than that of
wide channel devices [13]. The impact of WNS on the SS and DIBL of
stacked lateral NS-FETs are illustrated in Fig. 2 (c) and Fig. 2 (d) respec-
tively. As the WNS of stacked lateral NS-FET increases, its gate control
over the nanosheets decreases and therefore SS and DIBL also increases
[14]. In shorter gate length devices the impact will be more.
Shuo Zhang et al. [15] demonstrated the performance of p-type sin-
gle nanosheet and vertically stacked horizontal NS-FETs (Fig. 3) with
Si and Ge channels. Shuo Zhang et al. has have investigated the impact
of channel crystal orientations and channel width (Wch ) on the electri-
cal characteristics of p-type vertically stacked horizontal NS-FET with
Si and Ge channels and observed that p-type NS-FET with vertically
stacked horizontal nanosheets exhibits higher ION compared with sin-
gle NS-FET for both Ge and Si channels. Crystal orientation of Si and Ge
channels also plays a key role in determining ION of the devices (Fig. 4
(a) & (b)). In p-type vertically stacked horizontal Si-NS-FET, [111] crys-
tal oriented channel exhibited higher ION than [110] and [100] crystal
oriented Si- channels. On the other hand, for p-type vertically stacked
horizontal Ge-NS-FET, [100] crystal oriented channel provided highest
ION than [111] and [110] crystal oriented Ge channels. Increase in Wch
results in the decrease of ION and increase of SS and DIBL in p-type
NS-FETs with both Si and Ge channels. In both Si and Ge channel based
p-type NS-FETs, a [100] crystal oriented channel provided lowest SS
compared with [110] and [111] crystal oriented channels (Fig. 4 (c) &
(d)). When Wch increases, source to drain tunnelling rate also increases
due to the poor gate control of the nanosheets. Therefore, with increase
in Wch in p-type Si and Ge channel based NS-FETs, IOFF and SS also
increases.
J. Ajayan et al.
Fig. 2. Impact of WNS on (a) electron density in the channel [13] (b) transfer curves [13] (c) subthreshold swing (SS) [14] and (d) DIBL of Lateral NS-FETs [14].
Fig. 3. (a) NS-FET with single nanosheet (b) NS-FET with vertically stacked horizontal nanosheets [15].
The impact of nanosheet thickness (NSH_TH) and nanosheet width
(NSH_W) on the ION of vertically stacked NS-FET is illustrated in Fig. 5
(a). A wider and thinner nanosheet is required to achieve higher ION .
IOFF can also be reduced by using thin nanosheet channels. As NSH_TH
increases, the potential barrier height in the conduction band energy of
the channel decreases which results in the increase of IOFF . DIBL of ver-
tically stacked NS-FET is also a strong dependent of both NSH_W and
NSH_TH and it is found that DIBL increases with increase in NSH_W as
well as NSH_TH (Fig. 5 (b)). Therefore, thinner and wider nanosheet
channels are essential for enhancing the ION /IOFF ratio of vertically
stacked GAA NS-FETs (Fig. 6 (a)). fT and fmax of vertically stacked
GAA NS-FET are also found to be increasing with respect to increase
in NAS_W (Fig. 6 (b) & (c) respectively). However, a thicker nanosheet
is required to improve both fmax and fT . This is due to the fact that the
Cgs /Cgd ratio decreases with increase in NSH_TH (Fig. 6 (d)). A large
NSH_TH also results in the increase of drain conductance and decrease
of maximum intrinsic gain [16].
3. Impact of substrate materials
In 2019, V. Jegadheesan et al. [16] investigated the impact of SOI
(silicon on insulator), SSR-Si (Super steep retrograde-Si) and PTS-Si
(Punch-through stopper-Si) substrates on the RF/analog performance
of vertically stacked NS-FETs and observed that the wafer material has
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Microelectronics Journal 114 (2021) 105141
a significant impact on the electrical characteristics of NS-FETs because
the substrate material can affect the carrier mobility in the channel. NS-
FET with SOI wafer exhibited higher electron mobility in the nanosheet
channel due to elimination of dopants intrusion from the wafer. On
the other hand, NS-FET with PTS-Si substrate provides lowest electron
mobility in the nanosheet channel due to dopant diffusion into the chan-
nel from the wafer during the annealing treatments. The diffusion of
dopants from PTS-Si substrate to the Si-nanosheet channel enhances
the Coulomb scattering effects which degrade the electron mobility in
the nanosheet. Therefore, NS-FETs with SOI and SSR-Si substrates pro-
vide higher transconductance (Fig. 7 (a)) and drain current compared
with PTS-Si substrate. Due to the absence of parasitic channel for lower
NSH_W in vertically stacked GAA NS-FETs with SOI and PTS-Si sub-
strates, IOFF will be minimum in these devices compared with SSR-Si
substrate based NS-FETs. For wider NSH_W, NS-FETs with SOI wafer
exhibits higher gds (drain conductance) (Fig. 7 (b)) due to the lowering
of energy barrier in parasitic channel.
4. Impact of parasitic nanosheet channel height
Parasitic nanosheet channel is nothing but the nanosheet channel
which is placed below the vertically stacked nanosheet channels in NS-
FETs. The height of the parasitic nanosheet channel (Hch ) significantly
affects the DC characteristics of the vertically stacked GAA NS-FETs. In
J. Ajayan et al.
Fig. 4. (a) Impact of Wch on ION of Si-NS-FET (b) impact of Wch on ION of Ge-NS-FET (c) impact of Wch on SS of Si-NS-FET (d) impact of Wch on SS of Ge-NS-FET
[15].
Fig. 5. Impact of NSH_W and NSH_TH on the (a) ION and (b) DIBL of NS-FETs [16].
2020, Yunho Choi et al. [17] investigated the impact of Hch on the DC
performance of vertically stacked GAA NS-FET and observed that SS,
DIBL and ION /IOFF ratio improves with increase in Hch . The impact of
Hch on the transfer curves of vertically stacked GAA NS-FET is illus-
trated in Fig. 8 (a). The impact of Hch and ground plane doping con-
centration on the SS, DIBL and ION /IOFF ratio of the vertically stacked
GAA NS-FET is depicted in Fig. 8 (b)–(d) respectively. The use of ground
plane doping helps to minimize the effect of parasitic nanosheet channel
in vertically stacked GAA NS-FETs. The ground plane doping can effec-
tively minimize the punch through and it can also increase the thresh-
old voltage of the parasitic nanosheet channel. Gate capacitance and
RC delay of vertically stacked GAA NS-FET also increases with increase
in Hch . SS and DIBL of vertically stacked GAA NS-FET can be reduced
effectively by increasing Hch and ground plane doping concentration. A
large Hch and high ground plane doping also results in the enhancement
of ION /IOFF ratio.
5. Impact of gate length scaling
Self heating effect is a serious concern in multi-gate transistors since
it limit the reliability and performance with aggressive down scaling of
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Microelectronics Journal 114 (2021) 105141
their gate lengths [18–21]. Aggressive scaling down of LG in NS-FETs
severely degrade the SCEs. The electron velocity as a function of trans-
port direction for NS-FET, NW-FET and FinFET are plotted in Fig. 9
(a). GAA NS-FET exhibits highest electron velocity under the gate com-
pared to NW-FET and FinFET and this may be due to their outstanding
sub-band occupation and better gate control over the nanosheet chan-
nel. The impact of LG down scaling and S/D doping density (NS/D ) on
the SS, VT and ION /IOFF ratio of FinFET, NW-FET and NS-FET are illus-
trated in Fig. 9 (b)–(d) respectively. SS of all the three devices severely
degrades with aggressive downscaling of LG . Among the three devices,
NW-FET exhibits least SS. SS is also found to be degrading severely with
increase in NS/D . Moreover, a higher NS/D leads to the reduction in VT
and ION /IOFF ratio of the devices. GAA NS-FET exhibits better ION /IOFF
ratio compared with NW-FET and FinFET for the same device feature
sizes. Aggressive scaling down of LG leads to the reduction of VT which
in turn increases the IOFF and degrades the ION /IOFF ratio of NS-FETs.
GAA NS-FET offers higher drive current compared to GAA NW-FETs
and FinFETs due to their large effective WNS per layout footprint and
reduced parasitic capacitances. The large effective WNS of GAA NS-FETs
help to improve the volume inversion under ON state conditions that
also results in the improvement of ION . In 2019, Meng-Ju Tsai et al.
J. Ajayan et al.
Fig. 6. Impact of NSH_TH and NSH_W on the (a) ION /IOFF ratio (b) cut off frequency (fT ) (c) maximum oscillation frequency (fmax ) and (d) Cgs /Cgd ratio of vertically
stacked GAA NS-FET [16].
Fig. 7. Impact of SOI, SSR-Si and PTS-Si substrates on the (a) transconductance (gm ) and (b) drain conductance (gds ) of vertically stacked GAA NS-FET [16].
[23] experimentally demonstrated the impact of tri-gate, omega-gate
and GAA structures on the scalability of NS-FETs and observed that NS-
FET with GAA structure is preferable for achieving reduced SCEs. That
is, NS-FET with GAA structure exhibits extremely low SS (Fig. 10 (a))
and DIBL (Fig. 10 (b)) compared to NS-FET with tri-gate and omega-
gate structures. This extremely low SS and DIBL of GAA NS-FET indi-
cates their outstanding scalability compared to NS-FET with tri-gate and
omega-gate structures.
6. Impact of temperature
Temperature is a key parameter in the design of NS-FETs because
it can significantly affect its AC/DC performance. In 2019, Po-Hsiang
Liao et al. [24] experimentally demonstrated the impact of tempera-
ture on the ON/OFF state performance of n-type Si0.15 Ge0.85 NS-FET.
Po-Hsiang Liao et al. observed that when temperature is varied from
300 K to 80 K, the ION /IOFF ratio of n-type Si0.15 Ge0.85 NS-FET is found
to be increasing from 5 × 107 to 5 × 108 at VDS = 0.5 V. The SS of
the n-type Si0.15 Ge0.85 NS-FET was found to be increasing when tem-
perature was raised from 80 K to 300 K. A rise in temperature leads to
the increase of IOFF which in turn degrade the SS of the device. Phonon
scattering and impurity scattering are the two most important temper-
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Microelectronics Journal 114 (2021) 105141
ature dependent scattering mechanisms in n-type Si0.15 Ge0.85 NS-FET.
At 300 K, impurity scattering dominates where as phonon scattering
will be dominant at 80 K. Lattice temperature of the device also sig-
nificantly degrade the carrier mobility by enhancing phonon scattering
[25]. In 2020, Sankatali Venkateswarlu et al. [25] reported that the
thermal conductivity of the nanosheets decreases with increase in tem-
perature. Increasing the width of nanosheet helps to reduce the ther-
mal resistance of the device and hence to improve the ION . In 2019,
Meng-Ju Tsai et al. [23] investigated the impact of temperature on the
DC performance of vertically stacked p-type NS-FET with GAA, omega
– gate and tri-gate architectures and observed that vertically stacked
p-channel NS-FET with GAA architecture exhibited least SS (Fig. 11
(a)) and least threshold voltage (Fig. 11 (b)) compared with NS-FET
with omega-gate and tri-gate structures. It clearly points out that ver-
tically stacked NS-FET with GAA technology is the most promising
solution for improving the scalability towards future 3-nm technology
node.
7. Impact of gate metal work function
Work function of the gate metal and gate metal thickness are two
important parameters which can be used to modulate the threshold
J. Ajayan et al. Microelectronics Journal 114 (2021) 105141

Fig. 8. The impact of Hch on the (a) transfer curves (b) SS (c) DIBL and (d) ION /IOFF ratio of vertically stacked GAA NS-FET [17].

Fig. 9. (a) The electron velocity as a function of transport direction for NS-FET, NW-FET and FinFET (b) The impact of LG down scaling and S/D doping density
(NS/D ) on the SS (c) The impact of LG down scaling and S/D doping density (NS/D ) on the threshold voltage (VT ) (d) The impact of LG down scaling and S/D doping
density (NS/D ) on the ION /IOFF ratio [22].

voltage of NS-FETs. In 2018, Jun-Sik Yoon et al. [26] investigated the
impact of gate metal work function and gate metal thickness on the
DC performance of both n and p type vertically stacked GAA NS-FETs
using TCAD simulations by varying the work function from 4.22 eV
to 4.82 eV. It was observed that in n-type vertically stacked GAA NS-
FETs, threshold voltage increases with respect to increase in work func-
tion. On the other hand, in p-type vertically stacked GAA NS-FET, the
threshold voltage decreases with increase in gate metal work function
(Fig. 12 (a)). The increase of gate metal work function leads to the
increase in threshold voltage of the device which in turn reduces both
ION and IOFF of the device. Bottom side nanosheet width (Wbot )/top side
nanosheet width (Wtop ) ratio also modulates the threshold voltage and
drive current of both n and p channel vertically stacked GAA NS-FETs.
Both n and p-channel NS-FETs with large Wbot and Wtop exhibit rela-

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J. Ajayan et al. Microelectronics Journal 114 (2021) 105141

Fig. 10. The impact of LG downscaling on the SS and DIBL of NS-FETs with tri-gate, omega-gate and GAA structures [23].

Fig. 11. Impact of temperature on the (a) SS and (b) threshold voltage of the vertically stacked NS-FET with omega-gate, tri-gate and GAA structures [23].

Fig. 12. The impact of work function on the (a) threshold voltage (Vth ) and (b) drive current of n and p channel vertically stacked GAA NS-FETs [26].

tively low threshold voltage compared to NS-FETs with smaller Wbot
and Wtop (Fig. 12 (a)). The drive current of both n and p-channel ver-
tically stacked GAA NS-FETs decreases when gate metal work func-
tion is increased or decreased from 4.52 eV due to the shifting of
threshold voltage. Moreover, both n and p channel vertically stacked
GAA NS-FETs with large Wbot and Wtop (Wbot/Wtop = 50/45 nm)
exhibits relatively high drive current compared to devices with smaller
(Wbot /Wtop = 20/15 nm) Wbot and Wtop due to the large effective
width of the channel (Fig. 12 (b)). The carrier density in the nanosheet
changes significantly with variation in gate metal work function. This is
also a major reason for the shifting of threshold voltage and drive cur-
rent in NS-FETs. For a p-type NS-FET with a work function of 4.22 eV,
a large amount of hole density will be created at the centre of the
nanosheet and the hole density formed near the top and edge of the
nanosheets are very small. When work function increases from 4.22 eV
to 4.82 eV, the hole density created at the edge of nanosheet nearer
to the work function metal increases and only a very small amount of
hole density will be created at the edge of bottom nanosheet channel.
On the other hand, n-type NS-FET exhibits an opposite trend in electron
density in the nanosheets compared with p-type NS-FETs.
8. Impact of source/drain metal depth
Scaling down of nanosheet/channel width or depopulation of Fin
along with the reduction of cell height results in the drastic increase
in source-drain parasitic resistance (RSD ) which severely degrade the
DC performance of multi-gate transistors including NS-FETs [27–38].
Metallic source/drain (S/D) structure can be used to effectively mini-
mize RSD beyond 7-nm technology node. The S/D metal depth (TM0 )
can significantly affect the DC/AC performance of NS-FETs. The impact
of TM0 on the transfer curves of p and n channel NS-FETs with metal-
lic S/D contacts are illustrated in Fig. 13 (a) and Fig. 13 (b) respec-
tively. In 2019, Jun-Sik Yoon [39] reported that increasing the TM0
from 0 nm to 50 nm resulted in the enhancement of drain current in
both p and n channel GAA vertically stacked NS-FETs. This may be due
to the increase of gate capacitance with increase in TM0 . RC delay and

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J. Ajayan et al. Microelectronics Journal 114 (2021) 105141

Fig. 13. The impact of S/D metal depth (TM0 ) on (a) transfer curves of P-type vertically stacked GAA NS-FET (b) transfer curves of N-type vertically stacked GAA
NS-FET (c) ION of P-type vertically stacked GAA NS-FET and (d) ION of N-type vertically stacked GAA NS-FET [39].

Fig. 14. 2-D cross sectional view of vertically stacked NS-FET (TreeFET) and its comparison with FinFET and NS-FET [40].

RSD of the vertically stacked GAA NS-FET can also be minimized effec-
tively by increasing the TM0 . The impact of TM0 and contact resistivity
(𝜌con ) on the ION of both p and n type vertically stacked GAA NS-FETs
are illustrated in Fig. 13 (c) and Fig. 13 (d) respectively. A low contact
resistivity and high TM0 is essential for enhancing the ION of vertically
stacked GAA NS-FETs.
9. Future research directions IN NS-FETs
TreeFETs and GAA negative capacitance NS-FETs (GAA NC NS-
FETs) are considered as the future of NS-FETs towards 3 nm node. Verti-
cally stacked NS-FET with Fin shaped inter bridge channel, also known
as TreeFET, can effectively improve ION compared with conventional
vertically stacked GAA NS-FETs due to the additional channel area for
carrier transport from source to drain. In 2020, Hung-Yu Ye et al. [40]
investigated the influence of height of the inter bridge (HIB ) and width
of the inter bridge (WIB ) on the DC performance of vertically stacked
Ge-NS-FETs. The 2-D cross sectional view of vertically stacked NS-FET
(TreeFET) is shown in Fig. 14. The geometry of TreeFET is considered
as a combination of FinFET and stacked NS-FET. The TreeFET consists
of a vertical interbridge channel (Fin-shaped structure) that connects
the vertically stacked nanosheets. It is very important to reduce the
difference in threshold voltages between the nanosheet and interbridge
channels for the optimization of ION in TreeFETs. The TreeFET with low
HIB (7.5 nm & 10 nm) provides very low channel charge density (nch )
compared with stacked NS-FET without interbridge structure. This indi-
cates that the interbridge channel requires a sufficient height (greater
than 10 nm) to improve the nch and ION . The impact of HIB on the
nch of the TreeFET is plotted in Fig. 15 (a). It was observed that the
nch of the TreeFET increases with increase in HIB . ION of the TreeFET
increases with increase in HIB due to the enhancement of electron den-
sity in the inter bridge channel. ION of TreeFET also increases with
increase in WNS Fig. 15 (b). The HIB does not affect the charge den-
sity in nanosheet channels, however, the charge density in the inter
bridge channel improves with increase in HIB .
Voltage scaling in GAA NS-FETs can be enabled by introducing neg-
ative capacitance (NC) effects. The introduction of NC effect also help
to achieve sub-60 mV/dec SS in GAA NS-FETs. In 2020, Fahimul Islam
Sakib et al. [41] investigated the DC performance of Si-GAA NC-NS-
FET using TCAD simulations. In order to introduce the NC effect, a
metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used in
the gate stack of GAA NS-FETs. It was observed that Si-GAA NC NS-FET
exhibited 9% and 38% lower SS compared with NC-NW FET and NC-
FinFET respectively. Thickness of the ferroelectric layer (TFE ) and gate

8
J. Ajayan et al. Microelectronics Journal 114 (2021) 105141

Fig. 15. (a) The impact of HIB on the channel charge density (nch ) of the TreeFET (b) The impact of WNS on the ION of the TreeFET [40].

Fig. 16. (a) The impact of TFE on the ION of NC NW-FET, NC FinFET and NC NS-FET (b) The impact of TFE on the SS of NC NW-FET, NC FinFET and NC NS-FET (c)
The transfer curves of NC FinFET, NC NW-FET and NC NS-FETs (d) The variation in SS with voltage (VDD ) scaling of single and double stacked NC NS-FETs [41].

charge (QG ) are the two critical parameters that influences the voltage
across the ferroelectric layer (VFE ). The impact of TFE on the ION and
SS of NC NW-FET, FinFET and NS-FET are plotted in Fig. 16 (a) and
(b) respectively. The ION of all the devices were found to be increasing
with increase in TFE . Moreover, the SS of the devices were found to be
decreasing with increase in TFE . Therefore, a large TFE is desirable to
achieve higher ION and lower SS. NC NS-FET exhibits ION and lower
SS compared with NC NW-FET and NC FinFET. The transfer curves of
NC FinFET, NC NW-FET and NC NS-FETs are plotted in Fig. 16 (c).
Single stack NC NS-FET exhibits higher ION and lower SS compared to
double stack NC NS-FET due to reduced parasitic effects. The variation
in SS with voltage (VDD ) scaling of single and double stacked NC NS-
FETs are depicted in Fig. 16 (d). A lower LG is preferable to achieve
low SS as well as DIBL in GAA NC NS-FETs (Fig. 17 (b) and (c) respec-
tively). The impact of nanosheet dimensions (TNS xWNS ) on the transfer
curves of GAA NC NS-FET is depicted in Fig. 17 (a). A large TNS xWNS
is required to achieve higher ION in Si-GAA NC NS-FETs. However, a
large TNS also results in the increase of IOFF due to its poor gate control
over the nanosheets. SS and DIBL also increases with increase in TNS .
The impact of metal work function (WF) on the threshold voltage of
Si-GAA NC NS-FET is illustrated in Fig. 17 (d). The threshold voltage of
the Si-GAA NC NS-FET is found to be increasing with increase in WF of
the gate metal. However, a large WF is required to achieve lower IOFF
and higher ION /IOFF ratio in NC NS-FETs. An overview of state of the
art DC performance of NS FETs are given in Table 1. There is no doubt
that the NS-FETs are going to dominate the semiconductor industry in
the coming years due to their outstanding scalability without degrading
the performance [42–62].
For incessant scaling with silicon to keep Moore’s la alive, NS-FETs
are considered as the most promising solution especially for future 3-
nm technology node [42–63]. At 7-nm technology node, Si-NS-FET pro-
vides higher ION and gm at reduced SCEs compared to FinFET and NW-
FET technologies due to the large effective WNS for the same wafer
footprint. It is also possible to integrate flash memory and dynamic
random access memory (DRAM) onto a single NS-FET because of its
stacked nanosheet structure. This is a major advantage of these transis-
tors which makes them attractive for future analog/digital system on
chip (SoC) applications. NS-FETs with wider WNS offers very low RC
delay and very high ION , gm and fT which also makes them suitable for
future high performance ultra low power integrated circuit applications

9
J. Ajayan et al. Microelectronics Journal 114 (2021) 105141

Fig. 17. (a) The impact of nanosheet dimensions (TNS xWNS ) on the transfer curves of GAA NC NS-FET (b) SS Vs LG characteristics (c) DIBL Vs LG characteristics (d)
Variation of threshold voltage with metal work function [41].

Table 1
An overview of DC performance of NS FETs (WNS : Nanosheet Width, SS: Subthreshold swing, Ref: Reference, LG :
Gate Length).
Ref. LG (nm) WNS (nm) Channel material ION 𝜇 A/𝜇 m ION /IOFF ratio SS mV/dec
[5] 80 90 Ge 1510 105 140
[5] 80 90 Ge 1650 104 130
[2] 12 15 Si – 106 75
[2] 12 15 Si – 106 85
[63] 200 20–100 InGaAs 1350 – –
[6] 60 18.7 GeSn 1975 7 × 104 108
[24] 75 60–100 SiGe >500 5 × 108 150
[13] 14 25 Si 290.5 – 68.10
[13] 14 50 Si 283.7 – 70.01
[13] 14 75 Si 283.1 – 71.04
[16] 7 10 Si 68 2.6 × 107 71
[20] 2500 1500 ZnO – 108 400
[23] 1000 1276 Si – 7.5 × 106 187
[23] 1000 1300 Si – 1.6 × 107 149
[23] 1000 4604 Si – 2.03 × 108 100
[55] 60 135 SiGe 37.6 1.8 × 105 86
[22] 12 50 Si 699 1.2 × 105 71
[60] 12 40 Si 1130 1.13 × 105 79.8
[60] 12 40 Si 1410 1.41 × 105 73.9

[64–71]. The drive current capability of vertically stacked NS-FETs can
be further improved by replacing traditional silicon and germenium
channel materials with III-V materials such as InGaAs, InAs, InSb and
GaN [72–78]. The use of High-K gate dielectric materials with permit-
tivity greater than 20 will help to scaledown the vertically stacked NS-
FETs towards 3 nm technology node.
10. Conclusion
This review article emphasized the effect of geometrical scaling,
the impact of substrate materials, parasitic channel height effects, the
influence of thermal and source/drain (S/D) metal depth effects on the
digital/analog performance of NS-FETs. The compatibility of NS-FETs
with different metal gates along with the crystal orientation of the
nanosheets have also been explored. It has been found that NS-FETs
can be scaled down continuously even below 5 nm technology node
with negligible short channel effects. However, the quantum mechani-
cal effects become severe at these sub-5 nm technology nodes. To toss
out this issue, GAA NS FETs in Vertical stacked horizontal configu-
ration is explored by the researchers. Further, the effective width of
nanosheets in NS-FETs is not limited by Fin quantization as well as
Fin-pitch, which in turn, gives the flexibility of width adjustment to
the device/circuit designers for better performance and power manage-
ment. The NS-FETs compatibility with different metal gates in gate-
stack configuration allows tuning its threshold voltage that in turn
attracts the research community towards these devices for below 5 nm
technology node. Consequently, it can be concluded that NS-FETs is the
most promising candidate for future digital/analog integrated circuit
applications.

10
J. Ajayan et al.
Author statement
Dr. J. Ajayan and Dr. D. Nirmal have role in Conceptualization,
Methodology and Writing Original Draft, Dr. Shubham Tayal, Dr.
Sandip Bhattacharya and Mr. L. Arivazhagan, have the credits to Soft-
ware, Validation and Investigation, Dr. A. S. Augustine Fletcher, Dr. P.
Murugapandiyan and Dr. D. Ajitha have their credits in Formal analysis,
Resources, Data Curation, Writing Review and Editing.
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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