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University of Ottawa
School of Information Technology and Engineering

Name (surname, first name):____________________________________

Number:___________________________________________________

Please circle CEG2131A CEG2131B

CEG2131A&B computer architecture I

Examiners: Professor A. H. G. Al-Dhaher

Professor N.M. Rahmani

Final test December 19, 2002 Time allowed: 3 hours

Notes:
 Calculators are not allowed

 You may use the back of the pages for any side work. This will not be
marked.

 Instruction formats and PSR format for the ARC is given on page 8

 ARC ALU operations is given on page 9

 Microprogram for the ARC is given on page 10 & 11

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Question 1 (20 marks):

The following 10 questions are a multiple-choice type. Circle the correct answer.

1. Converting ( -15)10 to 8-bit binary, using signed 2’s complement notation is equal to:
(a) 01110001 (b) 11110001
(c) 00101101 (d) 11000111

2. The equivalent number in base 4 of (38.625)10 is:

(a) 122.35 (b) 152.25
(c) 252.32 (d) 212.22

3. What portion of an instruction tells the CPU what operation to perform?

(a) Operand (b) Opcode
(c) Code mnemonic (d) None of these

4. What portion of an instruction tells the CPU where data are to be taken from or sent to
during the instruction execution?
(a) Operand (b) Opcode
(c) Code mnemonic (d) None of these

5. Which CPU register provides the address from which the next instruction opcode is to
be fetched?
(a) Stack pointer SP (b) Link register
(c) Program counter PC (d) None of these

6. The basic element used in binary data storage is:

(a) AND gate (b) Flip-flop
(c) Counter (d) None of these

7. If the capacity of a certain memory is 4kbyte, then the number of address lines to
access to all the allocations is:
(a) 4 (b) 4096
(c) 12 (d) 210

8. If the number of lines in the address bus is 20, then we can access to the following
number of memory locations:
(a) 20 (b) 1 Mega
(c) 512 (d) 1 Kilo

9. For the microarchitecture of ARC, the control store is a 2048-word  n-bit ROM,
where n is:
(a) 31 (b) 24
(c) 16 (d) 41

10. In ARC instructions, registers are always referred to in terms of their contents, and
never in terms of an address
(a) True (b) False
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Question 2 (20 marks):

Assuming a system with a 6-bit biased exponent (i.e. excess 32) and a 10-bit two’s
complement mantissa. Perform the following operation.
157.3
- 12.6

By completing the following steps (give you answer for each step)

(i) convert 157.3 to binary

100 111 01 . 010 01

(ii) Normalize the fixed-point binary number

0.10 011 101 010 01 X 28

(iii) Round the mantissa to 10 bits.

0.100 111 011

(iv) Write how the floating point number would be stored

101 000 010 011 101 1

(v) Convert 12.6 to normalized floating point number and rounded to 10 bits.

0.110 010 011 X 24

(vi) Form the two’s complement of the mantissa for the 12.6

1.001 101 101

(vii) Equalize exponents

1.111 100 110 X 28

(ix) Perform addition and give your final restult

0.100 100 001 X 28 = 100 100 00 . 1

(x) Convert your result into decimal and compare to exact answer.

Your result = …144.5………………………………..

Exact result = …144.7……………………………..

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Question 3 (20 marks):

Part A (10 marks)
Write an ARC subroutine that performs swap operation on the 32-bit operands X = 25
and Y = 50, which are stored in memory. Use as few registers as you can. Make you
subroutine starts at memory location 2048.

.begin
org 2048
swap ld [X] , %r1
ld [Y] , %r2
st %r1 , [Y]
st %r2 , [X]
jmpl %r15 + 4 , %r0

X: 25
Y: 50
end

Part B (10 marks):

Write an ARC subroutine that perform subtraction operation on the 32-bit operands X =
50 and Y = 25 which are stored in memory. Make your subroutine starts at memory
location 2048

.begin
org 2048
subtract ld [X] , %r1
ld [Y] , %r2
orncc %r2 , %r0 , %r2 !complement Y
addcc %r2 , 1 , %r2 ! making 2nd complement of Y
addcc %r1 , %r2 , %r2
st %r2 , [Z]
jmpl %r15 + 4 , %r0

X: 50
Y: 25
.end
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Quesiton 4 (20 marks):

Part A (10 marks)
From this object code for the ARC, re-create the source assembly code.

10000100 10000000 10100000 00000001

10000000 10001001 01000000 00000110
00000010 10000000 00000000 00000011
10001100 10010001 10100000 00000001
00010000 10111111 11111111 11111100
10000001 11000011 11100000 00000100

Solution:

b: addcc %r2,1,%r2
andcc %r5,%r6,%r0
be a
orcc %r6,1,%r6
ba b
a: jmpl %r15+4,%r0

Part B (10 marks)

Rewrite the microcode for the call instruction starting at line 1280 so that only three lines
of microcode are used instead of four. The microcode is given in pages 10 & 11

Solution:

1280 : R[15] <- AND(R[PC] , R[PC]); /save %pc in %r15

1281 : R[temp0] <- LSHIFT2 (R [ir]); /shift disp30 left two bits

1282 : R[PC] <- ADD (R[PC] , R[temp0]); /jump to subroutine

GOTO 0;
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Quesiton 5 (20 marks):

Microprocessor system uses 64K memory space of 8 bits. In typical application this
memory space is divided into 4 blocks each of 16K.

(i) Draw the memory map

showing the starting address
(in Hex) and end address
(in Hex) of each of these 4 blocks

(ii) Use a decoder logic element, draw diagram showing how to decode the address of the
the memory space. In your drawing show clearly how the address bus and the data bus
are connected to the memory space.
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(iii) Assuming that a decoder is not available, draw diagram show how to implement the
decoding approach in part (ii) using logic gates such NOT, OR, NOR, AND and NAND.
The chip select signal to be generated is an active low (i. e. CS)
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Instruction formats and PSR format for the ARC

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ARC ALU operations

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Microprogram for the ARC (continues on next page)

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Microprogram for the ARC (continues from previous page)