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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
A 5–13.5 Gb/s Multistandard Receiver With
High Jitter Tolerance Digital CDR
in 40-nm CMOS Process
Zhou Shu, Shalin Huang , Zhipeng Li, Peng Yin , Jiandong Zang, Dongbing Fu,
Fang Tang , Senior Member, IEEE, and Amine Bermak, Fellow, IEEE
Abstract— A 5-13.5 Gbps multi-standard I/O link receiver is
presented in this paper. An inductor-free CTLE, whose gain
and bandwidth are highly adjustable, is achieved by using the
second-order negative capacitance circuit. A high jitter tolerance
clock and data recovery (HJTOL-CDR) is proposed for Spread
Spectrum Clock applications. In this work, the JTOL is improved
by two ways: first, a partial-noise-shaping-based digital loop filter
(PNS-DLF) is implemented to reduce the output jitter caused by
the truncation error in the integral path; second, the proposed
CDR logic is fully custom designed to operate at a quarter-
rate clock of 5 GHz. Moreover, the CDR bandwidth can be
tuned to satisfy various data rates and jitter masks. Post-layout
simulation shows that the proposed CTLE can provide wide gain
tuning range, the boost gain at 10 GHz is beyond 29 dB and
the proposed CDR can tolerate up to 31-kppm frequency offset.
The proposed receiver is fabricated in 40-nm CMOS with an
active area of 0.06 mm2 and 65 mW power consumption at
20 Gbps from 1.2-V supply. Measurement results show that, when
receiving the PRBS31 data at 10 Gbps with 5-kppm frequency
offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at
10 MHz and can guarantee a 0.34 UIpp at high frequency, which
proves that the proposed receiver can meet stringent standards
such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4.
Index Terms— Multi-standard receiver, clock and data recov-
ery, continuous time linear equalizer, jitter tolerance, digital loop
filter, spread spectrum clock.
I. I NTRODUCTION
H IGH-SPEED SerDes system is evolving rapidly
driven by the applications such as edge computing,
ultra high-definition video and emerging data storage
Manuscript received December 30, 2019; revised March 13, 2020 and
April 15, 2020; accepted April 26, 2020. This work was partly sponsored
by Natural Science Foundation of Chongqing, China, No. cstc2019jcyj-
zdxmX0014, and the Fundamental Research Funds for the Central Univer-
sities Project No. 2019CDJGFWDZ002, and by the Research Foundation of
Chongqing Science and Technology Bureau No. cstc2018jszx-cyztzxX0049.
This article was recommended by Associate Editor S. Gupta. (Corresponding
author: Fang Tang.)
Zhou Shu, Shalin Huang, Zhipeng Li, Peng Yin, and Fang Tang are with the
Chongqing Engineering Laboratory of High Performance Integrated Circuits,
School of Microelectronics and Communication Engineering, Chongqing
University (CQU), Chongqing 400044, China.
Jiandong Zang and Dongbing Fu are with the Science and Technology on
Analog Integrated Circuit Laboratory, Chongqing 400060, China.
Amine Bermak is with the College of Science and Engineering, Hamad Bin
Khalifa University, Doha 34110, Qatar.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2020.2991253
1549-8328 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1
applications [1], [3]. Considering the system cost, the receiver
should support the major industrial standards [4], such as USB
3.2, PCIe 3.0/4.0, DisplayPort 1.4, SATA, and JESD204B.
Such a multi-standard receiver design has many technical
challenges [5], [8], such as various data rates, high jitter corner
frequency and jitter tolerance (JTOL) amplitude. As shown
in Fig. 1(a), the standards provide the transfer functions
of continuous time linear equalizer (CTLE) for reference,
therefore, the proposed multi-standard CTLE should have
wide tuning ranges of gain, besides wide bandwidth and
high boost gain [9], [11]. We have slightly improved the
active feedback topology [21], [37], and negative capacitance
circuit (NC) for wide CTLE gain control without using
inductors. Moreover, the peak gain frequency can be changed
from 3.7 GHz to 11.4 GHz by changing the tail current
for optimum loss compensation. Additionally, a high jitter
tolerance clock and data recovery (HJTOL-CDR) is tailored
to SSC applications for frequency offset tracking. Increasing
the CDR loop gain is a way to expand the CDR bandwidth
so as to ameliorate jitter tolerance [12], [13]. However,
too large loop gain decreases phase margin, causing jitter
peaking [14], [15]. Another way is to improve the speed of
the CDR logic [16], but it sharply increases the circuit design
difficulty, especially for SSC applications. Consequently,
many designs [17], [26] adopted subsampling/demultiplexing
techniques to reduce the clock frequency. A summary of the
operating speed of digital loop filters (DLF) for designs in the
past 15 years is shown in Fig. 1(b). Even in newer than 40-nm
process, it is hard to design DLF operating above 2 GHz,
because of the effects of parasitic capacitance/resistance [27].
By reducing the bit width of the phase accumulator, using
carry look ahead adder topology as well as full-custom
CMOS logic, this work pushes the DLF operating speed to a
quarter-rate clock of 5 GHz. On the other hand, when CDR
with high bandwidth is used for SSC tracking, the integral
path of the DLF becomes a non-negligible jitter source
due to the truncation error [28]. In this work, to further
improve JTOL, the partial quantization noise is shaped to
be out of band. As a result, most of jitter introduced by
the truncation error is suppressed with less bit width in
the digital accumulator (ACC), which significantly relieves
the hardware design complexity. Notice that, the proposed
topology does not affect the CDR loop bandwidth and
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 1. (a) Channel compensation requirements for DP 1.4, PCIe 3.0/4.0 and
USB 3.2. (b) Comparison of DLF’s operating speed with published works in
past 15 years.
the loop latency. In [29] and [30], delta-sigma modulator
(DSM) was adopted in the CDRs to improve the resolution
of digital controlled oscillator (DCO) and PI. By using
the above-mentioned proposed techniques, a low-power
multi-standard I/O link receiver with enhanced JTOL is
realized. The theoretical calculation results demonstrate that
the noise power spectral density (PSD) of the proposed CDR
is reduced by about 22 dB compared with the high speed
CDR without a partial-noise-shaping-based digital loop filter
(PNS-DLF). Post-layout simulations show that the DC gain
ranges from −18.4 dB to −3.8 dB, and the maximum boost
gain is beyond 29 dB. Measurement results validate that the
proposed receiver, with the high jitter tolerance CDR, satisfies
the stringent jitter tolerance specifications.
The remainder of this paper is organized as follows.
Section II presents the receiver’s architecture, and analyzes the
CDR’s loop dynamics for SSC applications. Section III gives
a detailed implementation of the PNS-DLF and the CTLE.
Finally, the measurement results and conclusions are reported
in Section IV and Section V, respectively.
II. R ECEIVER A RCHITECTURE AND D ESIGN
C ONSIDERATIONS
A. Receiver Architecture Overview
The proposed receiver, shown in Fig. 2, is realized by using
a half-rate architecture and consists of an impedance matching
network, loss of signal (LOS) detection, two-stage CTLE,
1-tap DFE, CDR, 2:40 demutiplexer and built-in pseudo-
random bit sequence (PRBS) checker. CX for a block refers
to the clocking speed of a block, which is 1/Xth of data
rate, for example, C4 is a quarter-rate clock of 5 GHz. The
off-chip AC-coupling capacitor Ci is generally provided by the
standards, for example, the USB 3.2 requires a AC-coupling
capacitor of 75 nF to 265 nF. AC-coupling serves to isolate
the transmitter and receiver common-mode voltages such that
optimized bias voltages can be chosen independently [19].
After the CTLE, the signal is fed into the half-rate one-tap
perspective DFE to further reduce the post cursor inter-symbol
interference (ISI) [31]. Then the output data signals are sent
into a PRBS checker via a 2:40 demultiplexer for built-in self-
test (BIST). At the same time, output data signals and edge
signals are aligned to a half-rate clock to keep synchronization.
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After that, the bang-bang phase detector (BBPD) receives
data (D) and edge (E) signals to generate the lead or lag
phase information, which is aggregated by the tree-style
majority voter (MV) [14], it has three possible outputs: lead
(Up/Dn = 10, +1), lag (Up/Dn = 01, −1), hold
(Up/Dn = 00,0). A second-order DLF is necessary to track
SSC, which outputs the 6-bit phase control signal PC[5:0],
and the 2-MSB of PC[5:4] is used for coarse phase selection
(PS) from PLL, while the 4-LSB PC[3:0] is converted into a
16-bit thermometer code by the binary to thermometer (B2T)
decoder to finely adjust the digital PI. Finally, an appropriate
sampling clock with a phase resolution of 1/32 UI is recovered.
The digital PI is implemented based on the tri-inverter struc-
ture, which is similar to [32]. The tri-inverter provides good
isolations between the input and output nodes, that is helpful
to avoid the decrease of linearity caused by signal coupling.
By optimizing the circuit structure, the whole CDR in this
work can be implemented by CMOS logic at a relatively faster
speed in 40-nm process, that both the BBPD and the MV run
at a half-rate clock (10 GHz), while the DLF operates at a
quarter-rate clock after 2-times downsampling.
B. Jitter Tolerance Analysis
In this section, a mathematical analysis of CDR loop
dynamics for SSC applications is presented to explain our
design considerations. Latest industrial standards have devel-
oped strict jitter masks. For example, USB 3.2 requires that the
CDR can tolerate 0.17 UI at high frequency, while the jitter
corner frequency of DisplayPort 1.4 is even up to 15 MHz.
The linear model of PI-CDR is shown in Fig. 3, where φin is
the input data phase, φout is the recovered clock phase, φerr
is the phase error, K p is the proportional path gain, K i is the
integral path gain, K d is the phase accumulator gain, and K pi
is phase interpolator gain, and Ndel is the loop delay. The delay
of the integration path can be ignored, especially for high-
speed DLF [14]. K p and K d are adjustable to accommodate
different bandwidth requirements. The linearization method of
the phase detector and majority voter have been discussed
in [13] and in order to reduce the bit error rate (BER),
the phase error must be minimized. The open-loop transfer
function of the CDR can be derived as
K pd K mv K pi K d Ki
L(z) = (K p + )z −Ndel (1)
1 − z −1 1 − z −1
To estimate the maximum input jitter allowed at a target
BER, jitter tolerance function Jt olp− p is adopted, as shown
in (2), where max(ϕerr ) (within 1 UI) indicates the eye closure
caused by deterministic jitter and random jitter.
Jt olp− p = [1 + L(z)] max(ϕerr ) (2)
For a BER of 10−12 , max(ϕerr ) equals 1 − 14σ j − D j . σ j
(UI) is the standard deviation of overall random jitter, which
mainly comes from input data and the recovered clock. D j
(UI) is deterministic jitter. Intuitively, reducing random jitter
can directly improve the JTOL. An alternative way is to adopt
larger K p or K d to increase the value of L(z), however, at the
cost of phase margin degradation and worsen jitter tolerance
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SHU et al.: 5–13.5 Gb/s MULTISTANDARD RECEIVER WITH HIGH JITTER TOLERANCE DIGITAL CDR IN 40-nm CMOS PROCESS 3

Fig. 2. Block diagram of the proposed receiver.

Fig. 3. Linearized PI-CDR model.

at high frequency. When neglecting the effect of loop delay,

(1) can be approximated as
K 1 K p fs · s + K 1 K i fs 2
LG(s) = (3)
s2
where K 1 = K pd K mv K pi K d , f s is the operating frequency
of the DLF. (3) is a typical second-order open loop transfer
function, and its damping factor is proportional to K d and
K p , so increasing K d or K p will increase phase margin and
improve JTOL across the entire frequency apparently given
that JTOL = 1 + LG(s). However, when considering the loop
delay, LG(s) has changed. The CDR model can be simplified
by setting K i = 0, which results in an open loop transfer Fig. 4. Jitter tolerance of CDR versus (a) K d , (b) K p , (c) loop delay(Ndel )
function of and (d) operating rate of DLF.

K 1 K p f s −Ndel ·s / fs
LG(s) = ·e (4)
s
The effect of loop gain on JTOL is shown in
Fig. 4(a, b), the graph indicates increasing the loop gain
(K d , K p ) will create peaking in JTOL. Fig. 4(c) plots the
calculated JTOL as a function of loop latency (Ndel ), which
explains why minimizing the loop latency is critical to avoid
the jitter peaking [18]. Our systematic latency of the CDR
(including DFE) is about 32 UI, which is designed in the
C4 domain and reduces 1/3 loop latency compared with the
design in [19]. Fig. 4(d) illustrates that raising the operating
rate of the CDR can increase the jitter tolerance.  P. K. Hanu-
molu et al. defines a stability factor S = K p K i that needs
to be large enough (>100) to prevent the jitter peaking [30].
However, very small K i could reduce the frequency tracking
range, which may have an negative impact on some SSC
applications [15]. Therefore K i should be chosen considering
both the JTOL and SSC requirements.
C. Frequency Tracking Range
Frequency tracking range of the CDR is an essential spec-
ification, because it determines maximum SSC modulation
depth. The integrator needs to provide enough high-significant
bits to guarantee the tracking range for SSC, and truncate
enough low-significant bits to obtain a fractional gain, so that
the CDR can satisfy enough phase margin. The frequency

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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 5. Implementation of proposed normal high-speed DLF.
tracking range can be approximately expressed as [30]
 
(N−D−1) K d · K pi
FT rack = ± (2 )· (5)
Ts
where N is the bit width of the integrator (the MSB is sign
bit), D is the width of truncation bits and Ts is the DLF
clock period. Apparently, there is a trade-off between the
design difficulty and the frequency tracking range. In other
words, it is difficult to expand the bit width of the integrator
and phase accumulator in such a high operating frequency
domain (5 GHz in 40-nm process). Furthermore, the value of
K pi can not be set too large, otherwise the JTOL could be
degraded [33]. Also, too small PI gain K pi leads to smaller
SSC tracking range and much larger cost (area and power)
for DLF and PI. In this work, a typically value of 1/32 UI is
chosen for K pi .
III. P ROPOSED H IGH -JTOL CDR AND CTLE
I MPLEMENTATION
A. Analysis of the High-Speed DLF
As briefly stated in the introduction section and indicated
in Fig. 4(d), the proposed CDR operates at a high speed to
achieve an improved jitter tolerance. However, when consider-
ing SSC tracking range, the CDR stability and the DLF real-
izability, the high-speed DLF becomes the main challenging
block in the CDR. This paper proposes a high-speed DLF
circuit, based on the classic topology [28] as shown in Fig. 5.
The proportional path achieves various gain by logical left
shift of Up + Dn. The carry look-ahead adder (CLA) is
adopted to implement the 11-bit integrator to reduce the time
delay, which is divided into a 3-stage accumulator for the
convenience of implementation. The first two stages of the
integrator are normal bidirectional accumulators (B-ACC). The
third stage is a signed saturating bidirectional accumulator
(S-ACC), which can avoid a significant output change from
a positive value to negative due to the bit overflow. Although
with full-custom design, the phase accumulator is still the
speed bottleneck of the whole DLF. A compromise between
the bit width of the full adder in the phase accumula-
tor and the operating frequency should be made, that the
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Fig. 6. Jitter model of normal high speed DLF.
input of the phase accumulator is limited to only 4-bit
width which consists of the 3-MSB di[10:8] from the inte-
grator and a extra signed bit to avoid the bit overflow.
The parameters of K p and K d can be programmed accord-
ing to SSC and jitter mask requirements. When K d = 1,
Ts = 4 UI, K pi = 1/32 UI, N = 11 and D = 8,
the CDR provides a maximum frequency tracking range of
FT rack = ±31.25 kppm, which can be calculated by 5. When
the DLF runs at a lower frequency, or has no need to satisfy
SSC applications, the quantization noise of the integrator due
to the bit truncation can be ignored, because of noise suppres-
sion by the narrow bandwidth of the CDR [34]. Unfortunately,
the quantization error becomes a main jitter source in the
proposed wide-band CDR scheme, which is the main design
consideration in this paper to reduce the jitter contribution
to the output phase error and eventually to improve the jitter
tolerance of the CDR.
The jitter model of the normal C4 high-speed DLF and the
characteristic of the integrator quantization noise () is shown
in Fig. 6. Quantization error can be considered as a Gaussian
white noise, and its power spectral density with an uniform
distribution, between − and 0 [20], p(e) is the noise prob-
ability density function and e is the
 noise mean  value. Owing
to uniform distribution, p(e) = 1 , e = −2 . Therefore,
the power of the quantization noise can be derived as 6.
0
2
σe2 = (e − e)2 p(e)de = (6)
12
−
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SHU et al.: 5–13.5 Gb/s MULTISTANDARD RECEIVER WITH HIGH JITTER TOLERANCE DIGITAL CDR IN 40-nm CMOS PROCESS 5

Fig. 8. Jitter model of the proposed PNS-DLF.

before arriving at the final output, the quantization noise passes

through the phase accumulator (K d /1 − z −1 ) and the phase
Fig. 7. Implementation of the proposed PNS-DLF. interpolator (K pi = 1/32), which form a low-pass filter (LPF)
approximately [29], and therefore, the overall quantization
noise could be significantly reduced if the quantization noise
The single sideband noise power spectral density (PSD) of can be shaped into the high frequency zone.
the integral path is given in 7. As shown in Fig. 7, the 4 MSBs di [7 : 4] in the truncated
2 · σe2 8-bit di is fed into a first-order DSM based on a digital
Sφint ( f )= (7) accumulator, where Co is the ACC carry-out bit and only
fs
4-bit width DSM is required. Moreover, owing to di [3 : 0] just
To simplify the analysis, z −1 is approximated as 1 − sTs , equals di [7 : 0]/16, most of the quantization noise is finally
so the CDR response model is converted from z-domain to filtered out without using all 8 truncated bits. As a result,
s-domain. As a result, the effect of the integrator quantization this proposed approach relaxes the circuit structure complexity
noise on the PSD (Serr_int ) of the output phase error can be of the accumulator, and extra LPF for the introduced DSM
approximated as is not required due to the existence of the following phase
⎧

accumulator and phase interpolator.
⎪
⎪
G F G_int (s)
2
⎪
⎪

Serr_int ( f ) = Sφint ( f )

The signal transfer function (STF) of the first-order DSM
⎪
⎪
⎨ 1 + L(s)
s= j 2π f can be seen as a unit gain, while the noise transfer function
K d · K pi −sTs Ndel
⎪ G F G_int (s) = e (8) (NTF) equals 1 − z −1 . As shown in Fig. 8, benefiting from
⎪
⎪ sTs
⎪
⎪ K K K K K the noise shaping function of the DSM, the overall residual
⎪
⎩ L(s) = pd mv pi d (K p + i )e−sTs Ndel quantization noise fed into the following phase accumulator
sTs sTs
consists of two parts: 1) the truncated 4 LSBs di [3 : 0] with
where G F G_int (s) is the forward gain function starting from the amplitude Q L4 of 16 1
; 2) the shaped quantization error
the quantization noise injection point and L(s) is the CDR of DSM with the amplitude of ×NTF. Similar to the normal
open-loop gain. In order to have a more intuitive understanding DLF model analyzed in section II.B, the proposed PNS-DLF
of the truncation error effect, the variance of the output phase PSD can be derived as
error can be calculated by (9), the frequency range for noise ⎧  
⎪
⎪ S ( f ) = Sφ ( f ) + S φ ( f ) · |s · T |2
integration is 0 to 2.5 Ghz. ⎪
⎪
err_dsm

L4

dsm s
⎪
⎪
G F G_int (s)
2
 f s/2 ⎪
⎪
⎨ ×

σerr_int =
2
Serr _int ( f )d f (9) 1 + L(s)
s= j 2π f (10)
0 ⎪ 2
⎪
⎪ 1
⎪
⎪ Sφ L4 ( f ) = Sφint ( f )
The blue line with diamonds in Fig. 9(a) illustrates that ⎪
⎪ 16
as the loop bandwidth increases, the RMS jitter σerr_int of ⎪
⎩
Sφdsm ( f ) = Sφint ( f )
the high-speed CDR also rises. To obtain a better JTOL, it is
necessary to decrease the PSD of the quantization noise due to In order to further quantitatively estimate the noise reduction
the integrator bit truncation, especially for SSC applications. effect, a noise rejection ratio R of the output phase error PSD,
between the proposed PNS-DLF and the normal DLF, can be
defined as
B. Proposed PNS-DLF With Delta-Sigma Modulator 2
Serr_dsm ( f ) 1
This section describes introducing a DSM to realize the R= = + |s · Ts |2s= j 2π f (11)
proposed DLF with the capability of quantization noise shap- Serr_int ( f ) 16
ing. Firstly, the jitter model of the proposed PNS-DLF is built Fig. 9(a) shows the attenuated RMS jitter of the CDR with
in Fig. 8, and then, the noise PSD and the RMS jitter reduction the proposed PNS-DLF under the same loop condition. The
can be calculated compared with the conventional high-speed calculated results of R for different DSM orders are shown
CDR without quantization noise shaping. As shown in Fig. 2, in Fig. 9(b). Indicated by the blue line for the 1st order DSM

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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 9. (a) Calculated contributions to output RMS jitter from the integral
path varying with bandwidth; (b) jitter suppression comparison of different
order DSM.

Fig. 10. Simulated time-domain phase error and histogram distribution results
scheme, the contribution to output jitter PSD from the integral for designs without PNS-DLF (a, b), and with PNS-DLF (c, d), respectively.
path with the proposed PNS-DLF is reduced by about 22 dB,
compared with the conventional high-speed CDR. We have
tried to decrease clock frequency of the phase accumulator to
attain better noise filtering, but it will increase the loop latency.
In addition, unless a higher order filter is used, increasing over-
sampling rate and order of the DSM are not good ways to
improve noise shaping. While considering the hardware com-
plexity and power consumption, some compromises are made
in current work. However, the gain of the phase accumulator
(Kd) can be adjusted to slightly improve noise filtering.
Fig. 11. Comparison of simulated jitter of phase error between the CDR with
and without PNS-DLF for (a) RMS jitter (b) peak to peak jitter, respectively.
C. Simulation Results Comparison of the CDR
Since the proposed CDR is all-digital design which can
be accurately simulated [35], a Matlab/Simulink model is
constructed in this work to evaluate the noise performance
improvement of the CDR using the proposed PNS-DLF in
comparison with the normal high-speed CDR. Fig. 10 (a, c)
show time-domain phase errors, histogram and fitted normal
distributions for CDR with or without the proposed PNS-DLF
(b and d), when receiving 33-kHz, 5000-ppm SSC-modulated
20-Gbps data. A normal high-speed CDR has a phase error
of 0.0266 UIrms/0.1689 UIpp, as indicated in Fig. 10(b). Fig. 12. Jitter tolerance of PNS-DLF at different data rate against (a) PCIe
In contrast, as illustrated in Fig. 10(d), a high-speed 4.0 jitter mask, and (b) USB 3.2 jitter mask.
CDR with the proposed PNS-DLF remains a phase error
of 0.0127 UIrms/0.1065 UIpp for the same loop parameters.
the truncation error of integral path. But when modulation
The results in Fig. 10 are from the time-accurate behavioral
depth of SSC is more than 1 kppm, the proposed CDR with
simulations with SSC stress in Simulink, this model is more
PNS-DLF has advantage in suppressing the quantization error.
close to the actual schematic, However, the results in Fig. 9 are
Fig. 12 demonstrates the simulated JTOL results of
theoretically calculated by linearized CDR model. So the
the proposed CDR when receiving 33-kHz, 5,000-ppm
results in Fig.10 are not in good agreement with the results
SSC-modulated PRBS7 data. A random jitter of 0.02UIrms is
in Fig.9. But importantly, they all illustrate that adopting the
injected into the recovered clock to represent the noise from
proposed method is beneficial to improve JTOL.
PLL and input data. To reduce the simulation time, the CDR
When the loop bandwidth is fixed and modulation depth of
only receives one million data bits to confirm that the BER
SSC is varied from 0 to 13 kppm, the RMS jitter and the peak
is below 10−6 . Fig. 12(a) and (b) illustrate that the proposed
to peak jitter of phase error is shown in Fig. 11(a) and (b),
HJTOL-CDR has enough jitter budget to pass multi-standard
respectively. It can be found that when owing to SSC mod-
masks.
ulation depth is less than 1 kppm, there is no enough fre-
quency deviation to cause large truncation error, therefore the
proposed CDR with PNS-DLF cannot show full advantage of D. Implementation of High-Gain and Wide-Band CTLE
quantization noise shaping. This is one reason for that many As shown in Fig. 1(a), multiple I/O link standards ask for
CDRs without requirements of SSC tracking don’t care about different channel loss compensation requirements, which need

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SHU et al.: 5–13.5 Gb/s MULTISTANDARD RECEIVER WITH HIGH JITTER TOLERANCE DIGITAL CDR IN 40-nm CMOS PROCESS 7

Fig. 13. The schematic of the proposed CTLE circuit, with 2nd -order negative capacitor (NC).

that CTLE has reconfigurable features with wide bandwidth, large (> 200 mV ), the NC can be turned off to save power,
high boost gain, and wide DC gain range [36]. However, because the CTLE can provide enough high-frequency gain
in this work, realizing such a CTLE faces two main challenges, for the channel compensation.
which are: 1) using no inductor to save chip area; 2) large ⎧
⎪ Vout G m1 R L1 · G m2 R L2
parasitic capacitance due to six samplers needed in the half- ⎪
⎪ =
⎪
⎪ 1 + G m f b R L1 · G m2 R L2
rate receiver. To solve these problems, a CTLE structure ⎨ Vin
based on RC source-degeneration equalizer is implemented G m f b = gm3 gm4 gm5 R3 R4 (12)
⎪
⎪
with a proposed 2nd -order negative capacitor (NC) circuit, ⎪ R L1 = R L1 −R NC1 − R I 1
⎪
⎪
⎩ 
as shown in Fig. 13. Firstly, the CTLE employs the classic R L2 = R L2 −R NC2 − R I 2
current-mode-logic (CML) stages, and a zero is created by
Adjustable degeneration resistor (Rs1 , Rs2 ) and capacitor
inserting a resistor R p and a capacitor C p in the feedback
(Cs1 , Cs2 ) are also adopted to further extend the tuning ranges.
loop to maximize the CTLE bandwidth [9]. Additionally,
Shown by the transconductance expressions in 13 [37], the DC
differential Miller capacitors C M are adopted to reduce the
gain increases as the degeneration resistor reduces, and the
output capacitance of the first stage, and thus the bandwidth
peak gain can be adjusted by changing the value of the
is extended. Moveover, a 2nd order NC circuit is introduced
degeneration capacitor.
to enhance the CTLE gain and bandwidth further. Z NC is
the equivalent impedance of the NC circuit, which can be gm1
G m1 =
derived as −R NC − SC1NC in the high frequency region, where 1 + gm1 ( 1+sRRs1s1 Cs1 )
 
R NC = −(2 + C gs 2C NC ) gmNC . Because of C gs < C NC , 1 + s Rs1 Cs1
R NC approximately equals −2 gm NC , where gm NC and C gs =
Rs1 + 1+sgRm1
s1 C s1
are the transconductance and the parasitic capacitance of the
1
cross-coupled NMOS transistors.
 As a result, the NC1 circuit ≈ + sCs1 , i f 1 + s Rs1 Cs1  gm1 Rs1 (13)
can create a zero (ωz = 1 R NC1 C NC1 ) in the CTLE transfer Rs1
function, and therefore the low-frequency pole can be can- According to the simulation result at the slow-slow (ss)
celed. As shown in Fig. 14(a), when NC1 is enabled, the peak process corner and 125o C, tuning Rs1 can provide a wide
gain can be increased by 5.42 dB. gain range of 14.67 dB, as depicted in Fig. 14(c). When
Importantly, the proposed CTLE explores active feedback the receiver needs to satisfy the Display Port 1.4 (high peak
technology, and we insert two amplifiers (gm3 and gm4) in the gain), the NC1 and NC2 can be simultaneously enabled to
feedback loop to achieve lower DC gain, which can be proved enhance the peak gain and the DC gain. Fig. 14(d) shows
by (12). In addition, the second stage NC2 is mainly adopted that increasing Cs1 can maximize 4.34 dB of the peak gain.
to improve the DC gain. In low frequency region, the capacitor Additionally, Rs2 can provide about 8 dB coarse tuning range
C NC2 can be seen as disconnected, thus the impedance Z NC2 of the DC gain, the simulated maximum boost gain is above
approximately equals −R NC2 − R I 2 , where R I 2 is resistance 29 dB, the peak gain frequency is changed from 3.7 GHz to
of the current source in the NC2. After applying standard 11.4 GHz by controlling the tail current consumption. The
feedback equations, the DC gain of the overall CTLE can be maximum GBW is around 12.6 GHz, the load capacitance
expressed as 12. Where G m is the equivalent transconductance, at the CTLE output is more than 500 fF, including parasitic
R L represents the equivalent load resistance. If appropriate cap extracted by the layout, and this load capacitance is used
values of R L2 , R I 2 and R NC2 are chosen, a large value of for the simulation results. As shown in Fig.15, although the
R L2 can be achieved, thereby the DC gain can be increased. incoming data attenuated by imperfect channel, the equalized
As shown in Fig. 14(b) with the enabled NC2, the DC gain is data show wide eye widths. In conclusion, the small-signal
increased by 6.59 dB without sacrificing the peak gain at high analysis and post-layout simulation results indicate that the
frequency. When the swing of the received data is relatively proposed CTLE can compensate for various channel losses,

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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 14. Frequency response curves of the CTLE with and without
(a) NC1 circuit (NC2 off), (b) NC2 circuit (NC1 on), and varies with
(c) Rs1 , (d) Cs1 .
Fig. 15. Simulated eye diagrams of the received and the equalized data.
which is suitable for the multi-standard receiver. Moreover,
according to post-layout simulations, the eye width of the
recovered half-rate data (10 Gbps) is about 0.90 UIpp, which
illustrates the DFE can further reduce ISI, and the CDR is
capable of jitter tracking.
IV. M EASUREMENT R ESULTS
The proposed receiver is designed and fabricated in a
mixed-signal 40-nm CMOS process. Fig. 16 shows the chip
microphotograph that consists of four RX lanes, a charge-
pump PLL and a shared digital logic circuit. The core chip
size is 760 × 670 μm 2 , where the RX and PLL occupy an
active area of 0.062 mm2 and 0.19 mm2 , respectively. For
each RX lane, core areas for CTLE, DFE, and CDR are about
0.023 mm2 , 0.006 mm2 , and 0.011 mm2 , respectively. The
fan-out wafer level packaging (FOWLP) technique is adopted
for high-reliability applications to reduce package parasitics.
The power consumption of the multi-phase PLL at 10 GHz
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Fig. 16. Microphotograph of the fabricated chip.
Fig. 17. RX chip area and measured power consumption.
is 82 mW, including the clock distribution network, and the
phase noise is around −87 dBc/Hz (@1MHz).
Each RX lane consumes 65 mW with a 1.2-V power
supply at 20 Gbps, which refers to a energy efficiency
of 3.3 mW/Gbps at the maximum data rate, including the
global clock distribution. The percentage breakdown of the
RX power consumption is illustrated in Fig. 17, which shows
that the analog frontend (CTLE + Samplers + DFE) accounts
for 47% (30 mW) of the total power consumption and the
secondary power-dominant block is the digital CDR (38%).
At 10 Gbps with a 1.2-V power supply, the power consumption
for each RX is reduced to 43 mW.
The total channel loss at the Nyquist frequency (5 GHz)
is estimated to be about 14 dB including package (2 dB),
3-cm-long Rogers 4350B PCB traces (1.5 dB), SMA con-
nectors (1dB), and a 2.5-m cable(9.2 dB), which is shown
in Fig. 18. A measured eye diagram at the CTLE output
with a 10-Gb/s PRBS7 data pattern is displayed in Fig. 19(a).
Note that, this eye diagram is the output after the CTLE’s
output passes through high-speed buffers. Total jitter (TJ) is
31.6 ps at a bit error rate (BER) of 10−12 . The corresponding
BER bathtub curves is shown in Fig. 19(b), the horizontal eye
opening was 0.68 UI.
Due to the data rate limitation of our lab equipment (Agilent
N4872A), the JTOL can only be measured below 13.5 Gbps.
When receiving PRBS31 data at 10 Gbps with a 5-kppm
SSC frequency offset, the voltage amplitude of the transmitted
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SHU et al.: 5–13.5 Gb/s MULTISTANDARD RECEIVER WITH HIGH JITTER TOLERANCE DIGITAL CDR IN 40-nm CMOS PROCESS 9

TABLE I
S UMMARY AND C OMPARISON TO D IGITAL -CDR BASED RX

Fig. 18. Measured insertion loss of a 2.5-m cable.

data is 1 Vpp without feed-forward equalization (FFE), and

the measured BER of 10−12 is achieved with a 95% con-
fidence interval. The measured JTOL against USB 3.2, DP
1.4 and PCIE 4.0 jitter masks is reported in Fig. 20. When
PNS-DLF is turned on, the amplitude of the sinusoidal jitter
tolerance is 0.39 UIpp at 10 MHz which remains above
0.34 UIpp for the high frequency condition above 20 MHz.
The RX can work at 20 Gb/s data rate, that is proved by
built-in self test using the built-in PRBS checker. In addition,
when the data rate is at 13.5 Gb/s, the measured JTOL Fig. 19. (a) Measured eye diagram, and (b) BER bathtub at 10 Gbps with
with the PNS-DLF ON at 10Mhz is 0.43 UIpp, and the 14 dB channel loss.
minimum high-frequency JTOL is 0.32 UIpp, that is improved
by 0.048 UIpp compared with the PNS-DLF OFF. The data
rate is measured at 10 Gbps, which is equivalent to a 20 Gbps high-frequency jitter tolerance still well exceeds the tolerance
signal whose every bit is repeated two times. But with this mask. Note that, the main reason for the decrease of high-
lower-rate signal, the high-frequency tolerance may be over- frequency JTOL from 0.6 UIpp (simulation) to 0.3 UIpp (mea-
estimated while the low-frequency tolerance may be under- surement) is that, deterministic jitter is not considered in
estimated due to the reduced data transition(similar to reduce simulation process, another reason is that the BER of the
CDR bandwidth) [21]. Therefore, kd is changed to 1/4 to measurement is more stringent. However, deterministic jitter
indirectly increase data transition density. Nonetheless, the can be found by simulating circuit, and the deterministic

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10
Fig. 20. Sinusoidal jitter tolerance measured at 10 Gb/s with 14 dB channel
loss.
jitter can be injected into the CDR’s simulation model to
acquire JTOL, which will be closer to the measurement results.
Although the proposed PNS-DLF only helps the JTOL by
0.05 UIpp, it has already reduced the most of the jitter from the
integral path. Moreover, under terrible channel and SSC stress,
it is easier for the receiver to satisfy more industrial standards.
In conclusion, the measured JTOL results show that the
proposed receiver meets the requirements of multiple I/O link
standards (PCIe 4.0, USB 3.2, DP1.4 and so on). The per-
formance summary of the proposed design and the previously
reported receivers is given in Table I. It can be found that
this work achieves good jitter performance under a wide-range
SSC stress with a little sacrifice of power and area in 40-nm
CMOS process.
V. C ONCLUSION
In this work, a 5-13.5 Gbps multi-standard receiver in 40 nm
CMOS is proposed. The total power consumption and area of
4 lane RX with one PLL are 344 mW, 0.51 mm2 , respectively.
A high boost gain CTLE is achieved, and its DC gain range
is widely configured for various standards. Another key block
is the proposed high jitter tolerance CDR, which is designed
full custom to keep it running at a quarter-rate clock to
reduce loop latency. Furthermore, it has been tailored to SSC
applications, and partial noise shaping technique is employed
to lower output jitter caused by truncation error with little
power and area penalty. Moreover, with enough JTOL margin,
and high jitter corner frequncy, the proposed CDR is capable
of satisfying JTOL mask of the latest advanced standard such
as USB 4, PCIe 5.0, 200G/400G Ethernet.
R EFERENCES
[1] J. E. Proesel et al., “A 32 Gb/s, 4.7 pJ/bit optical link with- 11.7 dBm
sensitivity in 14-nm FinFET CMOS,” IEEE J. Solid-State Circuits,
vol. 53, no. 4, pp. 1214–1226, Apr. 2018.
[2] Y. Lee, Y. Choi, J. Choi, and C. Kim, “24-Gb/s input-data-independent
clock and data recovery utilizing bit-efficient braid clock signaling
with fixed embedded transition for 8K-UHD intrapanel interface,” IEEE
Solid-State Circuits Lett., vol. 2, no. 3, pp. 21–24, Mar. 2019.
Authorized licensed use limited to: University College London. Downloaded on May 23,2020 at 19:02:58 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
[3] X. Zheng et al., “A 40-Gb/s quarter-rate SerDes transmitter and receiver
chipset in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 11,
pp. 2963–2978, Nov. 2017.
[4] M. Pozzoni et al., “A multi-standard 1.5 to 10 Gb/s latch-based 3-tap
DFE receiver with a SSC tolerant CDR for serial backplane commu-
nication,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1306–1315,
Apr. 2009.
[5] M. Erett et al., “A 0.5–16.3 Gbps multi-standard serial transceiver
with 219 mW/channel in 16-nm FinFET,” IEEE J. Solid-State Circuits,
vol. 52, no. 7, pp. 1783–1797, Jul. 2017.
[6] S. Ma, H. Yu, Q. J. Gu, and J. Ren, “A 5–10-Gb/s 12.5-mW source
synchronous I/O interface with 3-D flip chip package,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 66, no. 2, pp. 555–568, Feb. 2019.
[7] S. Biereigel et al., “A low noise fault tolerant radiation hardened
2.56 Gbps clock-data recovery circuit with high speed feed forward
correction in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 67, no. 5, pp. 1438–1446, May 2020.
[8] Y.-H. Kim, T. Lee, H.-K. Jeon, D. Lee, and L.-S. Kim, “An input data
and power noise inducing clock jitter tolerant reference-less digital CDR
for LCD intra-panel interface,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 64, no. 4, pp. 823–835, Apr. 2017.
[9] S. Parikh et al., “A 32Gb/s wireline receiver with a low-frequency
equalizer, CTLE and 2-tap DFE in 28 nm CMOS,” in IEEE ISSCC
Dig. Tech. Papers, Feb. 2013, pp. 28–29.
[10] H. Liu et al., “A 5-Gb/s serial-link redriver with adaptive equalizer
and transmitter swing enhancement,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 61, no. 4, pp. 1001–1011, Apr. 2014.
[11] C.-F. Liao and S.-I. Liu, “A 40 Gb/s CMOS serial-link receiver with
adaptive equalization and clock/data recovery,” IEEE J. Solid-State
Circuits, vol. 43, no. 11, pp. 2492–2502, Nov. 2008.
[12] T. Masuda et al., “A 12 Gb/s 0.9 mW/Gb/s wide-bandwidth injection-
type CDR in 28 nm CMOS with reference-free frequency capture,” IEEE
J. Solid-State Circuits, vol. 51, no. 12, pp. 3204–3215, Dec. 2016.
[13] J. Liang, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi,
“Loop gain adaptation for optimum jitter tolerance in digital CDRs,”
IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2696–2708, Sep. 2018.
[14] I. Ozkaya et al., “A 60-Gb/s 1.9-pJ/bit NRZ optical receiver with low-
latency digital CDR in 14-nm CMOS FinFET,” IEEE J. Solid-State
Circuits, vol. 53, no. 4, pp. 1227–1237, Apr. 2018.
[15] M. Talegaonkar, R. Inti, and P. K. Hanumolu, “Digital clock and data
recovery circuit design: Challenges and tradeoffs,” in Proc. IEEE Custom
Integr. Circuits Conf. (CICC), Sep. 2011, pp. 1–8.
[16] P. A. Francese et al., “A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and
baud-rate CDR with 31 kppm tracking bandwidth,” IEEE J. Solid-State
Circuits, vol. 49, no. 11, pp. 2490–2502, Nov. 2014.
[17] S. Saxena et al., “A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver,” IEEE
J. Solid-State Circuits, vol. 52, no. 5, pp. 1399–1411, May 2017.
[18] M.-J. Park and J. Kim, “Pseudo-linear analysis of bang-bang controlled
timing circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 6,
pp. 1381–1394, Jun. 2013.
[19] G. R. Gangasani et al., “A 32 Gb/s backplane transceiver with on-chip
AC-coupling and low latency CDR in 32 nm SOI CMOS technology,”
IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2474–2489, Nov. 2014.
[20] J. Liang, M. S. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura,
“On-chip measurement of clock and data jitter with sub-picosecond
accuracy for 10 Gb/s multilane CDRs,” IEEE J. Solid-State Circuits,
vol. 50, no. 4, pp. 845–855, Apr. 2015.
[21] S.-H. Chu et al., “A 22 to 26.5 Gb/s optical receiver with all-digital
clock and data recovery in a 65 nm CMOS process,” IEEE J. Solid-
State Circuits, vol. 50, no. 11, pp. 2603–2612, Nov. 2015.
[22] J.-Y. Lee et al., “A power-and-area efficient 10 × 10 Gb/s bootstrap
transceiver in 40 nm CMOS for referenceless and lane-independent
operation,” IEEE J. Solid-State Circuits, vol. 51, no. 10, pp. 2475–2484,
Oct. 2016.
[23] R. Navid et al., “A 40 Gb/s serial link transceiver in 28 nm CMOS
technology,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 814–827,
Apr. 2015.
[24] T. Musah et al., “A 4–32 Gb/s bidirectional link with 3-Tap FFE/6-
tap DFE and collaborative CDR in 22 nm CMOS,” IEEE J. Solid-State
Circuits, vol. 49, no. 12, pp. 3079–3090, Dec. 2014.
[25] W. Rahman et al., “A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate
digital CDR with DFE and CTLE in 28-nm CMOS,” IEEE J. Solid-State
Circuits, vol. 52, no. 12, pp. 3517–3531, Dec. 2017.
[26] U. Singh et al., “A 780 mW 4 × 28 Gb/s transceiver for 100 GbE
gearbox PHY in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49,
no. 12, pp. 3116–3129, Dec. 2014.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

SHU et al.: 5–13.5 Gb/s MULTISTANDARD RECEIVER WITH HIGH JITTER TOLERANCE DIGITAL CDR IN 40-nm CMOS PROCESS 11

[27] M. Verbeke et al., “A 1.8-pJ/b, 12.5–25-Gb/s wide range all-digital clock Peng Yin received the B.S. degree from the College
and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 53, no. 2, of Mobile Telecommunications, Chongqing Univer-
pp. 470–483, Feb. 2018. sity of Posts and Telecommunications, Chongqing,
[28] J. L. Sonntag and J. Stonick, “A digital clock and data recovery archi- China, in 2014. He is currently pursuing the Ph.D.
tecture for multi-Gigabit/s binary links,” IEEE J. Solid-State Circuits, degree with School of Microelectronics and Com-
vol. 41, no. 8, pp. 1867–1875, Aug. 2006. munication Engineering, Chongqing University. His
[29] T. Lee, Y.-H. Kim, J. Sim, J.-S. Park, and L.-S. Kim, “A 5-Gb/s research interest includes digital integrated circuit
2.67-mW/Gb/s digital clock and data recovery with hybrid dithering design.
using a time-dithered delta–sigma modulator,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 24, no. 4, pp. 1450–1459, Apr. 2016.
[30] P. K. Hanumolu, G.-Y. Wei, and U.-K. Moon, “A wide-tracking range
clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 43,
no. 2, pp. 425–439, Feb. 2008.
[31] W.-C. Chen et al., “A 2.5-8Gb/s transceiver with 5-tap DFE and second
order CDR against 28-inch channel and 5000ppm SSC in 40 nm CMOS
technology,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010,
pp. 1–4. Jiandong Zang received the B.Sc. and master’s
[32] J. Liang, A. Sheikholeslami, H. Tamura, and H. Yamaguchi, “On-chip degrees from the University of Electronic Sci-
jitter measurement using jitter injection in a 28 Gb/s PI-based CDR,” ence and Technology of China (UESTC), Chengdu,
IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 750–761, Mar. 2018. China, in 2005 and 2008, respectively. He is cur-
[33] H. Won et al., “A 0.87 W transceiver IC for 100 gigabit Ethernet rently a Researcher with the Science and Tech-
in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 2, nology on Analog Integrated Circuit Laboratory,
pp. 399–413, Feb. 2015. Chongqing, China. His research interests focus on
[34] H. Song, D.-S. Kim, D.-H. Oh, S. Kim, and D.-K. Jeong, high-speed digital-to-analog converters and signal
“A 1.0–4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and processing.
adaptive proportional gain control,” IEEE J. Solid-State Circuits, vol. 46,
no. 2, pp. 424–434, Feb. 2011.
[35] Y.-C. Huang, P.-Y. Wang, and S.-I. Liu, “An all-digital jitter tolerance
measurement technique for CDR circuits,” IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 59, no. 3, pp. 148–152, Mar. 2012.
[36] S. Choi et al., “A 0.65-to-10.5 Gb/s reference-less CDR with asyn-
chronous baud-rate sampling for frequency acquisition and adaptive
equalization,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 2, Dongbing Fu received the B.Sc. and master’s
pp. 276–287, Feb. 2016. degrees from the University of Electronic Science
[37] Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and and Technology of China (UESTC), Chengdu,
T. Kuroda, “A 10-Gb/s receiver with series equalizer and on-chip ISI China, in 2000 and 2003, respectively. He is
monitor in 0.11-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 4, currently a Senior Engineer with the Science
pp. 986–993, Apr. 2005. and Technology on Analog Integrated Circuit
Laboratory, Chongqing, China. His research interests
focus on high performance mixed-signal IC designs.
Zhou Shu received the B.Sc. and master’s degrees
from the College of Communication Engineer-
ing, Chongqing University, Chongqing, China,
in 2015 and 2017, respectively, where he is currently
pursuing the Ph.D. degree. His research interest
includes mixed-signal Integrated circuit design for
high speed interconnection.

Fang Tang (Senior Member, IEEE) received the

B.S. degree from Beijing Jiaotong University, China,
in 2006, and the M.Phil. and Ph.D. degrees from The
Hong Kong University of science and Technology
Shalin Huang received the B.S. degree from in 2009 and 2013, respectively. He is currently
the College of Microelectronics and Communica- the Distinguished Research Fellow with Chongqing
tion Engineering, Chongqing University, Chongqing, University, China, and also the Associate Direc-
China, in 2016, where she is currently pursuing the tor with the Chongqing Engineering Laboratory of
Ph.D. degree. Her research interest focuses on high- High Performance Integrated Circuits and leads the
speed links. Smart Integrated Circuits and Systems Laboratory
(http://sislab.cqu.edu.cn/).

Zhipeng Li received the B.Sc. degree from the Col- Amine Bermak (Fellow, IEEE) received the M.Eng.
lege of Electrical Information Engineering, Henan and Ph.D. degrees in electronic engineering from
University of Engineering, Henan, China, in 2016. Paul Sabatier University, Toulouse, France, in 1994
He is currently pursuing the master’s degree with and 1998, respectively. He was the Founder and
Chongqing University. His research interest focuses the Leader of the Smart Sensory Integrated Systems
on mixed-signal integrated circuit design for bio- Research Laboratory, HKUST. He is currently a
medical sensor. Full Professor with the College of Science and
Engineering, Hamad Bin Khalifa University, Qatar.

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