546
2, FEBRUARY 2022
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate
Bang-Bang CDR Without Reference and Separate
FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed
of the PAM-4 Input in 28-nm CMOS
Xiaoteng Zhao , Student Member, IEEE, Yong Chen , Senior Member, IEEE, Pui-In Mak , Fellow, IEEE,
and Rui P. Martins , Fellow, IEEE
Abstract— This article reports a single-loop full-rate bang-bang
clock and data recovery (BBCDR) circuit supporting a four-
level pulse amplitude modulation (PAM-4) pattern. We eliminate
both the reference and the separate frequency detector (FD) by
deliberately adding two fixed strobe points in the bang-bang
phase detector (BBPD) curve via a clock-selection scheme.
As such, we can achieve a wide frequency-capture range in a
single-sided FD polarity. The BBPD also incorporates a hybrid
control circuit to automate the frequency acquisition over a wide
frequency range. Prototyped in a 28-nm CMOS, the proposed
BBCDR occupies a tiny area of 0.0285 mm2 and exhibits a
23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/µs]
and energy efficiency (0.68 pJ/bit) compare favorably with the
state of the art.
Index Terms— Acquisition speed, bang-bang clock and data
recovery (BBCDR), charge pump (CP), CMOS, four-level pulse
amplitude modulation (PAM-4), frequency detector (FD), hybrid
control circuit (HCC), jitter tolerance (JTOL), jitter transfer
function (JTF), phase detector (PD), strobe point (SP).
I. I NTRODUCTION
T HERE is a strong trend toward realizing clock and data
recovery (CDR) circuits for serializer and de-serializer
(SerDes) receivers to support a wide capture range without
requiring a reference frequency input [1]–[31]. This approach
Manuscript received February 24, 2021; revised June 10, 2021 and July 20,
2021; accepted September 13, 2021. Date of publication September 29,
2021; date of current version January 28, 2022. This article was approved
by Associate Editor Daniel Friedman. This work was supported in part
by Guangzhou Science and Technology Innovation and Development of
Special Funds (GSTIC) under Grant EF002/IME-CY/2019/GSTIC and in
part by Macau Science and Technology Development Fund (FDCT) through
the SKL Fund under Grant SKL-AMSV(UM)-2020-2022. (Corresponding
author: Yong Chen.)
Xiaoteng Zhao, Yong Chen, and Pui-In Mak are with the State Key
Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau
999078, China, and also with the Department of Electrical and Com-
puter Engineering (DECE), Faculty of Science and Technology, Institute of
Microelectronic (IME), University of Macau, Macau 999078, China (e-mail:
ychen@um.edu.mo).
Rui P. Martins is with the State Key Laboratory of Analog
and Mixed-Signal VLSI, University of Macau, Macau 999078, China,
and also with the Department of Electrical and Computer Engi-
neering (DECE), Faculty of Science and Technology, Institute of
Microelectronic (IME), University of Macau, Macau 999078, China,
on leave from the Instituto Superior Técnico, Universidade de Lisboa,
1049-001 Lisbon, Portugal.
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/JSSC.2021.3113773.
Digital Object Identifier 10.1109/JSSC.2021.3113773
0018-9200 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO.
enables flexible support for a range of applications while
avoiding the use of external crystals. The key challenges in
designing such a referenceless CDR include its robustness,
the speed and range of the frequency acquisition, and its
area and energy (<1 pJ/bit) efficiency. Most of the existing
solutions, based on the separate frequency detector (FD)
or lock detector [1]–[29], use the input data stream [1]–
[8] to sample the multi-phase clocks for the frequency-
acquisition function, implying that they are not suitable
for multi-level data input, e.g., four-level pulse amplitude
modulation (PAM-4). The injection-locking-type CDR also
demands large-swing data signals [9]. Although the dual-
loop architecture [10]–[16] provides more design freedom,
it is hard to guarantee robustness during the state transition
between frequency acquisition and phase locking. To sur-
mount this issue, a simpler single-loop CDR topology merges
clock-phase-selection (CPS)- [4] and data-phase-selection
(DPS)-based [5] FDs. The above FDs effectively increase the
capture range of the open-loop FD but still require the data as
the clock signal. To avoid this, Huang et al. [17] reported an
FD-less referenceless CDR based on the linear phase detector
(PD) with a deliberate strobe point (SP). Regrettably, it suffers
from the following limits: 1) the delay-based offset is sensitive
to the process, voltage, and temperature (PVT) variations;
2) large off-chip capacitors (2 × 510 pF) are required to
complete the control logic; 3) the single-sided capture range
enhancement must bind with a certain frequency error polar-
ity, and 4) it experiences a long frequency-acquisition time
(116 μs). While the bang-bang phase/FD [18]–[20] uses the
always-on multi-phase oversampling to improve the acqui-
sition speed of 1.005 Gb/s/μs, it almost doubles the power
budget of the clock generation to obtain extra clock phases,
lowering the energy efficiency of 2.25 pJ/bit.
This article extends [30] that reported the single-loop full-
rate bang-bang clock and data recovery (BBCDR) for PAM-4
signaling, without reference and separate FD. By deliberately
adding two fixed SPs in the bang-bang PD (BBPD) curve
compared with the linear counterpart [17], we realize a wide
frequency-capture range in a single-sided FD polarity. Also,
unlike the typical dual-loop CDRs that may suffer from
the transition issue between frequency acquisition and phase
locking, the proposed BBCDR manifests fast and automatic
ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR
Fig. 1. (a) Block diagram of the proposed BBPD in full-rate topology and
(b) its operation principle that uses clock-phase switching to realize ZSP, NSP,
and PSP.
frequency acquisition in a single loop via a hybrid control
circuit (HCC). Prototyped in 28-nm CMOS, the design auto-
matically tracks 23-to-29-Gb/s PAM-4 input data with a faster
acquisition speed of 8.2 Gb/s/μs while outperforming the
recent CDRs in terms of smaller area (0.0285 mm2 ) and better
energy efficiency (0.68 pJ/bit).
The remainder of this article is organized as follows.
Section II introduces the proposed frequency-acquisition tech-
nique based on deliberate SPs and its control principle.
Section III details the circuit design of the proposed BBCDR
with the simulated results. Section IV presents the measured
results. Finally, Section V draws the conclusions.
II. P ROPOSED F REQUENCY-ACQUISITION T ECHNIQUE
The full-rate BBPD [Fig. 1(a)] runs by the complementary
clocks: CK = CK0 and CKS = CK180 . With the symmetric
PD output about the origin, there is an equal chance of being
Early or Late in the timing diagram. If the data rate ( f DR )
deviates largely from the clock frequency ( f CK ), the average
output current (Iout,av ) of FD for both the open loop and closed
loop will yield zero, indicating that the typical BBPD cannot
capture the frequency variation for a certain frequency error
( f = f DR − f CK ). To solve it, we propose a clock-phase
switching scheme to dynamically alter the PD/FD character-
istic. Specifically, we denote the case as zero SP (ZSP) when
CKS = CK180 [Fig. 1(b)]. If CKS = CK90 , the PD output will
show a polarity change at ϕ = −π/2. The negative SP (NSP)
favors the chance of being Early than Late. In this case,
Iout,av of the open-loop FD will keep the single-sided negative
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547
Fig. 2. State transition between NSP, ZSP, and PSP modes in the proposed
BBCDR for frequency acquisition and phase locking.
polarity over a certain  f , and it leads to VCONT decreasing
as desired. Likewise, if CKS = CK270 , it will imply a positive
SP (PSP) in the PD curve [Fig. 1(b)], and the single-sided
positive polarity of the open-loop FD output results in VCONT
increasing. Differing from the open-loop situation, the closed-
loop FD curve exhibits a stable point at  f = 0. Regardless
of whether the closed-loop experiences single-sided polarity
in PSP or NSP, it can still reach the locking condition.
The above observation leads to the SP-selection scheme
for both frequency acquisition and phase locking, as shown
in Fig. 2. Given fDR = f CK , the proposed BBCDR can
lock in all cases of NSP, ZSP, and PSP. Otherwise, PSP/NSP
increases/decreases VCONT , which corresponds to a “searching”
process in a certain voltage-controlled oscillator (VCO) band,
regardless of the polarity of  f . If we properly change the
VCO band until we find the correct value, the BBCDR will
finally lock at the desired data rate. With the BBCDR locked
stably, we will set the SP to zero for better jitter performance.
III. C IRCUIT I MPLEMENTATION
A. Complete Diagram of the Proposed BBCDR
Fig. 3(a) shows the complete diagram of the proposed
BBCDR to implement the developed principles (Figs. 1 and 2).
Recalling Fig. 1(a), the three SP conditions share the same
flip-flops (FFs), XOR gates, and charge pump (CP). They can
only identify themselves by the phase of CKS . Yet, for the
circuit realization, there are two reasons to introduce additional
hardware [Fig. 3(a)]. First, it is challenging to design a
three-phase clock selector for CK90 /CK180 /CK270 because of
the undesired phase deviation, while the multiplexer (MUX1 )
easily works as the two-phase selector for CK90 /CK270 . Sec-
ond, the clock-to-Q delay causes insufficient time margin for
the two-stage DFFs when CKs = CK270 . Thus, FF9 is inserted
between FF8 and FF10 and triggered by CK180 to entail enough
time margin. Meanwhile, FF3 is also introduced to align the
timing in PSP. In summary, (FF1-2 , FF4-5 ), (FF1-2 , FF6-7 ), and
(FF1-3 , FF8-10 ) are used for ZSP, NSP, and PSP, respectively.
Correspondingly, the XOR / XNOR gates along with the CPs
are also replicated three to match the output of three groups
of FFs.
The proposed BBCDR loop contains two operating modes,
namely, the frequency-acquisition mode (FAM) and phase
acquisition mode (PAM). Functionally, the former drives the
548
Fig. 3. Complete diagram of the proposed single-loop full-rate BBCDR without reference and separate FD, along with its control summary. (b) Its detailed
operation under different modes.
loop to the correct frequency, whereas the latter aims at
recovering clock and retiming data at a specific data rate.
In PAM (i.e., ZSP), besides the clock generator, the loop
consists of FF1,2 , FF4,5 , and CPPAM with the corresponding
XOR / XNOR gates. Though FF3 and FF6-10 are still working,
CP90 and CP270 are turned off by their grounded bias voltage
through MUX5,6 . Therefore, the FAM is inactive, and the
loop exactly operates like a conventional BBCDR loop. Sim-
ilarly, in FAM, the PSP/NSP together with the corresponding
CPs are also operating in the “one-hot” mode, as shown
in Fig. 3(b).
The proposed single-loop full-rate scheme [Fig. 3(a)] uses
a double-tail comparator [31] as an FF to shift and retime
the PAM-4 input by comparing it with the external reference
voltages (VRef,A and VRef,C ) and finally outputs the most
significant bit (MSB) and least significant bit (LSB) data by
the multiplexer-based decoder [32], [33]. The proposed BBPD
generates three groups of three successive samples for ZSP
(S2 , S3 , and S4 ), NSP (S2 , S3 , and S5 ), and PSP (S1 , S2 ,
and S6 ). Thus, the three CPs handle the respective Late/Early
signals to charge/discharge the loop filter (LF). Here, the CPs
based on the dual compensation paths alleviate the mismatch
between the UP and DN currents caused by the channel-length
modulation [19], [34].
An LC-VCO supplies the required clock phases operating
at 2 f Baud followed by a quadrature output divider-by-two,
where f Baud is the baud rate of the input data (the analysis
of these blocks is in Section III-C). Fig. 3(a) (bottom left)
shows the control logic provided by the HCC. Here, MDSW =
0/1 denotes the FAM and PAM state, and plus, the CKS switch
signal (SW) indicates the VCO band switching state, toggling
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022
CKS between CK90 and CK270 by transmission-gate-based
multiplexer [Fig. 3(b)].
Fig. 4 shows the schematic of the HCC to perform the
control algorithm (Figs. 2 and 3) consisting of the VCO
hopping control and mode switch control. The former part
functions as the PSP/NSP controller in FAM. First, SW toggles
only when VCONT crosses VS+ during its uptrend or falls
below VS− during its decline, where VS+ and VS− are the
upper and lower threshold voltages of the Schmitt trigger,
respectively. Whether SW outputs a rising or falling edge, the
successive edge detector delivers a pulse on the band switch
signal (BANDSW), thus triggering the counter to increase and
upshift the VCO band by one. Meanwhile, the hopping SW
switches CKS between CK90 and CK270 , ensuring the reverse
trend for VCONT in the adjacent band. This process continues
until the correct VCO band is found.
The mode switch control assists the BBCDR in switching
between PAM and FAM automatically. Recalling Fig. 1(b),
the proposed BBCDR can lock not only in ZSP, but also in
PSP/NSP. Thus, we identify the locking when VCONT remains
stable longer than a preset time (TPRE ). To realize it, we use a
timer triggered by a f Baud /8192 clock to monitor the locking
state. When the timer overflows, it produces a rising edge on
OVER, leading to a high-level “mode switch” signal (MDSW)
by G3 . At this instant, the loop enters PAM and operates as a
normal BBCDR. TPRE should be longer than the searching time
in any VCO band, thus eliminating incorrect mode switches.
Furthermore, we design the three-input AND gate (G1 ) and
comparators (G4 and G5 ) to restart the FAM. First, when Reset
is low, the switch (G2 ) turns on, pulling down BANDSW,
thereby G1 outputs a low-level MDCLR to reset MDSW,
ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR 549

Fig. 4. Block diagram of the HCCs.

Fig. 5. Operating illustration of frequency and phase acquisition starting from Reset signal.

ensuring the BBCDR begins with FAM. Second, with the
data rate changed after locking the loop (BBCDR operates
in PAM), VCONT may drift out of the allowed range ([VREF− ,
VREF+ ]). Namely, if VCONT > VREF+ or VCONT < VREF− ,
MDCLR will also return to zero, forcing the BBCDR to
enter into the FAM again, since the counter starts over to be
0 after counting up one bit from 7, and we can always find
the correct band. [VS− , VS+ ] is the intrinsic threshold voltage
of the Schmitt trigger, while [VREF− , VREF+ ] is the external
reference voltage for defining the reasonable VCONT range.
From a mathematical perspective, [VS− , VS+ ] is a subset of
[VREF− , VREF+ ].
B. Operating Dynamics
With the hardware described in Section III-A, we exemplify
a typical frequency acquisition and phase tracking process
in Fig. 5, which starts from an active Reset signal. Here,
we extract the involved building blocks from Figs. 3 and 4,
and the sampling relationship refers to that in Fig. 1(b).
At the beginning, phase 1 delivers a negative pulse on
Reset to the 3-bit counter in HCC, thus resetting the VCO
to Band 0. Without loss of generality, we assume that the
initial SW is low and the targeted frequency locates in Band 2.
Once Reset returns to high, the BBCDR enters PSP in FAM,
with CK270 selected as CKS by SW. Thereby, the samples

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550
Fig. 6. (a) Complete algorithm of our BBCDR operation and (b) dynamic acquisition process including all the states.
(S1 , S6 , and S2 ) serve CP270 to deliver more IUP than IDN .
Therefore, the BBCDR searches upwardly in Band 0 (phase 2).
When VCONT climbs to VS+ , the loop enters the first transition
and it functions as follows: 1) the larger-than-VS+ VCONT
toggles the Schmitt trigger, outputting a rising edge on SW;
2) a pulse shows on BANDSW to trigger the VCO band
counter; and 3) the VCO jumps to Band 1 with VCONT holding
on around VS+ . Therefore, in the next step (phase 3), with
CK90 activated, the valid samples change to S2 , S5 , and S3 ,
delivering more IDN than IUP instead. Thus, the BBCDR
searches downward in Band 1. When VCONT falls to VS− , the
NSP-to-PSP transition occurs similar to its reciprocal case.
The falling edge of SW upshifts VCO and restarts the new
upward searching in Band 2 (phase 4). When we finally find
the targeted frequency in Band 2 with a PSP, the average of
VCONT remains stable. When the timer in HCC monitors and
detects that VCONT stays in [VS− , VS+ ] for a time longer than
TPRE , it alarms and generates a pulse on OVER and finally
switches MDSW to the high level (phase 5). At this moment,
the phase of CKS is unconcerned since only CPPAM [Fig. 3(b)]
is on duty. The locking converges to a more stable condition
due to the SP vanishing (phase 6).
Fig. 6(a) shows the detailed control algorithm, among which
Fig. 5 mainly involves the states transitions of RESET to FAM,
SP switching in FAM, and FAM to PAM. Fig. 6(a) shows
the reverse transition paths, especially for the transition from
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022
PAM to FAM, implying the process of the automatic frequency
recapture, which happens when the data rate changes.
Fig. 6(b) shows a process containing the above states
transitions. It consists of two parts, where the preceding one
(t0 –t1 ), beginning with an active Reset signal, is similar to
that in Fig. 5. Differently, at t1 , the input data rate suddenly
changes, the loop loses lock and VCONT drifts out of [VREF− ,
VREF+ ] at t2 (VREF+ = VS+ in this case). Thus, MDCLR
changes to the low level, resetting MDSW and forcing the loop
to enter FAM again. The BBCDR executes another complete
frequency acquisition from t1 to t3 , indicating that we can
reach the re-locking regardless of the initial locking frequency.
C. Design Considerations
Fig. 7 shows the schematic of the quadrature clock scheme.
It consists of a class-B LC VCO operating at 2 f Baud with
an ac-coupled divider-by-two based on a low-power dynamic
latch [35]. The n-type LC VCO uses a 3-bit switched capacitor
to achieve the overall eight bands covering 23.4–29.1 GHz,
consuming 4.2 mW at 28 GHz with a 0.6-V supply, where
C1 = 22.4 fF and the two-turns inductor in the LC tank
features ∼370 pH with the quality factor of 16 at 28 GHz,
occupying 150 × 135 μm2 .
Although our clock-selection scheme requires the quadra-
ture phases at f Baud , the divider-by-two in our design only
occupies 3.3 × 3.4 μm2 and consumes ∼0.8 mW at 28 GHz
ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR
Fig. 7. Schematic of the quadrature clock scheme.
Fig. 8. (a) Details of the Schmitt trigger and (b) its design consideration.
with 1-V supply and 0.45-V common-mode bias voltage
(VCKCM ). Thus, the extra area and power are <0.1% and
<11%, respectively.
The alternative clock scheme is the quadrature LC VCO
operating at f Baud , which needs two larger inductors. The
phase ambiguity in the quadrature LC VCO [36] is unac-
ceptable in the clock-selection scheme because the chosen
phase binds the SP polarity and further affects the frequency
acquisition.
We design the Schmitt trigger [Fig. 8(a)] in the HCC to
eliminate improper band hopping. Considering a VCONT signal
shown in Fig. 8(b), although its overall trend is rising, there is
still up and down in the whole process. When VCONT climbs
near to VS+ , the constant-threshold comparator in [17] may
output multiple edges on SW to increase the VCO band more
than once. The Schmitt trigger ensures that the VCO band
jumps only once due to its hysteresis feature. Meanwhile, M1
[Fig. 8(a)] functions as the threshold-voltage tuner to provide
a proper VCONT range.
D. Simulation Results
Fig. 9 shows the simulation results of the open-loop FD
for the proposed BBCDR and its linear counterpart in [17].
The simulation is conducted under a full-rate structure with
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551
Fig. 9. Comparison of the open-loop FD feature between the proposed PD
and the PD described in [17].
Fig. 10. Comparison of the UP/DN and VCONT signals when the SP is zero,
positive, and negative in the pull-in process if the VCO frequency is slower
than the input data rate.
a 14-Gb/s non-return-to-zero (NRZ) input and a 50-μA CP
current with the SPs in [17] set to ±15 ps for comparison.
Here, we use the pre-layout double-tail-based DFFs along with
the ideal delay cell and clock phases.
We observe that the FD curves of the proposed scheme for
both PSP and NSP are symmetric about the x-axis. It implies
that the strength of the single-side polarity is almost the same
for the two SP conditions. Compared with the topology in [17],
the BBPD shows a wider range (∼4–40 GHz) maintaining
the desired single-sided polarity. Moreover, Iout,av surpasses its
linear counterpart throughout the whole frequency range, indi-
cating the faster acquisition speed for the proposed scheme.
We also perform different input patterns to verify the robust-
ness of the clock-selection scheme.
552 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022

Fig. 11. Negative single-sided polarity comparison when setting (a) f CK = 9.5 GHz and (b) f CK = 8.5 GHz.

Fig. 12. Positive single-sided polarity comparison when setting (a) f CK = 26 GHz and (b) f CK = 28 GHz.

We further compare these two PDs in the closed loop with

a behavioral simulation. Using the same loop parameters [17],
where K VCO = 1 GHz/V, R1 = 1 k, C1 = 1 nF, and C2 =
100 pF, we set the CP current to 500 μA and the SPs in [17]
to ±15 ps. For the simulations (Figs. 10–12), we input a
“0101” pattern at 10 Gb/s. Fig. 10 compares the UP–DN and
VCONT signals in ZSP, PSP, and NSP when we set an initial
f CK to 9 GHz. The single-sided polarity is reversed for [17]
and this work. Hence, we unify the non-ZSP conditions by
the pulling-in direction. Under ZSP, the BBPD shows almost
equal intervals for charging and discharging. The average of
VCONT is almost unchanged, corresponding to the closed-loop Fig. 13. Dynamic process under PSP using the same loop parameter of that
curve in Fig. 1(b). Also, its UP–DN changes only once in a in Fig. 10 when setting the input of a 10-Gb/s PRBS 27 − 1 pattern and the
initial f CK = 19.9 GHz.
cycle slip. Differently, the linear PD generates more pulses
in a cycle slip since  f is in the pull-in range of the linear
PD, it shows a little more charging than discharging, and thus,
the corresponding VCONT gradually climbs up. As for the pull- Fig. 11(a) and (b) shows the processes with an initial f CK of
up case [Fig. 10 (middle)], both PDs output much more UPs 9.5 and 8.5 GHz, respectively. VCONT of BBPD keeps decreas-
than DNs, and therefore, the loop has higher capability of ing in Fig. 11(a) and (b) as desired, while the linear PD fails
charging than discharging the LF. Conversely, the pull-down when f CK = 8.5 GHz. Fig. 12 shows the reciprocal case, where
case [Fig. 10 (bottom)] supplies more DNs to decrease VCONT . the BBPD operates in PSP and the linear PD works in NSP
In the non-ZSP conditions, VCONT from both the PDs shares (see Fig. 9) for an upward searching. At 26-GHz f CK , both
the same trend, but the BBPD always provides a faster pulling- PDs exhibit an increasing VCONT , as shown in Fig. 12(a). How-
in speed, agreeing with Fig. 9. ever, the linear PD fails to maintain the positive single-side
Since the frequency acquisition in the proposed BBCDR polarity at 28-GHz f CK [Fig. 12(b)], indicating that our
and that in [17] relies on the available single-side polarity BBCDR has a wider frequency-capture range.
range, Figs. 11 and 12 show the pull-in process. Recall- A harmonic-locking issue may occur if the variable fre-
ing Fig. 9, the PSP in [17] fails to maintain the negative quency range of the VCO is too large [38], which happens
single-sided polarity at low frequency. With a 10-Gb/s input, with the loop locked to any of the harmonics rather than the

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ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR 553

Fig. 14. Illustration of the harmonic-locking issue in terms of f 1 , f 2 , and Reset signal, where f 1 and f 2 denote the first and second target frequencies,
respectively.

fundamental of the target frequency [39]. Then, the harmonic

locking may also impact the proposed BBPD. Using the loop
parameter in Fig. 10, we simulate a dynamic process under
PSP (Fig. 13), where the input is a 10-Gb/s pseudorandom
binary sequence (PRBS) 27 − 1 pattern, with the initial f CK
set at 19.9 GHz, the loop finally locks at 20 GHz, namely,
the second harmonic of the target frequency. However, there
are mechanisms to weaken its effect. We sketch four cases,
as shown in Fig. 14, assuming that the BBCDR maintains
the single-sided FD polarity over the frequency range of
interest. At t1 , the loop locks at f 1 , with the data rate changed
at t2 . Since the harmonic frequency also changes with the
input data rate, as long as f 2 > f 1 , the harmonic-locking
issue will not affect the loop [Fig. 14(a) and (b)]. Yet, when
f 2 < f 1 , the loop will lock at the frequency of 2 f 2 , which
is not desirable, as shown in Fig. 14(c). To avoid it, if we
reset the loop at t2 , the VCO will return to its lowest band Fig. 15. Dynamic process with 2.9× frequency variation based on the same
and starting a new frequency-acquisition process [Fig. 14(d)]. loop parameter of that in Fig. 10 with 100-μA CP current.
Finally, the hunt of the correct frequency will start.
To assess the frequency-acquisition ability, we develop a
5-bit VCO model and VCO hopping control logic (see To examine the effect of the input data randomness,
Figs. 4 and 6) in MATLAB/Simulink to support a wide-range Fig. 16 shows the simulated dynamic processes under PRBS
frequency acquisition and to eliminate the limitation of the 27 − 1, 215 − 1, and 231 − 1. Here, we use the same loop
real VCO. We conduct a behavioral simulation, as shown parameters of Fig. 10 with 100-μA CP current, where we set
in Fig. 15, where we set the initial f CK at 7.8 GHz by the the initial and target frequency to 7.8 and 12 GHz, respectively.
negative pulse of Reset. While we input a 22.5-Gb/s PRBS With the same Reset, we obtain the fastest process under PRBS
27 − 1 to obtain a 2.9× frequency variation from the initial 27 − 1, while the slowest results from PRBS 231 − 1, which
f CK to the target frequency. The BBCDR loop searches from verifies the robustness of the proposed BBCDR in terms of
Band 0 to Band 21 and finally locks at 22.5 GHz. the input randomness.

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554
Fig. 16. Dynamic processes under the PRBS 27 − 1, 215 − 1, and
231 − 1 patterns.
Fig. 17. (a) Chip micrograph with area and power breakdown. (b) PAM-4 eye
diagram of the sub-block (E) by performing the post-layout simulation.
IV. M EASUREMENT R ESULTS
Fig. 17(a) shows the chip photograph along with the area
and power breakdown of the proposed BBCDR fabricated
in a 28-nm CMOS. The VCO is characterized by a 0.6-V
supply and other sub-blocks are powered by a 1.2-V supply.
Occupying a 0.0285-mm2 core area, the proposed prototype
dissipates 19.16 mW at 28 Gb/s, excluding the 27 − 1 PRBS
pattern generator (E) and the test buffers (F1,2 ). The addi-
tional hardware for the frequency acquisition only occupies
0.0006 mm2 (2.1%) and consumes ∼8 mW (41.8%). In this
design, we perform a similar testing platform [33] and use
the bit error ratio tester (BERT) to provide the half baud rate
clock for an on-chip PAM-4 generator with a 27 − 1 PRBS.
Fig. 17(b) shows the 28-Gb/s eye diagram of the PAM-4
input obtained from 1-μs post-layout simulation, including
the effect of the on-chip metal trace and load capacitors. The
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022
peak-to-peak swing of the PAM-4 input is 1.43 Vppd and the
horizontal eye opening is 61.38 ps.
A. Performance Assessment
To assess the settling process, we first examine the case
starting from the Reset signal. From Fig. 18(a), initially,
the proposed BBCDR locked at 26 Gb/s corresponds to the
VCO Band 4 (where Band 0 is the lowest and Band 7 is
the highest). At t0 , Reset is active, and the loop starts to
unlock. Then, Reset goes high at t1 , activating FAM and
VCONT wanders between VS+ and VS− to search for the desired
frequency. After 2.052 μs, with Band 4 hunted, the loop locks
at t2 . When the timer overflows at t3 , MDSW goes high and the
PAM takes over, while further suppresses the voltage ripple on
VCONT . Fig. 18(a) (bottom) shows the time-domain dynamic
variation of f VCO . To further illustrate the acquisition behavior,
Fig. 18(b) shows the corresponding frequency traveling route
in the overall VCO tuning range. At t0 , the frequency drops
sharply from Band 4 to Band 0 due to the active-low Reset
signal. Once VCONT climbs to VS+ for the first time, the
VCO band does not jump to Band 1 because Reset is still
active until t1 . Then, f VCO moves up in a zigzag manner
alongside each VCO band. Finally, at t2 , we re-reach the
targeted frequency.
Fig. 19 shows the second settling process (Dynamic II).
The dynamic process begins with NSP at t0 and locks in
PSP in Band 6 at t2 , indicating that the proposed BBCDR
can lock regardless of the initial or final SP polarity. When
comparing it to Dynamic I in Fig. 18, we can conclude
that the initial SW level dominates the initial SP, while the
number of bands jumped before locking determines the ended
SP polarity.
Fig. 20(a) shows the third dynamic process which jumps
from one band to another without a Reset signal, verifying
the frequency recapture [Fig. 6(b)]. Initially, the BBCDR
locks at 27.8 Gb/s in Band 6 until the data rate suddenly
drops to 25.2 Gb/s at t0 . Consequently, the loop loses lock-
ing and VCONT drifts up gradually, reaching VREF+ at t1 .
At this moment, we reset MDCLR to zero with the gate (G1 )
(Fig. 4), outputting a low-level MDSW, indicating that the
BBCDR switches to FAM and searches for the new frequency.
On account of finding the targeted frequency in Bands 6 and 7,
a new round acquisition starts at t2 , leading to the re-locking
at t3 and entering PAM at t4 . Fig. 20(b) shows the frequency-
domain searching process. With the cyclical counter in HCC
(Fig. 4), the proposed BBCDR can always find the tar-
geted frequency regardless of the polarity of the data-rate
difference.
Fig. 21 shows the acquisition speed versus the bias of the
CP in FAM. At the highlighted point in Band 7, the initial data
rate is 23.45 Gb/s, while the target data rate is 28.6 Gb/s, and
the CP bias (VCP_FAM ) is 0.75 V. Because the unbalanced CP
current would change with the real-time frequency difference,
the frequency acquisition speed here is an average value. The
acquisition time becomes shorter when VCP_FAM rises in each
band due to the larger loop bandwidth. Furthermore, we obtain
all the results with a 0.32-V fixed VCP_PAM . It implies that the
ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR 555

Fig. 18. (a) Measured dynamic process which starts from the Reset state, ends in NSP, and locks in Band 4. (b) Corresponding frequency traveling route
along with the overall VCO tuning range.

Fig. 19. (a) Measured dynamic process which starts from the Reset state, ends in PSP, and locks in Band 6. (b) Corresponding frequency traveling route
along with the overall VCO tuning range.

acceleration of locking consumes no extra power in the PAM
and exhibits robustness for the mode switch between the FAM
and the PAM when varying the CP voltage bias.
Fig. 22 shows the VCONT comparison between FAM and
PAM in two cases. The first is at 24.16 Gb/s in Band 1 with
0.61-V VCP_FAM and 0.39-V VCP_PAM . The time-domain wave-
form [Fig. 22(a)] intuitively suggests that VCONT under PAM
is steadier than that in FAM. We perform a statistical analysis
in both FAM and PAM and obtain the VCONT histogram
[Fig. 22(b)]. VCONT under PAM concentrates more on its
median with less variance of 2.19 × 10−5 V2 . We extract the
other case from a dynamic at 24.8 Gb/s in Band 2 [Fig. 22(c)],
where the voltage bias difference is 0.4 V between FAM and
PAM. The VCONT variance under PAM is also less than half
of that in FAM [Fig. 22(d)]. These results prove a better jitter
performance when disabling the deliberate SP.
Entering the PAM, we further measure the other jitter-
related performance of the BBCDR. Fig. 23(a) shows the
retimed MSB/LSB data and recovered clock at 28 Gb/s. The
histogram of the recovered clock shows a standard devia-
tion of 789.3 fs, including the 270.6-fs standard deviation
jitter of the data-homologous trigger signal [Fig. 23(b)].
Fig. 23(c) and (d) shows the spectrum and phase noise of the
14-GHz recovered clock, respectively. The integrated jitter

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556
Fig. 20. (a) Measured dynamic process which starts from Band 6 in locking state, ends in PSP, and re-locks in Band 3. (b) Corresponding frequency traveling
route along with the overall VCO tuning range.
Fig. 21. Acquisition speed versus the CP bias (VCP_FAM ) in each band.
Fig. 22. Comparison of the steady VCONT in (a) Band 1 and (b) Band 2 and
the corresponding histogram in (c) Band 1 and (d) Band 2.
is 486.8 fsrms from 100 Hz to 1 GHz, including the data-
dependent spurs.
We also measure the jitter specifications under PAM, i.e.,
the jitter transfer function (JTF) and the jitter tolerance
(JTOL) [37]. A 0.2-UIpp jitter injection from the BERT
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022
Fig. 23. (a) Retimed data and recovered clock eyes. (b) Histogram of the
recovered clock along with the data-homologous trigger signal. (c) Recovered
clock spectrum. (d) Phase noise of the recovered clock. All the results are
obtained by supplying a 28-Gb/s PAM-4 input pattern.
(Keysight M8040A) assesses JTF, exhibiting a bandwidth of
∼12 MHz [Fig. 24(a)]. Here, we input the modulated jitter
for the JTOL assessment before the frequency acquisition.
Fig. 24(b) shows the measured JTOL curve, which achieves
0.41- and 0.4-UIPP out-of-band tolerance for MSB and LSB
data with 27 − 1 PRBS PAM-4 input, respectively.
B. Robustness Verification
To verify the long-term robustness, such as the slow fre-
quency drift, we measure the spectrum and spectrogram at
14 GHz using the N9040B signal analyzer. From Fig. 25,
we carried out the measurement continuously for more than
8 min, selecting the maximum-hold mode for the spectrum
collection. During the total test time, the spectrum peak only
appears at 14 GHz as desired, indicating that there is no
frequency drift.
ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR
Fig. 24. Measured (a) JTF and (b) JTOL with a 28-Gb/s PAM-4 input.
Fig. 25. Spectrum and spectrogram of the clock locking at 14 GHz.
To further assess the impact of the jittery input data on
the frequency acquisition, we supplement the measurements
(Figs. 26–30), of which Figs. 26 and 27 show the jitter
injection method along with the loop behavior at low f jitter
with a small Ajitter . Here, f jitter and Ajitter denote the jitter
frequency in Hz and peak-to-peak jitter amplitude in UIPP ,
respectively.
Utilizing the on-chip PRBS 27 − 1 generator, we determine
the data rate and jitter of the PAM-4 input data with its
input clock, supplied by the off-chip Keysight M8040A. From
Fig. 26(a), we modulate a 100-kHz, 0.2-UIPP sinusoidal jitter
on the half-baud-rate input clock with a 5.17-ps standard
deviation. The same jitter will also appear on the PAM-4
input. Fig. 26(b) and (c) shows the corresponding dynamic
process and spectrum of the recovered clock, respectively.
Since the BBCDR well tracks the in-band noise, the spectrum
[Fig. 26(c)] shows spurs spaced by 100 kHz around the center
frequency at 13.8 GHz. Fig. 27 shows the case under a
1-MHz f jitter with a 0.4-UIPP Ajitter . Here, the spurs [Fig. 27(c)]
are spaced by 1 MHz instead. In Fig 27(a), the standard
deviation is double when comparing it with the case in Fig. 26.
In addition, the steady VCONT [Fig. 27(b)] exhibits a larger
ripple due to the increased jitter amplitude.
Fig. 28 shows the measurements under higher f jitter with
a considerable Ajitter . With a 5-MHz, 0.5-UIPP jitter injec-
tion, Fig. 28(a) shows the corresponding dynamic process.
Recalling the JTF in Fig. 24(a), the bandwidth of the pro-
posed BBCDR is ∼12 MHz under a 0.2-UIPP jitter injection.
Therefore, the 5-MHz jitter would be well-tracked by the loop.
We can observe a sinusoidal ripple with the frequency of f jitter
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557
on VCONT under the PAM. [Fig. 28(a)] (phenomenon detailed
later). Fig. 28(c)–(f) shows the dynamic processes and spectra
with 100-MHz f jitter , which is out of the loop bandwidth and
thus will be attenuated by the loop. As a result, the spurs in
the spectra and ripples on VCONT are smaller than those in the
lower f jitter cases (see Figs. 26 and 27).
Ajitter in Fig. 28(e) and (f) slightly exceeds JTOL at
100 MHz. Thus, the dynamics show a two-phase process.
In Phase I, if there is no jitter injection, the loop should lock
at t1 , Yet, the 0.42-UIPP jitter injection unlocks the loop. At t2 ,
when VCONT exceeds VREF+ , the loop returns to the NSP to
start another frequency-acquisition process in Phase II and
finally locks at t3 . The spectrum [Fig. 28(f)] exhibits a terrible
phase noise and will go out of lock. The above phenomena
imply that the loop operates at the critical point of normal and
abnormal.
For a quantitative analysis, we derive the ripple on VCONT
due to the sinusoidal input jitter. Assume that the input clock
only includes the desired carrier signal and the sinusoidal jitter.
The excess phase of the input clock becomes
 
S Jφ (t) = A P sin 2π fjitter t + ϕ0 (1)
where A P denotes the amplitude of the sinusoidal jitter in rad
and is equal to π Ajitter and ϕ0 is the initial phase. Without
loss of generality, we set ϕ0 to 0 in the following derivation.
The excess phase (SJ ) will lead to a frequency fluctuation
( f FLUC ) since the frequency is the derivative of the phase
d S Jφ (t)  
f FLUC = /2π = π f jitter Ajitter cos 2π f jitter t . (2)
dt
Provided a constant A P , (2) indicates that the higher f jitter
injected, the larger f FLUC will be present. Considering the gain
(K VCO ) of the VCO, the fluctuation on VCONT is
 
fFLUC π f jitter Ajitter cos 2π f jitter t
VCONT,FLUC = = . (3)
K VCO K VCO
Therefore, the amplitude of the VCONT fluctuation is
π f jitter Ajitter
AVC,FLUC = . (4)
K VCO
The measurements (Figs. 29 and 30) verify the above
derivation. With a ∼0.6-GHz/V K VCO , the calculated AVC,FLUC
is 52.4 mV based on (4). From Fig. 29(c), we measure the
zoomed-in VCONT with the active probe of a Keysight real-time
oscilloscope (DSAV334A), and it shows a 59.2-mV AVC,FLUC ,
which includes the impact of the sinusoidal jitter, random jitter,
and so on.
In Fig. 30, we enlarge f jitter by ten times when comparing
with Fig. 29, while Ajitter decreases from 1000 to 100 UIPP .
Based on (4), AVC,FLUC remains unchanged. The measure-
ments [Fig. 30(c)] show a 59.5-mV AVC,FLUC , which is almost
the same as in Fig. 29 as desired.
Table I benchmarks our work with prior arts [5], [17], [19],
[22], [23]. Regarding the power, Huang et al. [17] used
current-mode-logic circuits to tune the delay on the high-
speed data path and suffers from 1.8-V VDD in a 180-nm
CMOS. Park et al. [19] needed a 4× oversampling ratio, thus
consuming 18 mW in both the high-speed clock path and bang-
bang phase/FD at 10 Gb/s. In [23], the synthesized digital
558 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 2, FEBRUARY 2022

Fig. 26. (a) Measured jitter histogram of the data-homologous input clock, (b) dynamic process, and (c) recovered clock under 0.2-UIPP , 100-kHz sinusoidal
jitter injection at 27.6 Gb/s in Band 6.

Fig. 27. (a) Measured jitter histogram of the data-homologous input clock, (b) dynamic process, and (c) recovered clock under 0.4-UIPP , 1-MHz sinusoidal
jitter injection at 27.6 Gb/s in Band 6.

Fig. 28. Measured dynamic processes and spectra of the recovered clock at 27.6 Gb/s in Band 6. (a) and (b) f jitter = 5 MHz and Ajitter = 0.5 UIPP . (c) and
(d) f jitter = 100 MHz and Ajitter = 0.25 UIPP . (e) and (f) f jitter = 100 MHz and Ajitter = 0.42 UIPP .

core and VCO consume 34.08 and 14.47 mW in a 28-nm
CMOS at 32 Gb/s, respectively, whereas in [5], only the FD
logic and delay line consume 11 and 6.6 mW, respectively.
Shu et al. [22] employed three loops in the overall CDR:
1) the multiplying delay-locked loop with a digitally controlled
delay line; 2) the frequency-locking loop; and 3) the phase-
locked loop, which consumes a total power of 15.3 mW.
In the proposed design, the VCO core and divider-by-two
[35] draw 4.2 and 0.8 mW at 28 Gb/s, respectively. The
balanced-threshold phase detection scheme for the PAM-4
signal [32], [33] reduces the number of high-speed
DFFs by ∼2/3. Furthermore, the multiplexer-based LSB
decoder [32], [33] only draws tens of nano-watt of power.
Although we add an HCC to facilitate the frequency and phase
acquisition, it only handles low-speed signals at several MHz
and consumes 1.9 mW in 0.0001 mm2 . The inductor in the
LC-VCO and the second-order LF occupy most of the core
area. As a result, this work shows better energy (>3.3×)
and area (>1.6×) efficiencies for recovering the clock from
PAM-4 data with a 3× oversampling ratio.

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ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR 559

Fig. 29. Measured (a) spectrum, (b) dynamic process, and (c) zoomed-in VCONT after locking under 1000-UIPP , 10-kHz sinusoidal jitter injection at 27.6 Gb/s
in Band 6.

Fig. 30. Measured (a) spectrum, (b) dynamic process, and (c) zoomed-in VCONT after locking under 100-UIPP , 100-kHz sinusoidal jitter injection at 27.6 Gb/s
in Band 6.
TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON W ITH S TATE OF THE A RT

In view of the acquisition speed, Huang et al. [17] used a
5-bit VCO to search the overall frequency range by jump-
ing the 31 SPs. It cannot set a too large SP; otherwise,
it loses the locking. Thus, the single-sided polarity is weaker
than that in the proposed design (Figs. 9–12), leading to a
longer acquisition time. While the frequency detection logic
in [22] and [23] requires an accumulation for the Fast/Slow
signals, they take a longer acquisition time. In this work,
the strong single-sided polarity and a 3-bit VCO contribute
to a fast acquisition speed of 8.2 Gb/s/μs for a data-rate
jump of 5.15 Gb/s, which is at least 8.1× faster than
recent art.
V. C ONCLUSION
This article presented a full-rate PAM-4 BBCDR without
the reference and the separate FD. Combining the deliber-
ately inserted SPs and HCC, the proposed BBCDR realized
fast and robust frequency acquisition in a true single loop.
Designed in 28-nm CMOS, the proposed prototype mea-
sured a 23-to-29-Gb/s data rate with an acquisition speed

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560
of 8.2 Gb/s/μs. Occupying a core area of 0.0285 mm2 ,
it scored a 0.68-pJ/bit energy efficiency at 28 Gb/s and
0.4-UIPP JTOL at 200-MHz jitter frequency, favorably com-
paring with the recent CDRs that support only the NRZ data
stream.
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ZHAO et al.: 0.0285-mm2 0.68-pJ/bit SINGLE-LOOP FULL-RATE BANG-BANG CDR
Xiaoteng Zhao (Student Member, IEEE) received
the B.Eng. degree in integrated circuit design and
integration system from Xidian University, Xi’an,
Shaanxi, China, in 2014, and the M.Eng. degree in
integrated circuit engineering from the University
of Chinese Academy of Sciences, Beijing, China,
in 2017. He is currently pursuing the Ph.D. degree
with the State-Key Laboratory of Analog and Mixed-
Signal VLSI (AMSV), University of Macau, Macau,
China.
His research interests are focused on the high-
speed wireline backplane transceiver design.
Yong Chen (Senior Member, IEEE) received
the B.Eng. degree in electronic and information
engineering, Communication University of China
(CUC), Beijing, China, in 2005, and the Ph.D.
degree in microelectronics and solid-state electron-
ics from the Institute of Microelectronics, Chinese
Academy of Sciences (IMECAS), Beijing, in 2010.
From 2010 to 2013, he worked as a Post-
Doctoral Researcher at the Institute of Microelec-
tronics, Tsinghua University, Beijing. From 2013 to
2016, he was a Research Fellow at VIRTUS/EEE,
Nanyang Technological University, Singapore. He has been an Assistant
Professor with the State Key Laboratory of Analog and Mixed-Signal VLSI
(AMSV), University of Macau, Macao, China, since March 2016. His
research interests include integrated circuit designs involving analog/mixed-
signal/RF/millimeter-wave/sub-terahertz/wireline.
Dr. Chen was a recipient of the “Haixi” (three places across the Straits)
postgraduate integrated circuit design competition (Second Prize) in 2009.
He was a co-recipient of the Best Paper Award at the IEEE Asia Pacific Con-
ference on Circuits and Systems (APCCAS) in 2019, the Best Student Paper
Award (Third Place) at the IEEE Radio Frequency Integrated Circuits (RFIC)
Symposium in 2021, and the Macao Science and Technology Invention
Award (First Prize) in 2020. His team reported three chip inventions at the
IEEE International Solid-State Circuits Conference (ISSCC; Chip Olympics):
mm-wave PLL 2019, VCO 2019, and radio frequency VCO 2021. He has
been serving as an Associate Editor for IEEE T RANSACTIONS ON V ERY
L ARGE S CALE I NTEGRATION (TVLSI) S YSTEMS since 2019, IEEE A CCESS
since 2019, and IET Electronics Letters (EL) since 2020, an Editor of
International Journal of Circuit Theory and Applications (IJCTA) since
2020, and a Guest Editor of IEEE T RANSACTIONS ON C IRCUITS AND
S YSTEMS —II: E XPRESS B RIEFS since 2021. He serves as the Vice-Chair
from 2019 and 2021 and the Chair for the term 2021–2023 of IEEE
Macau CAS Chapter. He was the Tutorial Chair of ICCS in 2020, a Con-
ference Local Organization Committee Member of Asian Solid-State Cir-
cuits Conference (A-SSCC) in 2019, a member of the IEEE Circuits and
Systems Society, Circuits and Systems for Communications (CASCOM)
Technical Committee for the term 2020–2021, a member of the Technical
Program Committee (TPC) of A-SSCC in 2021, APCCAS for the term
2019–2021, ICTA for the term 2020–2021, NorCAS for the term 2020–2021,
ICECS in 2021, and ICSICT in 2020, a Review Committee Member of ISCAS
in 2021, and the TPC Co-Chair of ICCS in 2021.
Pui-In Mak (Fellow, IEEE) received the Ph.D.
degree from the University of Macau (UM), Macao,
China, in 2006.
He is currently a Full Professor at the Depart-
ment of Electrical and Computer Engineering,
Faculty of Science and Technology, and the Asso-
ciate Director (Research) at the UM Institute
of Microelectronics and State Key Laboratory of
Analog and Mixed-Signal VLSI, UM. His research
interests are on analog and radio frequency (RF) cir-
cuits and systems for wireless and multidisciplinary
innovations.
Dr. Mak has been a fellow of U.K. Institution of Engineering and Technol-
ogy (IET) for contributions to engineering research, education, and services
since 2018, the IEEE for contributions to radio frequency and analog circuits
since 2019, and U.K. Royal Society of Chemistry since 2020. His involve-
ments with IEEE are as follows: an Editorial Board Member of IEEE Press
from 2014 to 2016, a member of Board of Governors of the IEEE Circuits
and Systems Society from 2009 to 2011, a Senior Editor of IEEE J OURNAL
ON E MERGING AND S ELECTED T OPICS IN C IRCUITS AND S YSTEMS from
2014 to 2015, and an Associate Editor of IEEE J OURNAL OF S OLID -S TATE
C IRCUITS since 2018, IEEE S OLID -S TATE C IRCUITS L ETTERS since 2017,
Authorized licensed use limited to: Inha University. Downloaded on February 07,2023 at 11:42:23 UTC from IEEE Xplore. Restrictions apply.
561
IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —I: R EGULAR PAPERS
from 2010 to 2011 and from 2014 to 2015, and IEEE T RANSACTIONS
ON C IRCUITS AND S YSTEMS —II: E XPRESS B RIEFS from 2010 to 2013.
He is/was the TPC Vice Co-Chair of ASP-DAC in 2016, a TPC Member
of Asian Solid-State Circuits Conference (A-SSCC) from 2013 to 2016 and
in 2019, European Solid-State Circuits Conference (ESSCIRC) from 2016 to
2017, and International Solid-State Circuits Conference (ISSCC) from 2017 to
2019). He is/was a Distinguished Lecturer of the IEEE Circuits and Systems
Society from 14 to 15 and the IEEE Solid-State Circuits Society from 2017
to 2018. He was the Chairman of the Distinguished Lecturer Program of
IEEE Circuits and Systems Society from 2018 to 2019. He (co)-received the
DAC/ISSCC Student Paper Award in 2005, the CASS Outstanding Young
Author Award in 2010, the National Scientific and Technological Progress
Award in 2011, the Best Associate Editor of IEEE T RANSACTIONS ON
C IRCUITS AND S YSTEMS —II: E XPRESS B RIEFS from 2012 to 2013, the A-
SSCC Distinguished Design Award in 2015, and the ISSCC Silkroad Award in
2016. In 2005, he was decorated with the Honorary Title of Value for scientific
merits by the Macau Government. He has been inducted as an Overseas Expert
of the Chinese Academy of Sciences since 2018.
Rui P. Martins (Fellow, IEEE) was born in
April 1957. He received the bachelor’s, master’s,
Ph.D., and the Habilitation for Full-Professor
degrees in electrical engineering and computer
science from the Department of Electrical and Com-
puter Engineering (DECE), Instituto Superior Téc-
nico (IST), University of Lisbon, Lisbon, Portugal,
in 1980, 1985, 1992, and 2001, respectively.
He has been with the DECE/IST, University of
Lisbon, since October 1980. Since October 1992, has
been on leave from the University of Lisbon and the
DECE, Faculty of Science and Technology (FST), University of Macau (UM),
Macao, China, where he is a Chair-Professor since August 2013. In FST,
he was Dean from 1994 to 1997 and has been a Vice-Rector of UM since
September 1997. From September 2008 to August 2018, he was a Vice-Rector
of Research, and from September 2018 to August 2023, he was a Vice-Rector
of Global Affairs. He created in 2003 the Analog and Mixed-Signal VLSI
Research Laboratory of UM, elevated in January 2011 to the State Key
Laboratory (SKLAB) of China (the first in Engineering in Macao), being its
Founding Director. He was the Founding Chair of UMTEC (UM company)
from January 2009 to March 2019, supporting the incubation and creation
in 2018 of Digifluidic, the first UM spin-off, whose CEO is a SKLAB Ph.D.
graduate. He was a Co-Founder of Chipidea Microelectronics [later Synopsys-
Macao], Macao, from 2001 to 2002. Within the scope of his teaching and
research activities, he has taught 21 bachelor and master courses and, in UM,
has supervised (or cosupervised) 47 theses, Ph.D. (26) and masters (21).
He has authored or coauthored eight books and 12 book chapters; 48 patents,
USA (38), Taiwan (3), an China (7); 628 papers, in scientific journals (263)
and conference proceedings (365); and other 69 academic works, in a total
of 765 publications.
Dr. Martins was a member of the IEEE CASS Fellow Evaluation Com-
mittee (2013, 2014, 2018—Chair and 2019, 2021, and 2022—Vice-Chair),
the IEEE Nominating Committee of Division I Director (CASS/EDS/SSCS)
(2014), and the IEEE CASS Nominations Committee from 2016 to 2017.
He received two Macao Government decorations: the Medal of Professional
Merit (Portuguese 1999) and the Honorary Title of Value (Chinese 2001).
In July 2010, he was elected, unanimously, as a Corresponding Member of
the Lisbon Academy of Sciences, being the only Portuguese Academician
working and living in Asia. He was the Founding Chair of the IEEE Macau
Section from 2003 to 2005 and the IEEE Macau Joint-Chapter on Circuits
and Systems (CAS)/Communications (COM) from 2005 to 2008) [2009 World
Chapter of the Year of IEEE CAS Society (CASS)], the General Chair of the
IEEE Asia-Pacific Conference on CAS (APCCAS 2008), the Vice-President
(VP) of Region 10 (Asia, Australia, and Pacific) from 2009 to 2011, and
VP-World Regional Activities and Membership of IEEE CASS from 2012 to
2013. He was an Associate Editor of IEEE T RANSACTIONS ON C IRCUITS
AND S YSTEMS —II: E XPRESS B RIEFS from 2010 to 2013, nominated Best
Associate Editor for the term 2012–2013. He was the General Chair of the
ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC
2016), receiving the IEEE Council on Electronic Design Automation (CEDA)
Outstanding Service Award in 2016, and the General Chair of the IEEE Asian
Solid-State Circuits Conference (A-SSCC 2019). He was the Vice-President
from 2005 to 2014 and the President from 2014 to 2017 of the Association
of Portuguese Speaking Universities (AULP).