This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2020.3008777, IEEE
Transactions on Circuits and Systems II: Express Briefs
A 5-Gb/s Adaptive Digital CDR Circuit with
SSC Capability and Enhanced High-Frequency
Jitter Tolerance
Shun-Chi Chang and Shen-Iuan Liu, Fellow, IEEE
 In this brief, the integral gain KI of a DLF is adjusted instead
Abstract—A 5-Gb/s digital clock/data recovery (DCDR) circuit
with spread-spectrum clocking (SSC) capability and enhanced
high-frequency jitter tolerance (JTOL) is presented. To track
input data with both the frequency offset and the SSC, an integral
gain controller is used to adjust an integral gain of the digital loop
filter. It enhances the high-frequency JTOL. This DCDR circuit is
fabricated in 40nm CMOS process. Its active area is 0.022mm2
and the power consumption is 9.9mW from a 1 V supply. With a
5-Gb/s PRBS of 27-1, the measured rms jitter of the retimed data
is 9.47ps. For input data with the frequency offset of ±300ppm and
SSC of -5000ppm, the measured minimum high-frequency JTOL
is equal to 0.55 UIpp by using the proposed integral gain controller
with a bit error rate (BER) <10-12.
Index Terms—Clock and data recovery, spread-spectrum
clocking, phase interpolator, high-frequency, jitter tolerance.
I. INTRODUCTION
C LOCK and data recovery (CDR) circuits are widely used
to recover the clock and retime the data for various
high-speed data transceivers. To suppress the electromagnetic
interference, a spread-spectrum clocking (SSC) [1,2] is usually
used in the high-speed data transceivers. The SSC normally has
a 30 kHz triangular profile with a frequency deviation between
0 and -5000 ppm [1]. For the data with both the frequency
offset and the SSC, the CDR circuit has to track these frequency
errors. The corresponding phase/frequency error will decrease
the data sampling timing margin and degrade the jitter tolerance
(JTOL) of the CDR circuit.
To enhance the JTOL, several methods are presented in
literature [3]-[5]. The loop gain [3,4] of a CDR circuit is
adaptively adjusted to improve the JTOL. While the loop gain
is altered, the 3dB corner frequency of the JTOL will not be
fixed. In addition, the data with SSC are not considered in [3,4].
For a digital CDR (DCDR) circuit, when the proportional gain
of the digital loop filter (DLF) rises, its loop gain is increased. It
increases the hunting jitter [6] and the high-frequency JTOL
degrades. On the contrary, if one reduces the proportional gain,
its loop gain is decreased and the low-frequency JTOL
degrades due to an insufficient phase/frequency tracking
capability. Although the DCDR circuits [5] can track a large
frequency error caused by both the frequency offset and the
SSC, a high-speed clock frequency (e.g. ≥ 2 GHz) is required
for the DLF. It may consume a large power [7] and is difficult
to synthesize the DLF by using a standard cell library.
The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei,
10617, Taiwan (e-mail: lsi@ntu.edu.tw).
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of the proportional gain KP. A DCDR circuit uses an adaptive
KI controller to track the 5-Gb/s data with the frequency offset
of ±300 ppm and the frequency deviation of -5000 ppm caused
by SSC. When the frequency or phase error between the data
and the recovered clock becomes large, the sequences with
consecutive early or late signals will occur at the bang-bang
phase detector (BBPD) output. For a timing interval, the length,
L, of the longest consecutive early signals and the summation,
SON, of the occurrence number of first three longest
consecutive early signals with the lengths of L-k (k = 0, 1, 2)
are recorded and compared. By reducing both L and SON, the
KI controller is used to adjust KI to reduce the phase error [8].
When the phase error between the data and the recovered clock
is reduced, the high-frequency JTOL of the DCDR circuit will
be enhanced. Besides, the clock frequency of this KI controller
can be further reduced to save the power in this work.
This brief is organized as follows. The circuit description is
given in Section II. The experimental results are presented in
Section III. The conclusions are given in Section IV.
II. CIRCUIT DESCRIPTION
A. DCDR
Fig. 1 shows the proposed DCDR circuit using the KI
controller. This DCDR circuit consists of two data/edge
samplers, a 2:16 demultiplexer, a BBPD logic, a majority
voting (MV) circuit [9], a first-order DLF, a phase interpolator
(PI) and a PI controller, a divide-by-2 divider, a low-pass filter
(LPF), and the KI controller. This DCDR circuit works as
follows. The data/edge samplers clocked by the full-rate
recovered clock CKREC sample the input data. The resulting
data and edge samples are demultiplexed to 16 samples and
aligned by using a 2:16 demultiplexer. A binary-tree structure
[10] is adopted here to reduce the power consumption. The
BBPD logic generates totally 8 early/late/hold signals [9]. The
MV circuit converts the 8 early/late/hold (+1/-1/0) signals into
a code MV[1:0] as 10, 01, and 00, respectively. The first-order
DLF and the PI controller update the phase control code of the
PI to adjust the phase of CKREC to align with input data. The PI
controller is composed of an accumulator and a decoder. For
the PI, the quadrature clocks are generated by a divide-by-2
divider, a LPF, and an external clock of 10GHz. The BBPD
logic circuit, the MV circuit, the DLF, the PI controller, and the
KI controller are synthesized by using a standard cell library.
The parameters of the DCDR circuits can be determined
from the 3dB corner frequency of the JTOL and the maximum
frequency tracking range (MFTR) requirement due to SSC. The
3dB corner frequency f3dB of the JTOL can be derived similarly
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Transactions on Circuits and Systems II: Express Briefs

CKREC DLF
PI Controller
KP
Data
(5-Gb/s)
Data/Edge D 2:16 BBPD Majority MV[1:0] z-1 Decoder
Phase
E
Samplers Demux 16 Logic 16 Voting 2 1-z-1 4 16 Interpolator
KI z-1 Accumulator
MV[1] 1-z-1 OINT CK0,90,180,270
MV[1:0] Integrator
CKDIG
early 10 /8 KI Controller 10GHz Clock /2 LPF
CKSSC 4
late 01
hold 00
Recovered Clock (CKREC)
Fig. 1. The proposed DCDR circuit using the KI controller.
Code Controller (CC)
ENCC 1st state 2nd state 1st state 2nd state
L[5:0] DCDR Detect Adjust DCDR Detect Adjust
settles Sequence KI settles Sequence KI
1:2 SON[14:0]
MV[1] Sequence Digital CMP PO
Demux 2 Detector Comparator UP/DN
Lpre[5:0] 1 CKSSC
Counter KI [6:0]
0
SONpre[14:0] TSSC
D Q
ENCC
CKDIG /2 POpre
15*TSSC 15*TSSC TSSC 15*TSSC 15*TSSC TSSC
CKSSC

(a)
Fig. 2. The (a) KI controller and (b) its timing diagram.
TABLE I PARAMETERS
Data rate
Clock frequency in the receiver
SSC Frequency deviation
Frequency offset in percentage ∆f/f
Demultiplexer ratio DR
Clock Frequency of DLF fDIG
Proportional gain KP
Phase step of PI KPI
Latency z-D
with [11] and given as
K P  K PI  f DIG
f3dB 
2
The KPI is the phase step of the PI in the unit of UI/code where
UI represents a unit interval and fDIG is the clock frequency of
DLF. Note that (1) is correct for the proposed DCDR circuit
with a PRBS of 27-1. The 3dB corner frequency of the JTOL is
determined by KP instead of KI and the s-domain approximation
is used in the derivation assuming the f3dB is much less than fDIG.
The maximum frequency tracking range (MFTR) of the
DCDR circuit is expressed as [5]
MFTR | DR  OINT ,max  K PI | 5600 ppm
where OINT,max is the maximum output of the integral path, and
DR is the demultiplexer ratio. Note that the DCDR circuit
tracks the maximum frequency error of 5600 ppm including a
600 ppm frequency offset and a 5000 ppm frequency deviation
caused by SSC.
Based on the (1) and (2), the parameters for this DCDR
circuit is determined as follows. To ensure the loop stability, KP
should be much larger than KI. In this work, KP is equal to 1/4
and KI is adjusted from 1/64 to 1/4096. To have an adequate
timing margin for the DLF and accumulator to be synthesized
by using the standard cell library under a 40-nm CMOS process,
the DR is chosen as 1/8. Note that f3dB is much less than fDIG.
When KPI is equal to 1/16 UI/code, KP and OINT,max can be
determined as 1/4, and 3/4, respectively, by (1) and (2). Table I
lists the parameters of this DCDR circuit.
B. The KI Controller
For the data with a frequency offset and a non-zero
frequency ramp rate due to SSC in a PI-based DCDR circuit,
(b)
5Gbps*(1-∆f/f) the maximum phase offset, which contributes as a part of the
10GHz*(1+∆f/f) total phase error, at the inputs of the BBPD is given as [8]
0 ~ -5000ppm
A
300ppm offset  (3)
1/8 K I  K BBPD  K PI  TD  f DIG 2
625 MHz
1/4 where A is the frequency ramp rate of the input data, KBBPD is a
1/16 UI/code linearized gain of the BBPD, and TD is the transition density of
z-4 input data. From (3), KI is inversely proportional to the phase
offset. The smaller KI is, the larger phase offset is. Thus, one
may increase KI to reduce the phase offset. However, when KI
becomes large, the latency-induced hunting jitter [6] increases
(1) and the phase margin (or loop stability) degrades. In summary,
when KI is large or small enough, the data sampling timing
margin is decreased and the high-frequency JTOL deteriorates.
Thus, an algorithm and a proposed controller will be presented
in this section to adjust KI properly.
Fig. 2(a) shows the KI controller which is composed of a 1:2
demultiplexer, a divide-by-2 divider, a sequence detector (SD),
and a code controller (CC). Fig. 2(b) shows the timing diagram
of the KI controller. This KI controller works with two states. In
the first state, once KI is updated, the DCDR circuit settles
(2) within 15TSSC where TSSC is the period of the external clock
CKSSC and its frequency is equal to 30kHz. After the DCDR
circuit settles, the SD detects the length and occurrence number
of the first three longest consecutive early signals from MV[1]
for an interval of 15TSSC. Since the data have the frequency
deviation of -5000 ppm caused by SSC, only the early signals
are detected. Suppose this condition is not met, the late signals
will be used. In the second state, the SD will generate a control
signal ENCC to enable the CC. The CC will update KI. Note that
CKSSC can be realized by dividing the DLF clock CKDIG.
In the first state, since the timing latency caused by the SD is
not critical, a 1:2 demultiplexer is used to lower the operation
frequency at fDIG/2 to save the power. Although the operation
frequency of the SD can be further lowered, it will increase the
required area occupied by the demultiplexers. In this work, a
PRBS of 27-1 is used which has the consecutive identical
digitals (CIDs) of 7 at most. Due to the majority voting using 8
early/late/hold signals, the sequence detector and the code
controller work. Note the transition density has a minor impact

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Transactions on Circuits and Systems II: Express Briefs

KI [6:0] = 0000010 x10-3

POpre = 1 5
L[5:0]
4.5
L[5:0] and SON[14:0]
4
|L[5:0] - Lpre[5:0]| > 1?
3.5
Yes No
3
L[5:0] > Lpre[5:0]? SON[14:0] > SONpre[14:0] ?

KI
2.5
Yes No Yes No 2
CMP = 1 CMP = 0 CMP = 1 CMP = 0 1.5
1
0.5
PO = CMP‧POpre + CMP‧POpre
t (ms)
0 2 4 6 8 10 12 14 16 18 20
KI[6:0] = KI,pre[6:0] - 1 if PO = 0 Fig. 4. Behavioral simulation results of KI by using the KI controller.
KI[6:0] = KI,pre[6:0] + 1 if PO = 1
Current = I
POpre = PO Current = 1.5I CKN CKP

Fig. 3. The flow chart of the code controller. #3 #7 #11 #15

TABLE II L[5:0] AND SON[14:0] COMPARISON RULES #2 #6 #10 #14
#1 #5 #9 #13
Present phase error #0 #4 #0
#8 #12
L[5:0]- Lpre[5:0] SON[14:0]-SONpre[14:0] CK0 CK90 CK180 CK270
> Previous one?
CK180 CK270 CK0 CK90
L[5:0]- Lpre[5:0]>1 - Yes (CMP=1)
L[5:0]- Lpre[5:0]<-1 - No (CMP=0)
SW[3:0] SW[7:4] SW[11:8] SW[15:12]
SON[14:0]> SONpre[14:0] Yes (CMP=1)
L[5:0]- Lpre[5:0]=1 Fig. 5. The phase interpolator.
SON[14:0]≤ SONpre[14:0] No (CMP=0)
SON[14:0]> SONpre[14:0] Yes (CMP=1)
L[5:0]- Lpre[5:0]=-1
SON[14:0]≤ SONpre[14:0] No (CMP=0) is set as 0 which is not included for comparison. In addition,
SON[14:0]> SONpre[14:0] Yes (CMP=1) ONL+1[14:0] is set as zero because it is not recorded by the KI
L[5:0]- Lpre[5:0] =0
SON[14:0]≤ SONpre[14:0] No (CMP=0)
controller yet. Similarly, when L[5:0]-Lpre[5:0]=1,
ONpre,Lpre-2[14:0] in (5) is set as zero. If SON[14:0] >
on f3dB in this case. If a PRBS of 231-1 with CIDs of 31 is SONpre[14:0], CMP becomes high; i.e., the present phase error
considered, the detection time for the sequence detector should is larger than the previous one.
be increased to acquire the sequences since the probability to The present polarity signal PO is determined by CMP and the
detect the correct value of L becomes low. In addition, the f3dB previous one POpre. When PO=1 or PO=0, KI[6:0] is increased
will be reduced due to the transition density. The parameters or decreased [12] by one least-significant bit (LSB),
such as L, SON, number of bits for the counter and threshold for respectively. To consider the slew-rate of -5000ppm SSC and
digital comparator are determined by the behavioral simulation. the loop latency, one LSB of KI[6:0] is chosen as 1/4096. When
The behavioral simulation shows that at least a 5-bit and an KI[6:0] converges, both L[5:0] and SON[14:0] are reduced.
11-bit counter are required to record L and SON, respectively. The phase error of the DCDR circuit is reduced and
Thus, L and SON are recorded as L[5:0] and SON[14:0] by high-frequency JTOL is enhanced. Although the analysis is not
using a 6-bit counter and a 15-bit one, respectively. Through D given, the measurement results shows the high-frequency
Flip-Flops clocked by CKSSC, Lpre[5:0] and SONpre[14:0] are JTOL is improved since the phase error is reduced when L and
recorded, which denote the previous L[5:0] and SON[14:0], SON is reduced. Note that if only L[5:0] is used to determine
respectively. SON[14:0] and SONpre[14:0] are calculated as CMP, KI cannot be properly adjusted. In the CC, both L[5:0]
2
SON [14 : 0]    Lk [14 : 0] (4) and SON[14:0] are used to determine CMP. Fig. 4 shows the
k 0 behavioral simulation results of KI by using the KI controller.
2 Using only L[5:0], KI will have a large deviation. Note that KI
SON pre [14 : 0]    pre, Lpre k [14 : 0] (5) still has a large deviation when only considering the summation
k 0 of the occurrence number of first two longest consecutive early
where ONL-k[14:0] and ONpre,Lpre-k[14:0] represent the present signals according to the behavioral simulations. So, the
and the previous occurrence number of the first three longest occurrence number of the first three longest consecutive early
consecutive early signals with the lengths of L-k (k = 0, 1, 2), signals with the same lengths are compared instead of the first
respectively. two longest consecutive early signals. By using both L[5:0] and
The flow chart of the CC is given in Fig. 3. To consider the SON[14:0], KI is converged to 8/4096 within ±1LSB.
stability, it is intuitive to have a small KI initially. The initial
KI[6:0] and the previous polarity signal POpre are set to C. Phase Interpolator
0000010 and 1, respectively. The comparison rules for L[5:0] Fig. 5 shows the PI. It is composed of 16 differential pairs
and SON[14:0] are listed in Table II. Note that if and the tail current sources are controlled by a thermometer
|L[5:0]-Lpre[5:0]| ≤ 1, the SON[14:0] and SONpre[14:0] are code SW[15:0]. The splitting differential pairs [13] ensure the
compared to further reduce the phase error. When L[5:0] is active tail currents working in saturation region when the
equal to Lpre[5:0], SON[14:0] and SONpre[14:0] are calculated control code is switching. To reduce the nonlinearity, the tail
by (4) and (5), respectively. When L[5:0]-Lpre[5:0]= -1, the current sources expressed by #0, #3, #4, #7, #8, #11, #12, and
occurrence number of the first three longest consecutive early #15 are 1.5x larger than the others. The post-layout simulation
signals (i.e., lengths with Lpre[5:0], Lpre[5:0]-1, and Lpre[5:0]-2) results show that the worst-case differential nonlinearity and
are considered in comparison while the case for integral nonlinearity under different process corners are
Lpre[5:0]-3=L[5:0]-2 is not considered. So, ONL-2[14:0] in (4) 0.13LSB and 0.15LSB, respectively.

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Fig. 6. Die photo
(a) (b)
Fig. 7. Measured eye diagrams of (a) retimed data and (b) CKREC.
(a)
(c)
(e) (f)
Fig. 8. Measured JTOL versus KI. (a) Without frequency offset. With
frequency offset of ±300 ppm and input data with SSC of (b) 0 ppm,
(c) -1250ppm, (d) -2500ppm, (e) -3750ppm, and (f) -5000ppm.
III. EXPERIMENTAL RESULTS
This chip is fabricated in a 40-nm CMOS process. Fig. 6
shows the die photo and its core area is 0.022 mm2. The total
power consumption of the DCDR circuit is 9.9mW wherein the
KI controller consumes 0.3mW from a supply voltage of 1V.
For a 5-Gb/s PRBS of 27-1, Fig. 7(a) and (b) shows the
measured eye diagrams of the retimed data and the recovered
clock, respectively. The measured rms jitter of the retimed data
and the recovered clock are 9.47ps and 9.12ps, respectively.
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Transactions on Circuits and Systems II: Express Briefs
7/4096
6/4096
4/4096
3/4096
2/4096
Fig. 9. Measured transient responses of KI generated by the KI
controller with five cases.
Note that the jitter of the recovered clock is mainly contributed
by the latency-induced hunting jitter. Fig. 8(a)-(f) show the
measured JTOL with six cases. KI is externally swept from
1/4096 to 1/64 by a factor of two and KP is fixed at 1/4. KP is
kept fixed to meet the 3dB corner frequency of the JTOL mask
(~5MHz for USB3.0 JTOL mask is chosen in this work). All
the measured bit error rates (BERs) are less than 10 -12. The
high-frequency JTOL is referred as the JTOL when the jitter
frequency>5MHz.
In Fig. 8(a)-(f), when KI 1/128, the high-frequency JTOL
degrades. It is because that the hunting jitter increases and the
phase margin (or loop stability) degrades. For the cases without
(b)
SSC, when KI 1/512, the high-frequency JTOL is improved,
compared to those with KI >1/512 as shown in Fig. 8(a) and (b).
For the cases with frequency offset of ±300 ppm and SSC
frequency deviation of -1250~-5000ppm, the high-frequency
JTOL degrades when KI < 1/1024 in Fig. 8(c)-(f). For instance,
when KI =1/4096, the minimum high-frequency JTOL of Fig.
8(c)-(f) are 0.51UIpp, 0.49UIpp, 0.42UIpp and 0.34UIpp,
respectively. When the SSC frequency deviation rises, the
DCDR circuit with a small KI has a poor frequency tracking
(d) capability and its high-frequency JTOL degrades.
To demonstrate the proposed KI controller, the measured
transient responses of KI generated by the KI controller are
shown in Fig. 9. The case without the frequency offset is not
shown since its transient response is almost similar to that with
the frequency offset of ±300 ppm. Note that each curve is
averaged by 30 times to reduce the undesired noises. When the
SSC frequency deviation rises, KI generated by the KI controller
is also increased for the DCDR circuit to track the frequency
deviation. For example, KI generated by the KI controller
converges to 2/4096 and 7/4096 for the cases with the
frequency offset of ±300ppm and the SSC frequency deviation
of 0 ppm and -5000 ppm, respectively. The noises induced by
SSC and the power supply have an impact on both L[5:0] and
SON[14:0]. All the KI values generated by the KI controller are
converged within ±1LSB (= 1/4096). For all the cases, the
worst-case convergence time is 15ms which is equal to 465
cycles of CKSSC.
Note that the minimum high-frequency JTOL of 0.55UIpp is
obtained for all six cases when KI is fixed at 1/512. The
proposed method also achieves 0.55UIpp or better by adjusting
KI. In Fig. 8(a), to compare the case with KI=1/512, the
measured high-frequency JTOL at 7.4MHz and 41.9MHz is
improved by 0.054UIpp and 0.034UIpp, respectively, while KI is
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Transactions on Circuits and Systems II: Express Briefs

TABLE III PERFORMANCE SUMMARY AND COMPARISON

[4] [5] [13] [14] [15] [16] This work
Technology (nm) 28 40 65 65 40 22 40
Supply (V) N/A 0.81 1.2 1 0.95 1.15 1
Data Rate (Gb/s) 28 1.25-8 1-16 1.5-10 2.5-8 16 5
Type Digital Digital Digital Digital Digital Digital Digital
Power (mW) 107 12 @8-Gb/s 87.6@16-Gb/s 60 @8.5-Gb/s 223.25**@8-Gb/s 59.7 9.9
FoM (mW/Gb/s) 3.82 1.5 5.48 7.06 27.9 3.73 1.98
Active Area (mm2) 0.073 0.005 0.088 0.33 0.445** 0.028 0.022
BER <10-12 <10-9 <10-12 N/A <10-10 <10-12 <10-12
SSC Capability No Yes No Yes Yes No Yes
JTOL@10MHz (UIpp) 0.25 0.55 0.4*** 0.6* 0.4 0.4*** 0.6
*Measured@8.5-Gb/s with 200 ppm frequency difference. **Transmitter is included. ***JTOL measured@10-Gb/s.
2/4096 generated by using the proposed method. In Fig. 8(d), to
compare the case of KI=1/512, when KI=4/4096 is generated by
using the proposed method, the measured high-frequency JTOL
are almost the same for both cases with the deviation less than
0.01UIpp. In Fig. 8(f), to compare the case of KI=1/512, when
KI=7/4096 is generated by using the proposed method, the
measured high-frequency JTOL are almost the same with the
deviation less than 0.01UIpp. Fig. 10 shows the measured JTOL
with six cases using KI generated by the KI controller with the
PRBS of 27-1. For different SSC frequency deviations, KI can
be dynamically adjusted and the f3dB of the DCDR circuit is kept
fixed. The measured minimum high-frequency JTOL for all six
cases is improved to 0.55UIpp and f3dB is fixed at 5MHz.
Compared with a fixed KI, the proposed method can keep the
final KI small for SSC with small frequency deviations and the
phase margin (or loop stability) of the DCDR circuit is also Fig. 10. Measured JTOL with six different cases after adaptation.
improved. For the high-frequency JTOL with input sinusoidal
[5] H. Pan et al., “A digital wideband CDR with ±15.6kppm frequency
jitter frequency of 10 MHz, our work achieves 0.6UIpp under tracking at 8Gb/s in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf.
frequency offset of ±300 ppm and SSC of -5000ppm. Finally, (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 442-443.
Table III shows the performance summary and comparison. [6] T. Yoshikawa et al., “An over-1-Gb/s transceiver core for integration into
large system-on-chips for consumer electronics,” IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 16, no. 9, pp. 1187-1198, Sep. 2008.
IV. CONCLUSIONS [7] J. L. Sonntag et al., “A digital clock and data recovery architecture for
The DCDR circuit using the proposed KI controller is multi-gigabit/s binary links,” IEEE J. Solid-State Circuits, vol. 41, no. 8,
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