470 IEEE SOLID-STATE CIRCUITS LETTERS, VOL.

3, 2020

A 6.4–11 Gb/s Wide-Range Referenceless Single-Loop

CDR With Adaptive JTOL
Hye-Ran Kim , Jun-Yeol Lee, Jeong-Su Lee, Dong-Seok Kang, and Jung-Hoon Chun , Member, IEEE

Abstract—A referenceless single-loop clock and data recovery (CDR)

with a 6.4–11-Gb/s capture range is presented. A dynamic bandwidth
control (DBWC) technique for reducing the frequency-acquisition time
and adaptive loop gain control (ALGC) for optimizing the jitter toler-
ance are described in detail. In addition, a cycle-slip detector (CSDET)
with a consecutive-edge selector (CES) is proposed to improve the accu-
racy of the frequency detection. Fabricated in a 28-nm CMOS process,
the proposed CDR has a frequency-acquisition time that is reduced by
approximately 30% with the DBWC technique enabled. Also, the cap-
ture range is expanded by 1.1 Gb/s compared to the prior work due to
improvement of the CSDET. The proposed ALGC technique based on
jitter estimation is demonstrated with JTOL test results using PRBS15
input data with 0.28-UIPP random jitter and 1–100 MHz sinusoidal jitter.
Index Terms—Adaptive loop gain control (ALGC), cycle-slip detec-
tion, frequency acquisition time, half-rate linear phase detector (PD),
referenceless clock and data recovery (CDR), single-loop CDR.

Fig. 1. Proposed referenceless single-loop CDR.

I. I NTRODUCTION
Clock and data recovery (CDR) circuits are responsible for both
frequency tracking to find the input data rate and phase tracking
to maximize the timing margin between the recovered clock and
the input data. General, dual-loop CDRs, which implement these
two functions in two different loops, are widely used. However,
despite the absence of a dedicated frequency-tracking loop, single-
loop CDRs, which have a relatively small active area and simple loop
control, can still perform frequency acquisition with a single phase-
tracking loop. Furthermore, referenceless CDRs have been studied
rigorously because they can be simply implemented without an exter-
nal clock. A variety of circuit techniques to expand the frequency-
tracking range, such as a rotational frequency detector (FD) or digital
quadri-correlator FD (DQFD), have been introduced [1]–[4].
However, the frequency-tracking and phase-tracking performances
of a referenceless single-loop CDR have a tradeoff relationship. For
example, increasing the loop gain helps to reduce the frequency-
acquisition time, whereas it causes the degradation of the timing
margin according to the input jitter [5]–[6]. Therefore, we need
to eliminate or mitigate the interference between the frequency-
tracking and phase-tracking operations and optimize them separately
to achieve both fast locking and high jitter tolerance characteristics.
Manuscript received August 1, 2020; revised September 18, 2020; accepted
September 23, 2020. Date of publication September 28, 2020; date of cur-
rent version October 21, 2020. This article was approved by Associate
Editor C. Kim. This work was supported in part by the Future Interconnect
Technology Cluster Program of Samsung Electronics and in part by IITP
grant funded by the Korea Government (MSIT) under Grant 2020-0-00960.
(Corresponding author: Jung-Hoon Chun.)
Hye-Ran Kim is with the DRAM Design Team, Samsung Electronics,
Hwasung 18448, South Korea, and also with the College of Information and
Communication Engineering, Sungkyunkwan University, Suwon 16419, South
Korea (e-mail: hr.kim@skku.edu).
Jun-Yeol Lee, Jeong-Su Lee, Dong-Seok Kang, and Jung-Hoon Chun
are with the College of Information and Communication Engineering,
Sungkyunkwan University, Suwon 16419, South Korea (e-mail:
jhchun@skku.edu).
Digital Object Identifier 10.1109/LSSC.2020.3027021
2573-9603 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Given these requirements, this letter introduces a dynamic band-
width control (DBWC) technique that is only activated during the
frequency-tracking operation and an adaptive loop gain control
(ALGC) technique to improve the jitter tolerance of a referenceless
single-loop CDR.
This letter is organized as follows. Section II presents the overall
architecture of the presented CDR with a detailed explanation of the
implemented circuits. Section III shows the chip measurement results.
II. P ROPOSED A RCHITECTURE
The overall structure of the proposed CDR is shown in Fig. 1.
The cycle-slip detector (CSDET), the DBWC block, and the ALGC
block are added to the conventional phase-tracking loop based on the
half-rate linear phase detector (PD). The CSDET controls the output
of the PD to perform a frequency-tracking operation. To expand the
capture range, an additional circuitry named consecutive-edge selec-
tor (CES) is added to the CSDET introduced in a prior work [7].
The auxiliary CP (AUX-CP) in the DBWC block is activated only
during frequency tracking to reduce the frequency-acquisition time.
After the frequency-tracking operation is completed, the ALGC block
estimates the frequency and amplitude of the input jitter and adjusts
the loop gain accordingly to maximize the timing margin during the
phase-tracking operation.
A. Dynamic Bandwidth Control Technique
In the CSDET, the DATA edges sample CK0 and CK90 as
illustrated in Fig. 1. According to the sampling results, the phase
relationship between the input data and clock can be defined as four
states: (A), (B), (C), and (D), as shown in Fig. 2(a)–(d). For example,
the state (A) means that the sampled CK0 and CK90 are high and
low (CK0 = 1, CK90 = 0), respectively. The PD outputs, UP_PRE
and DN_PRE, are set according to the determined state and affect the
corresponding charge pump (CP) current. When there is a frequency
error, the state determined by the phase relationship between the input

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KIM et al.: 6.4–11-Gb/s WIDE-RANGE REFERENCELESS SINGLE-LOOP CDR WITH ADAPTIVE JTOL
(a) (b)
(c) (d)
Fig. 2. Frequency acquisition based on ICP when (a) 2 fck < fdata , (b) 2
fck > fdata and ICP,AUX , (c) 2 fck < fdata , and (d) 2 fck > fdata .
(a) (b)
Fig. 3. Timing diagram of overall frequency-acquisition process in the
proposed CDR when (a) 2 fck < fdata and (b) 2 fck > fdata .
data and clock continues to change. When 2 fck < fdata , as shown in
Fig. 2(a), the state changes in order of “A→D→C→B→ · · · ” When
2 fck > fdata , the state changes the opposite direction as shown in
Fig. 2(b). Therefore, the PD outputs keep changing accordingly, and
the CP current, ICP , ramps and flips repeatedly as shown in Fig. 2(a)
and (b). The abrupt change of ICP is called a cycle slip, and ICP after
each cycle-slip occurrence, which is marked in dark gray in Fig. 2(a)
and (b), interferes with the frequency acquisition [7].
When there are consecutive transitions of DATA, it is possible to
determine both the sign of the frequency error and whether a cycle
slip occurs, based on the state-movement direction. For example, as
shown in Fig. 2(a), DN_BLKB is generated by the CSDET when
the state changes from (A) to (D) or from (C) to (B). If 2 fck <
fdata , DN_BLKB is asserted high, blocking the pull-down current
of CP to achieve the frequency acquisition. At the same time, as
depicted in Fig. 2(c), an additional push-up current from AUX-CP
is generated by DN_BLKB, and it speeds up the increasing rate of
fck . The push-up current of AUX-CP is generated only when both
DN_BLKB and DN are activated. Similarly, UP_BLKB is generated
by the CSDET when the state moves in the opposite direction, as
shown in Fig. 2(b). When 2 fck > fdata , UP_BLKB blocks the push-
up current of CP in Fig. 2(b) and generates the pull-down current of
AUX-CP in Fig. 2(d). Finally, fck decreases until the frequency acqui-
sition is obtained. Fig. 3(a) and (b) shows that the timing diagram of
the overall frequency-acquisition process in the proposed CDR.
As explained above, the proposed DBWC block is activated only
when the frequency acquisition is in progress. The proposed CDR
contains two CPs, but there is no interference between the two CP
operations. Adding a DBWC block is effective in terms of acquisition
time and complexity because it does not require any additional control
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471
(a)
(b) (c)
Fig. 4. (a) Frequency detection with clock pattern DATA versus nonclock
pattern DATA. (b) Operation of the CSDET with CES. (c) Normalized PFD
gain comparison between w/o and with CES.
between the frequency-tracking loop and the phase-tracking loop, as
is needed in the dual-loop CDR.
B. Consecutive-Edge Selector in CSDET
To illustrate the shortcomings of the conventional CSDET, Fig. 4(a)
shows the phase relationship between CK0/CK90 and DATA with two
positive ferr ( ferr = fdata - 2 fck > 0) cases: 1) close to maximum or
2) nearly zero. It is assumed that during the first half of the depicted
period, DATA toggles like a clock, however, during the second half,
DATA has random transitions. With a large ferr , the state determined
at every rising edge of the clock-pattern DATA changes in order of
“A→C→B→ · · · ” Therefore, the transition from (C) to (B), which
is “valid” for correct frequency detection, can be monitored by the
two successive rising edges. However, if DATA does not toggle like
a clock, some of state detection can be skipped. As a result, “valid”
state transitions from (C) to (B) may not occur and instead “false”
transitions from (B) to (C) may occur. On the other hand, with a
small ferr the state changes slowly (e.g., C→C→C→B→B→ · · · ):
therefore, the possibility of the wrong state transition is low even if
the data transition density is low.
In Fig. 4(a), we can observe that the transition from (C) to (B)
detected by two consecutive rising edges of DATA always passes
through the intermediate state (A) at the “falling” edge in the mid-
dle of the two rising edges. The proposed CES, shown in Fig. 1,
detects this intermediate state by sampling CK0 and CK90 at DATA’s
falling edges. Using the intermediate state information from the CES
to determine the validity of detected transitions, we can efficiently
exclude false transitions described above. Fig. 4(b) shows the opera-
tion of the proposed CSDET with CES. If 2 fck < fdata , the frequency
acquisition with DN_BLKB activation starts only when the state tran-
sition due to two consecutive rising edges of DATA is from (C) to
(B) and the output of CES, the intermediate state, is (A). Similarly, if
2 fck > fdata , the transition from (B) to (C) is considered valid when
the intermediate state from CES is (D).
Fig. 4(c) shows the normalized PFD gain according to the
frequency offset between the clock and data simulated with 10-Gb/s
PRBS15 data. Because the CES can exclude false state transitions,
the PFD gain increases especially when there is a large frequency off-
set. A higher PFD gain with a large frequency offset helps to perform
frequency acquisition, thus extending the capture range.
472
(a)
(b) (c)
Fig. 5. (a) ALGC overall block diagram and timing diagram with
(b) high-frequency input jitter and (c) low-frequency input jitter.
Fig. 6. Simulation result of V and INC for various jitter frequencies and
amplitudes in ALGC block.
C. Adaptive Loop Gain Control
The jitter estimation technique in a BBPD-based phase-tracking
loop [5] is applied to the proposed CDR, and an improved
methodology is obtained by the characteristics of a linear PD.
Fig. 5(a) shows the configuration of the ALGC block. The adaptive
loop gain CP (ALG CP), switched capacitor (SC), and comparator
(COMP) estimate the input jitter, and the following synthesized digi-
tal decision block determines the loop gain according to the estimated
jitter. ICP,ALG generated by UP and DN, outputs of the linear PD, is
provided to the SC. The SC is synchronized to DCLK1 which is on
the order of tens of MHz. The SC performs integration and precharge
operations for the first and second half cycles of DCLK1, respectively.
V of the SC deviates from the precharged level, VPRE, depending
on the PD output determined by the input jitter. The COMP deter-
mines whether V is between the two threshold voltages, VPRE+α
and VPRE-α. The frequency of DCLK2 for the COMP is the same
as that of DCLK1 with a certain phase offset. The final output signal,
INC, is provided by merging the two COMP outputs through a 2:1
mux.
Fig. 5(b) and (c) shows the timing diagrams when high- and low-
frequency sinusoidal jitter are applied, respectively. In Fig. 5(b),
the high-frequency input jitter repeats a number of cycles while
ICP,ALG is accumulated in SC: thus, V cannot exceed the VPRE+α
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IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 3, 2020
(a) (b)
Fig. 7. (a) Die-photo with block description. (b) Recovered clock jitter at
fck = 4 GHz.
(a)
(b)
Fig. 8. Measured frequency-acquisition behavior with and without DBWC
when (a) fdata = 11 Gb/s and (b) fdata = 6.4 Gb/s.
or VPRE−α thresholds. However, when low-frequency jitter is
present, as shown in Fig. 5(c), V exceeds the threshold because
ICP,ALG maintains the same polarity during the integration period.
Finally, INC = 1 is provided when DLKC2 is activated. While
INC remains high, the counter (CNT) inside the digital deci-
sion block is activated to generate 8-bit INC_CNT as illustrated
in Fig. 5(a). If INC_CNT exceeds the threshold within a prede-
termined time, it is determined that considerable low-frequency
jitter is present, and the loop gain is increased for better jitter
tracking. The determined loop gain is encoded to the number of
enabled CPs.
On the other hand, since the linear PD is used in the proposed CDR,
V and INC_CNT increase proportionally as the amount of jitter
increases. Depending on INC_CNT, the incremental step for the loop-
gain control is adjusted with the two different threshold values, NTH1
and NTH2 (NTH1 < NTH2), as described in Fig. 5(a). In Fig. 6,
the simulation results of V and INC are shown for three different
cases of input jitter: 1) 1 MHz/1.2× input jitter; 2) 1 MHz/1.0×
input jitter; and 3) 100 MHz/0.15× input jitter. Fig. 6 shows that the
proposed jitter estimation circuit with VPRE = 0.5 V and α = 50 mV
generates V and INC according to the input-jitter frequency and
amplitude.
KIM et al.: 6.4–11-Gb/s WIDE-RANGE REFERENCELESS SINGLE-LOOP CDR WITH ADAPTIVE JTOL
Fig. 9. Measured JTOL with ALGC.
TABLE I
P ERFORMANCE C OMPARISON W ITH P REVIOUS W ORKS
III. E XPERIMENT R ESULTS
The proposed CDR is fabricated in a 28-nm CMOS process. The
Die photograph is shown in Fig. 7(a), and the active area of the CDR
is approximately 0.111 mm2 . The jitters of the recovered clock are
monitored by a Tektronics oscilloscope MSO71604C, and the results
are shown in Fig. 7(b). With a 4-GHz recovered clock, the RMS and
peak-to-peak jitter were 1.66 ps and 12.5 ps, respectively.
Fig. 8(a) and (b) shows the measured frequency-acquisition behav-
ior of the proposed CDR. With various initial frequencies of the
VCO, the capture range was measured while sweeping the data
rate. A maximum capture range of 6.4–11 Gb/s can be achieved
by setting the initial frequency to 4.2 GHz. Fig. 8(a) shows that the
frequency-acquisition time without DBWC is approximately 14 μs
when fdata is 11 Gb/s and the initial fck is 4.2 GHz. With DBWC, the
frequency-acquisition time is reduced from 14 to 9 μs. Also, Fig. 8(b)
shows the frequency acquisition when fdata is 6.4 Gb/s and the initial
fck is 4.2 GHz. Without DBWC, the frequency acquisition time is
less than 25 μs and with DBWC, it is reduced from 25 to 15 μs.
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473
That is, the proposed DBWC reduces the frequency-acquisition time
by approximately 30%.
As shown in Fig. 9, when ALCG is off and five CPs are always
active, JTOL is relatively high at low jitter frequencies, but could
not satisfy the BER criteria at high jitter frequencies. Conversely,
as indicated by the blue dash-dotted line, a relatively high JTOL is
obtained at high jitter frequencies when one CP is activated. When
ALGC is finally activated, the number of activated CPs adaptively
changes depending on the jitter frequency and amplitude. In other
words, up to five CPs can be activated for low-frequency input jitter,
thus maximizing JTOL, and for high-frequency input jitter, only one
CP remains active to maximize JTOL. In conclusion, the proposed
CDR with ALGC achieves high JTOL without increasing BER over
a wide range of input-jitter frequencies.
The overall performance of the proposed CDR is compared with
that of previous works in Table I. The proposed CDR is the only
referenceless single-loop CDR with both a wide capture range and
adaptive JTOL. The proposed CDR, including the DBWC and ALGC
was implemented with only 0.11-mm2 active area and achieved an
energy efficiency of 2.7 pJ/bit. The relatively high power consumption
of the proposed CDR is due to its 8-phase VCO operating under a
1.5-V power supply.
ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education Center
(IDEC), Korea.
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