482 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO.
4, APRIL 2016
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less
Digital CDR With Half-Rate Common-Mode
Clock-Embedded Signaling
Kyongsu Lee, Member, IEEE, and Jae-Yoon Sim, Senior Member, IEEE
Abstract—This paper presents a continuous-rate reference-less
clock and data recovery (CDR) circuit that utilizes common-mode
clock-embedded signaling (CM-CES) and injection locking tech-
niques to reduce design complexity for the half-rate data recovery.
In the proposed receiver, the use of wideband injection-locked os-
cillator (ILO) greatly suppresses its phase noise while the narrow-
band digital phase tracking loop (DPTL) tunes retiming phase. For
wide-range and continuous-rate operation, four circuit techniques
have been adopted: a VCO with active inductance load for low
VCO gain at high frequency, a wide-range digitally-controlled
delay line (DCDL) with adaptive band selection, a linearized
delay control unit with CM-to-delay conversion technique, and
a coarse frequency detection scheme to drive the free-running
oscillator frequency toward injection locking. The prototype CDR,
fabricated in low power CMOS 65 nm technology, successfully
detects 0.8–6.5 Gb/s data rates over 5 FR4 trace with 231 − 1
PRBS pattern satisfying BER < 10−12 . The power efficiency was
2.4 mW/Gb/s at 6.5 Gb/s.
Index Terms—Clock and data recovery, common-mode clock-
embedded signaling, high-speed I/O, injection-locked oscillator,
reference-less CDR, wireline transceivers.
I. I NTRODUCTION
C ONTINUOUS-rate reference-less clock and data recov-
ery (CDR) circuit provides a cost efficient single-chip
solution for broad range of wireline specifications. The key
challenge for realizing this CDR has been to achieve wide
frequency detection without external reference frequency. Con-
ventional approaches such as quadri-correlator [1], [2] and rota-
tional frequency detectors [3], [4] have often exhibited limited
bit rate detection range because of contradictory bandwidth
requirements for noise suppression and pull-in lock range.
To overcome this limitation, various frequency acquisition
schemes [5]–[10] have been proposed for wide frequency-range
reference-less CDR. The accuracy of bit rate detection to ensure
Manuscript received August 24, 2015; revised December 8, 2015 and
January 9, 2016; accepted January 12, 2016. Date of publication March 15,
2016; date of current version April 15, 2016. This research was supported
by Basic Science Research Program through the National Research Founda-
tion of Korea (NRF) funded by the Ministry of Education (2010-0020163,
2013R1A2A2A01015738). This paper was recommended by Associate Editor
S. Levantino.
K. Lee is with the Department of Electronic Engineering, Inha University,
Incheon 22212, South Korea (e-mail: kyungsul@inha.ac.kr).
J.-Y. Sim is with the Department of Electrical Engineering, Pohang Uni-
versity of Science and Technology (POSTECH), Pohang 37673, South Korea
(e-mail: jysim@postech.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2016.2528480
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
subsequent phase lock requires additional design complexities,
and its implementation is often limited to full-rate architectures
[5], [7], [9].
In this paper, we propose a reference-less CDR scheme that
combines half-rate common-mode clock-embedded signaling
(CM-CES) and injection locking technique to achieve wide-
range frequency detection without trading off in noise sup-
pression and to relax the accuracy requirement of frequency
detection. In the CM-CES scheme, the clock signal is simply
extracted by filtering the received signal that is a direct sum
of NRZ data and clock. Since this signaling scheme carries a
source clock within the data signal traveling through the same
channel, the recovered clock can be conveniently used for data
recovery over wide data frequency range.
The feasibility of the CM-CES scheme has been proved
initially in the [11] where each of complementary full-rate
clock signals is added commonly to each pair of two differential
links. The phase of recovered complementary clock is tuned
from a delay line in the transmitter to secure retiming margin
for the recovery of two independent data streams. In [12],
each of full-rate differential clock signals is embedded to each
leg of single differential link where high-Q filtering has to be
incorporated to recover differential clock signal. Recently, the
group delay characteristics of half-rate CM clock-embedded
differential signaling have been proposed to realize matched
source-synchronous receiver designs [13], [14]. For higher data
rate, however, they require special cares to avoid mismatches
between data and clock recovery paths.
The proposed receiver in this paper takes advantage of half-
rate CM-CES scheme to realize a cost efficient reference-less
CDR for serial-links. Compared with previous approaches, the
proposed CDR tunes the clock phase continuously with respect
to data transitions in order to secure retiming margin in the
presence of group delay mismatches between data and clock
signal propagation paths. To realize half-rate data recovery,
the recovered clock is injected into an oscillator to generate
quadrature phases without losing its bit rate accuracy. Then, the
phase tracking of retiming clock is independently accomplished
by using a digital phase tracking loop (DPTL) to secure the
timing margin. This approach obviates the need for a high
gain frequency-locked loop (FLL) and multi-phase generation
circuits for the half-rate data recovery, thereby reducing design
complexity and power consumption. In addition, the filtering
nature of injection-locked oscillator (ILO) offers spectral bene-
fit to the DPTL with its wideband characteristic by decoupling
the contradictory loop bandwidth requirements for wideband
LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Fig. 1. Proposed receiver with conceptual signaling scheme (Tb = bit time).
suppression of oscillator noise and low dithering jitter at steady
state [15]. This loop dynamics, similar to multiplying delay-
locked loop (MDLL) [16], [17], leads to dramatic reduction
of the oscillator phase noise. It is also worth noting that
CM-CES allows unlimited run-length of continuous 1 or 0 bit
in the data stream and increases effective data rate by removing
the need for transition encoding (for example, up to 20% saving
for 8B10B).
For the wide continuous-rate operation, the proposed ILO
adopts active inductance load to extend its frequency range,
which also helps to reduce VCO gain (Kvco ) at high frequency
band. In the DPTL, a new delay control unit that utilizes
CM-to-delay conversion is proposed to realize a wide operation
range with improved linearity. Lastly, a digital coarse frequency
detection (CFD) scheme is implemented to drive the free-
running frequency of ILO toward its locking range and to preset
the range of controlled delay line adaptively in the DPTL.
Section II introduces the proposed signaling scheme and
CDR architecture. Circuit details are described in Section III.
Section IV describes experimental results, and Section V con-
cludes this work.
II. P ROPOSED CDR A RCHITECTURE
A. Receiver Overview
The half-rate CM-CES scheme and proposed receiver archi-
tecture are described in Fig. 1. A 2-to-1 serialized differential-
mode (DM) NRZ stream is combined with a half-rate CM clock
and transmitted via a communication channel. The phase of
clock signal to be combined is delayed properly to minimize
data to clock interference [13]. As a result of signal combina-
tion, each of differential signals in the channel includes half-
rate clock tone (0.5/Tb ) in the transmission signal spectrum.
This signal combination scheme provides convenience in the
signal recovery since the clock signal is considered as CM noise
for the data recovery and the data signal is considered as DM
noise for the clock recovery. Therefore, DM and CM amplifiers
at the receiver front-end separate data and clock without requir-
ing a high Q BPF. In the proposed receiver, a dual-functional
BPF is implemented to compensate channel attenuation of data
signal and to extract commonly embedded clock signal with
amplification. The frequency of half-rate clock is close to the
signal band of equalization such that the sharing of band-
filtering circuit is feasible, which is an advantage of embedding
483
Fig. 2. (a) Proposed phase tracking loop and (b) its phase noise profile.
a half-rate frequency. The extracted half-rate clock is converted
to differential with a single-to-differential converter (S2D) and
injected into an oscillator for phase multiplication.
When a pair of inhomogeneous micro-striplines is used for
the channel medium, DM and CM signals see different channel
characteristics resulting in inter-mode channel skew (IMCS)
[13]. This IMCS makes it difficult to predict the exact phase
relationship between the recovered data and clock thereby
requiring a PTL at the receiver. The phase of retiming clock is
adjusted through a feedback loop with digitally controlled delay
line (DCDL) for the optimal sampling margin. The use of ILO
offers three major benefits in this architecture: 1) generating
4 phases out of injected differential clock, obviating the need
for additional multi-phase generation loop to drive a half-rate
binary PD, 2) suppressing the VCO noise with large bandwidth
of ILO, and 3) avoiding the loop stability and jitter peaking
issues by using unconditionally stable PTL.
For wideband continuous-rate operation, the adaptation of
VCO frequency band to the data rate is achieved by employing
CFD circuit, which drives the free-running frequency to the
vicinity of injection lock. Note that the frequency tracking
accuracy of CFD circuit is greatly relaxed since the actual bit
rate of clock is tracked by injection frequency, which is closely
correlated to data. The digitally implemented CFD circuit is
designed to offer unlimited range of frequency tracking without
harmonic locking issue. The purpose of the switch controlled by
Injon signal is to let the VCO be in the free running state during
the coarse frequency tracking.
B. Digital Phase Tracking Loop
In the proposed DPTL in Fig. 2(a), the quantized phase error
from a half-rate bang-bang PD is decimated and accumulated
before it is fed to DCDL to adjust the sampling time. In
lock state, ILO provides filtering function without frequency
modulation of its output; thereby DPTL tracks only the phase
difference.
In the conventional CDRs, the requirement of a large loop
bandwidth to track wide frequency difference often contradicts
with a small loop bandwidth requirement to reduce dithering
jitter in locked state [11]. In the proposed CDR, the use of
ILO can decouple this tradeoff since a frequency offset (or a
phase ramp) can be tracked by the ILO with the large bandwidth
(equivalently its lock range), whereas the phase tracking band-
width can be independently designed to improve steady-state
484 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016
jitter performance. This loop dynamics is similar to that of
MDLL [16], [17] in that the jitter accumulation of the oscillator
is periodically reset by injecting a clean reference edge at every
N (> 1) integer multiple of oscillation cycle. The difference in
the proposed CDR is that its injection period is identical to the
oscillation cycle (N = 1). The bandwidth of digital feedback
loop for sinusoidal input jitter is represented by [15]
1 ΔT
fDPTL ≈ · · fUP (1)
2π · Φm DF
where Φm represents the amplitude of input jitter, ΔT is the
phase step in DCDL, DF is the decimation factor, and fUP is
updating frequency of the loop.
Two-stage ring oscillator has the minimum number of differ-
ential buffers to generate quadrature clock phases. Its lock range
under a single stage injection can be derived in terms of free-
running frequency (ωF R ) from [18, Eq. (46)]. In this derivation,
we assume that the injection frequency is close enough to the
oscillation frequency; thereby the phase difference between
injection and non-injection stages is close to π/2. The resultant
single-side lock range can be represented as
π/4 · cos θ
ωSL ≈ ωF R · (2)
I1 /IIN J + π/4 · sin θ
where I1 is bias current in the delay stage, IIN J is injection
current, and θ is phase difference between injection signal and
oscillation signal at the injection stage. In the nominal operation
(IIN J < I1 ), the lock range, which is a strong function of
IIN J , can be tuned by controlling the injection signal ampli-
tude. Typically, the lock range of ILO in strong injections can
be at least an order higher than the DPTL bandwidth in (1).
As the (2) implies, the difference between the free running and
injection frequencies does not affect the lock range of ILO once
the lock range sufficiently covers the accuracy of CFD.
C. Noise Filtering by the ILO
The sum of data and clock signals in CM-CES increases
transition density of resultant signal and incurs additional in-
terference while it passes through the band-limited channel
[13]. As a result, the embedded clock experiences a data-
induced jitter that often appears at high frequency spectrum.
The purpose of BPF in the receiver front-end is to filter out
this noise. However, its limited Q cannot completely remove
the noise. The use of ILO offers additional filtering of the noise
since the ILO, similar to PLL, provides the first-order low-pass
noise filtering to the injection signal where its bandwidth is
defined by its lock range [19].
The intrinsic phase noise of the oscillator can be dramatically
reduced by injection locking since its output phase is periodi-
cally corrected at each injection cycle. In the proposed DPTL,
unlike MDLL, the multiplication factor (N ) is set to 1 thereby
minimizing jitter accumulation [20]. The DPTL in the presence
of input phase noise is described in Fig. 2(a). Linj (ω) and
Ldat (ω) respectively represent the phase noise of the recovered
clock and the NRZ data. After the injection (Injon = high),
Fig. 3. (a) S-domain model of proposed PTL and (b) estimated phase noise
profile at β = 0.7.
the oscillator phase noise (Lo (ω)) is suppressed and its in-
band noise is predominantly determined by Linj (ω) and ILO
bandwidth (ωSL ) as shown in Fig. 2(b). When the DPTL
becomes active (Ptlon = high), its in-band noise below ωPTL
is dominantly determined by Ldat (ω). At this incident, the
contribution of the oscillator noise under injection locking to
the in-band phase noise is negligible. Note that a sub-rate inject-
ing MDLL scheme [16], [17] could also be employed for the
generation of half-rate quadrature phases from the recovered
clock to reduce the frequency of embedded clock. In this case,
the in-band noise due to the sub-rate injection will be increased
by N 2 times the phase noise of Ldat (ω) [20].
The s-domain model of proposed PTL assuming toggling
data input (3.25 GHz) is described in Fig. 3(a). The transfer
functions, Hrl (s) and Hup (s), represent the effect of the phase
realignment and up-conversion of injection noise respectively
[21]. The resultant output phase error can be derived as
K · Hrl (ω) s2 · Hrl (ω)
φo = · φdat + · φosc
s2 + K · Hrl (ω) s2 + K · Hrl (ω)
s2 · Hup (ω)
+ 2 · φinj (3)
s + K · Hrl (ω)
where K represents the gain product of phase detector (KP D ),
loop filter (KLF ), delay line (KDL ), and VCO (KVCO ). At low
frequency offset (s → 0), the output phase error is mainly con-
tributed by data phase error (φdat ). However, at high frequency
offset, the realigned oscillator noise (Hrl (s) · φosc ) and up-
converted injection signal noise (Hup (s) · φinj ) contributes to
the output phase error. The phase noise transfer functions after
injection locking (black dotted line) and after phase tracking
(black solid-line) are plotted in Fig. 3(b). In this estimation,
oscillator noise is modeled with its thermal (1/f 2 ) and flicker
(1/f 3 ) noise components. As expected, the phase noise at
high frequency offset is mainly governed by the realigned
oscillator noise (red line) where its bandwidth is bounded by
LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Fig. 4. (a) The magnitude and (b) phase responses in order to investigate
stability of the feedback loop in Fig. 3(a).
Fig. 5. Differential two-stage oscillator circuit with single-stage injection.
that of injection locking (fSL ). The realigning factor (β in [17])
represents the strength of injection locking, which determines
the bandwidth (fSL ). The phase noise at low frequency offset
follows the transfer function (blue line) of data input where its
bandwidth (fPTL ) is bounded by the PTL.
The magnitude and phase response of the feedback loop in
Fig. 3(a) is plotted in Fig. 4 in order to investigate the stability.
It can be noted that regardless of the β variation, the PTL is
unconditionally stable. This is because the phase realignment
function (Hrl (ω)) includes a zero at the origin that cancels out
one of the poles in the loop.
D. Quadrature Phase Generation
The main function of ILO in the proposed receiver is to
convert the differential clock to quadrature phases. This con-
version can be accomplished by injecting recovered clock into
a differential buffer of two-stage oscillator as shown in Fig. 5.
This single-stage injection often incurs phase error between
quadrature phases. The amount of phase error can be quantified
by deriving the phase relationship of fundamental harmonic
voltages at each node with the aid of differential equations and
Fourier series representation [18].
Without any signal injection, the two-stage oscillator oscil-
lates at its free-running frequency (ωF R ) and the phase of each
node is exactly spaced by 90 degree. For the oscillator circuit,
the steady state phase difference can be derived from the char-
acteristic equation of injection locking [18], which is given as
sin Δφ
ωIN J = ωF R ·
1 + RC · ωF R · cos Δφ
485
Fig. 6. Phase error between injection stage and non-injection stage of two-
stage ring oscillator with respect to the normalized injection frequency.
where ωIN J is injection frequency, RC is time constant of
output node, and Δφ is phase difference between the first and
second stages. The solution of this equation becomes
⎛ ⎞
⎜ 1 ⎟
Δφ = sin−1 ⎜
⎝ 
⎟
2 ⎠
(RC · ωF R )2 + ωF R
ωIN J
+ tan−1 (RC · ωIN J ). (5)
The calculated phase error due to the signal injection is plotted
and compared to circuit simulation in Fig. 6. As described
in (5), this phase error is a function of frequency difference
between free-running and injection signals where its quantity
is minimum at ωIN J = ωF R . Circuit simulation matches with
theory within 3% over the locking range. To avoid the use
of additional phase correction circuit, the injection frequency
needs to be kept within a close range of ωF R . In the proposed
receiver, the resolution of CFD is limited within ±10% to keep
the phase error less than 10%.
III. R ECEIVER C IRCUIT I MPLEMENTATION
A. Dual-Functional BPF
For a reliable transmission of DM data over band-limiting
channel, a continuous time linear equalizer (CTLE) is necessary
to compensate for the moderate channel loss [22]. The separa-
tion of the half-rate CM clock is effectively accomplished by
providing a CM gain (or DM rejection gain) within selective
pass band. Note that these frequency bands for data equaliza-
tion and CM clock recovery are close enough that a matched
filter topology can be used to realize a source synchronous
receiver design [13]. In this work, we design a dual-functional
BPF [Fig. 7(a)] where the source nodes of CTLE and CM
amplifier are shared to improve matching and reduce the area
overhead. Since the input dynamic range of the proposed circuit
is bounded by the headroom of Tx driver. Unlike the conven-
tional receiver front-end, no special consideration is required
to improve linearity. The series resistance (rS ) in the source
of CM amplifier prevents DM noise from smearing into CM
(4)
circuit and improves the gain linearity.
486 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016
Fig. 7. (a) Proposed dual-functional BPF topology and (b) its DM and CM
equivalent circuits.
The equivalent circuits for DM and CM amplifiers are shown
in Fig. 7(b). The transfer function of the analog equalizer
includes a zero and two poles. The control voltage (Veqctl )
provides adaptation of the transfer function to the channel con-
dition by tuning DC gain and the position of zero ((RS CS )−1 ).
For the CM amplification, the parallel network (RS and CS ) in
the source nodes can be voltages change in CM. Therefore, the
zero of CM transfer function appears at much lower frequency
where the effective resistance is the output resistance (r0 ) of
the current source.
The sharing of source node for DM (M1 ) and CM (M2 )
amplifiers offers matching advantage in the layout of these am-
plifiers by allowing them placed close to each other. However,
it may cause interference between them through the common
source node. To analyze this effect, the contributions of DM
and CM currents to the source node of amplifiers are also
investigated. The transfer functions of DM and CM equivalent
circuits can be described respectively as
Vdmo −gm1 RL 1 + sRS CS
=   ·
Vdmi gm2
1 + gm1 + 1+gm2 rS 2 RS 1 + sRL CL
1 B. S2D Converter
· (6)
1 +  sRS C S
gm2

RS
1+ gm1 + 1+g
m2 rS 2 In order to convert the single-ended clock from BPF to differ-
Vcmo −gm2 RL 1 + sro CS
≈ ·
Vcmi r0 (gm1 + gm2 + gm1 gm2 rS ) 1 + sRL CL
1 plemented as shown in Fig. 10(a). Two steps of phase splitting
·  (7)
0.5·s(1+gm2 rS )CS
1 + gm1 +gm2 +gm1 gm2 rS
where gm1 and gm2 are transconductances of DM and CM
amplifier respectively. Note that each 1st pole in (6) and (7)
is determined by the load network (RL and CL ), thereby the
peak gain frequencies of both circuits are identical. The effect
of source node sharing affects the DC gain and the 3rd pole
positions [i.e., gm2 terms in (6) and gM1 te rms in (7)]. For
example, when gm1 = 5 mS, gm2 = 15 mS, and rS = 100 Ω,
the DC gain and the 3rd pole of DM and CM gain are reduced
by 24% and 46% respectively. Apparently, DM amplifier with
higher overdrive voltage can affect more intervention onto
the CM circuit. This difference can be further reduced by
increasing the size of M2 at given isolation resistance (rS ). The
simulation results in Fig. 8 exhibit BPF characteristic where the
tunable DC gain of the equalizer is about 5 dB and the peak gain
of the CM amplifier is about 6.5 dB at 3.25 GHz.
Fig. 8. Frequency response of dual-functional BPF circuit.
In the presence of circuit parameter mismatches, the mode
conversion may affect the quality of extracted signal from the
proposed BPF. To analyze this effect, CM to DM conversion
gain (Acmdm) and DM to CM conversion gain (Admcm) are
estimated and compared with DM and CM gains under the
same mismatch condition. For this experiment, one-side of
differential branch (i.e., load resistance and amplifier widths)
in the BPF are assumed to experience 10% mismatch. The
simulation results in Fig. 9 exhibits that mode conversion gains
at 3.25 GHz (Acmdm and Admcm) are well below DM (−18.3)
and CM (−18.2 dB) gains. Note that this simulation assumes
the amplitudes of data and clock signals are same. In practice,
the data signal is larger than the clock signal, so the mode
conversion gain (Admcm) in Fig. 9(b) may increase accord-
ingly. For example, when data amplitude is 3× larger than clock
amplitude, the gain difference of 18.2 dB can be reduced by
about 9.5 dB. The DM and CM gain variations due to above
mismatch condition are small enough (< 0.3 dB).
ential signals, a CMOS single-to-differential (S2D) conversion
circuit on reference to active Balun topologies [23], [24] is im-
are implemented. At the 1st step, the output of common-source
(CS) amplifier M1 is fed to M2 input via Cf so that their output
phases are spaced by 180◦ . Since the output load of M1 is not
matched with that of M2 , their output phases often include the
gain and phase errors. Instead of using imbalanced transistor
sizes and output loads as suggested in [19], the broadband phase
correction technique (M3 − M6 ) is applied to compensate for
the phase error. Even though the gain mismatch at the drain
of M1 and M2 still contributes to the amplitude imbalance at
the output nodes (Vcko and Vckob ), this technique systematically
removes the phase error by averaging [24]. In the proposed S2D
circuit, the gates of M3 and M4 are connected to CS amplifier
outputs (M1 /M2 ) to enhance the gain. A following limiting
amplifier can remove gain mismatches by amplifying the small
signal to rail-to-rail swing. The simulated phase error from
0.5 to 4 GHz frequency range was less than 5 degree and the
voltage gain was about 6 dB at 3 GHz.
LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Fig. 9. The (a) CM to DM and (b) DM to CM mode conversion gain compared to DM and CM gain responses respectively under 10% mismatch in the proposed BPF.
Fig. 10. (a) Active S2D conversion circuit for CM clock and (b) simulated
phase imbalance over 0.5 to 4 GHz range.
Fig. 11. (a) Differential inverting buffer circuit and (b) simulated VCO gain
curve of proposed ILO.
C. Wide-Band ILO
The proposed ILO consists of two differential inverting
buffers to generate four clock phases. A differential buffer
circuit and its characteristic curve are shown in Fig. 11. In the
typical oscillator topology, it is difficult to satisfy wide fre-
quency operation range while keeping small sensitivity to noise
at the same time. This is simply because VCO gain (Kvco )
has to increase to support a wide frequency range operation at
limited control voltage range. To alleviate this constraint, the
VCO operating frequency is often divided into multiple bands
to enable wideband operation while keeping a moderate KVCO
[7], [25]. However, the selection of appropriate frequency band
may require extra calibration steps in the test or add design
complexity of frequency locking loop (FLL). To achieve wide
frequency range and to improve noise sensitivity especially
at high frequency band, the proposed ILO circuit employs an
active inductance load in conventional capacitance-tuned VCO.
487
Fig. 12. Lock range of proposed ILO across data rate of operation.
To keep continuity of circuit operation over the control
voltage (Vf c ), NMOS devices are used to implement the active
inductance (M3 /M4 ) and varactor (M1 /M2 ). The effective
inductance (Leff ) can be approximated as (Rg · Cgs )/gm , if
the transconductance (gm ) of M3 and M4 is large enough.
Variable gate resistance (Rg ) of M3 and M4 , which tunes the
effective inductance (Leff ), is implemented with on-resistance
of the PMOS. Therefore, the high resonance frequency region
(low Vf c ) is dominantly tuned by (Leff · Ct )−1/2 where Ct
represents total capacitance at the output node, whereas the low
frequency portion (high Vf c ) is tuned by (Reff · Ct )−1 where
Reff represents effective output resistance. The simulated Kvco
of high frequency band (0.6 GHz/V) is much smaller than that
of low frequency band (8.4 GHz/V).
The addition of active inductance in the inverting buffer
does not necessarily increase sensitivity to power supply noise,
when it is compared to inverter-based topology whose output
swings from rail to rail. This is because these NMOS transistors
(M3 and M4 ) are operating in saturation region. However, the
bulk of PMOS for the variable resistor (Rg ), if exposed to noisy
power line, may contribute additional path to the output through
Cgs . To alleviate this effect, the bulk of PMOS is isolated from
noisy power line.
As discussed in Section II-B, the lock range of ILO needs to
be large enough to keep the lock state across all data rates of
operation. For this purpose, the size of injection buffer should
be large enough to enable strong injection. The simulated lock
range (Fig. 12) of proposed ILO is more than ±10% of across
488 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

Fig. 13. Proposed delay unit circuit with coarse and fine control DACs.

0.5–3.5 GHz ranges. The narrower range at high frequency is

due to band limiting behavior of injection buffer.

Fig. 14. Bandwidth of CM-to-delay converter with respect to input CM voltage

D. Linearized Delay Line Circuit comparing with typical CS amplifier with PMOS load.
For continuous-rate DPTL, the proposed DCDL employs
adaptive band selection scheme where CFD circuit provides
the coarse digital code (Fcode) and the accumulation counter in
the DPTL provides the fine control code (Pcode) as described
in Fig. 1. Since Fcode represents data rate, the amount of
maximum delay (1UI) is set adaptively with respect to the ILO
frequency. The DCDL consists of four cascaded delay units and
each unit is tuned by two 6-bit DACs as shown in Fig. 13.
In the conventional current-starved delay control, its delay
is inversely proportional to the control current and this non-
linear V-I conversion does not provide a good linearity in the Fig. 15. (a) Linearity comparison between the proposed delay unit and current-
starved delay unit, and (b) total DCDL delay vs. Pcode [5:0] w.r.t. coarse control
control voltage vs. delay relationship [8]. To improve linear- voltage (V f c) sweep.
ity, our delay unit employs CM modulation and CM-to-delay
conversion techniques. In CM modulation, variable pull-down
(M3 ) and pull-up (M4 ) resistors are added in parallel with
inverting buffer (M1 /M2 ) to adjust output CM level. Once the
coarse CM level is set by the pull-down resistance (M3 ) at
given Vf c , the fine tuning of CM level can be linearly controlled
by the pull-up resistance (M4 ) according to the phase tracking
information (Vpc ).
To aid linear translation of the input CM level to the time
constant at the outputs (Vo /Vob ), a differential amplifier with
cross-mirrored load is used for the CM-to-delay conversion.
When a small-signal voltage swing is assumed, the voltage gain Fig. 16. Digitally implemented CFD circuit.
of the converter can be obtained by superposition, which is
 
gmn
· gmp + gmn · (rop //ron ) = 2 · gmn · (rop //ron ) (8)
gmp
where rop and ron represents the output resistance of saturated
short-channel NMOS and PMOS respectively. The 1st term in
(8) represents the gain from the other side amplifier through
cross-mirrored load. The CM gain response of this topology is
as follows: for the increase of CM input (Vcm ), the negative
side gain path through M9 and M10 increase |Vgs | of M8
while Vgs of the NMOS M7 is increased. The increase of
overdrive voltage of the output stage reduces time constant or
increases the bandwidth. To investigate this phenomenon, the
−3 dB bandwidth of output node (Vo ) is simulated according
to input CM level at 4 GHz in Fig. 14. Compared to a typical
CS amplifier with PMOS load, the output bandwidth (or time
constant) of proposed converter is linearly proportional to input
CM voltage. The cross-mirrored load also helps to extend the
dynamic range of operation.
The linearity of delay unit with respect to 6-bit control code
(Pcode) is plotted in Fig. 15(a) and is compared to a conven-
tional current-starved scheme where significant improvement
is exhibited. The extended dynamic range of the proposed
delay unit shown in Fig. 14 offers wide coverage of operating
frequency with a minimal number of delay units. As shown
in Fig. 15(b), at each coarse control voltage (Vf c ), two-stage
delay unit covers less than half-period (1UI) of 1 GHz and four-
stage unit covers less than half-period of 0.4 GHz frequency.
A variable capacitance at CM modulator output is added to
improve the linearity at very low frequency range.
E. Coarse Frequency Detection (CFD) Circuit
The purpose of CFD circuit is to detect the data rate from
the embedded clock to preset the operation range of ILO and
the delayline for the continuous-rate operation. The digitally
implemented CFD circuit and its timing diagram are shown
in Figs. 16 and 17. When a start signal (fdstart) is triggered,
LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Fig. 17. Timing diagrams of CFD circuit when (a) msbr precedes msbv and
(b) two frequencies are close.
divided clocks from the reference (Rck) and free-running ILO
(V ck) drive ring counters asynchronously. The time difference
(Δt) of the rising edges of MSBs (msbr, msbv) represents the
accumulated frequency difference and is proportional to the
length of counting [26]. If the difference is larger than one
period of the divided reference (tp), the latch output changes
its state from initial f up = f dn = 1 to f up = 1 and f dn =
0, setting the up-direction flag of the following accumulation
counter (8-bit) to decrease the ILO frequency [Fig. 17(a)].
At the next rising edge of the divided reference (rckdv), the
reset signal (resetb) is fed back to the ring counters to resume
counting and set the latch output back to the initial state. When
the ILO frequency is close to the reference [i.e., Δt < tp in
Fig. 17(b)], then the time overlap of MSBs generates a pulse
(fdoff_pulse) to stop the loop.
This CFD scheme does not depend on absolute frequency
of operation, thereby exhibiting unlimited acquisition range.
The total accumulated time difference during n count periods
is represented by n ∗ Δte ± Δti /(2N ), where Δte is the time
difference of two clock frequencies in a single counting period,
Δti is the initial phase difference of inputs (Rck, Vck), and
N is the division ratio. If N is large enough, the resolution
of frequency detection can be approximated as tp = n ∗ Δte ,
removing the effect of initial phase difference (Δti ). To keep
the phase error among the quadrature phases less than 10% as
we discussed in Section II-D, the 5-b ring counter (n = 25 )
and the divide-by-16 (N = 16) circuit are used to achieve the
theoretical resolution of 3.1%.
IV. E XPERIMENTAL R ESULTS
The prototype receiver chip was fabricated in a LP 65 nm
CMOS process [Fig. 18(a)]. Total chip area was 0.018 mm2 .
Die chips are assembled on FR4 PCB with chip-on-board
(COB) process [Fig. 18(b)] for the evaluation. In order to
generate test signals for CM-CES, RF power combiners are
used to commonly add the half-rate clock from pulse generator
489
Fig. 18. Photos of (a) the prototype chip and (b) test PCB.
Fig. 19. An eye diagram of the half-rate CM clock-embedded signal for the
test input.
(Agilent 81141A) to each of the differential data from PRBS
pattern generator (Agilent J-BERT N4903A) [13].
The eye diagram of resultant test signal at 6.5 Gb/s data rate
is shown in Fig. 19. Since there is no test equipment generating
input signal for the CM-CES based CDR, we used RF power
combiners to synthesize test signals for the receiver. However,
the use of RF combiners at NRZ signal inevitably suffers from
reflections due to impedance mismatches and causes an extra
deterministic jitter in the eye diagram. The total RMS jitter of
the combined test signal was about 5.16 ps. The data transitions
are out-phased by 90◦ with clock transitions to reduce the data
dependent clock jitter (DDCJ) [13]. This test signal was sent to
the receiver via 5-inch long trace whose attenuation at 3.25 GHz
was about −7 dB.
For the experimental purpose, the operation of proposed
receiver is controlled by 3 sequential steps, i.e., the coarse
frequency detection followed by the injection lock [Injon in
Fig. 2(a)] and the phase tracking [Ptlon in Fig. 2(a)]. The
measured signal spectrums of the recovered clock were shown
in Fig. 20 to exhibit the operation of CFD and the injection
locking. When the frequency detection is successfully accom-
plished (blue), the spectrum exhibits the phase noise of free-
running oscillator where its center frequency is 0.6% off from
the 3.25 GHz injection signal. After the injection locking (red),
the spectrum exhibits a distinct tone at 3.25 GHz where its
phase noise is greatly reduced.
The measured frequency errors (Fig. 21) of CFD were within
the boundaries of lock range (Fig. 12) ensuring proper operation
of ILO across clock frequencies of interest. Beyond 1 GHz, the
frequency error was well within theoretical resolution of 3.1%
imposed by CFD circuit as we have discussed in Section III-E.
490 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016
Fig. 20. The measured signal spectrums of recovered clock after coarse
frequency detection (blue) and injection locking (red).
Fig. 21. Measured frequency error in CFD scheme.
Fig. 22. Measured phase noise of oscillator after injection locking and phase
tracking.
However, the detection error increases at low frequency band.
This is because the resolution of 8-bit counter becomes dom-
inant. For example, the LSB of 8-bit DAC covering 1 V is
3.9 mV per step. Then the frequency resolution is obtained by
3.9 mV ∗ 8.4 GHz/V (Kvco in this region), which is 32.7 MHz
per step. At 800 MHz, this resolution was about 4%.
The phase noise of oscillation frequency at 3.25 GHz was
measured (Fig. 22) to observe the dynamics of injection locking
and phase tracking loop. For the measurement, a test signal
from a pattern generator and power combiners was transmit-
ted via 5-inch FR4 trace to the receiver chip to recover CM
clock and differential data. When the recovered clock signal
was injected into the free-running oscillator (gray dotted line
in Fig. 22), its in-band phase noise was dropped down to
−117 dBc/Hz (blue line). The in-band noise is primarily con-
tributed by the phase noise of injection clock (Linj (ω)). The
Fig. 23. Eye-diagrams of recovered data and clock waveforms at (a) 0.8 and
(b) 6.5 Gb/s.
Fig. 24. Measured clock jitter at 3.25 GHz.
bandwidth (fSL ) of the injection locking was about 200 MHz.
After the injection locking, DPTL was activated to track tran-
sitions of the NRZ data output from the analog equalizer. The
in-band noise (Ldat (f )) at low offset (red line) is about −87 dB
and bounded by DPTL bandwidth (fPTL ) of about 400 KHz.
The measured phase noise profile matches well with the esti-
mation in Fig. 3(b), thus validating the model in Fig. 3(a). The
rms jitter integrated over 10 KHz to 1 GHz after injection and
phase tracking was 2.5 ps and 4.0 ps respectively.
To evaluate the BER performance, the recovered data from
the previous setup was fed back to a BER tester (Agilent
J-BERT N4903A). The proposed CDR circuit was operated
successfully at 0.8–6.5 Gb/s ranges with 231 − 1 PRBS data
pattern satisfying BER < 10−12 . The eye diagrams of recov-
ered data (Fig. 23) exhibit RMS jitter of 35.3 ps and 5.06 ps at
0.8 Gb/s and 6.5 Gb/s respectively. The RMS and peak-to-peak
jitter of recovered clock at 3.25 GHz was 4.04 ps and 38.2 ps
respectively (Fig. 24).
The bathtub curve of proposed CDR circuit was measured by
sweeping the phase of combining clock from the pulse genera-
tor with open DPTL. At 6.5 Gb/s data rate, more than 0.4 UI
of sampling margin was obtained for both the even and the
odd data outputs at BER = 10−11 criterion as shown in Fig. 25.
LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Fig. 25. Measured bathtub curves at 6.5 Gb/s.
TABLE I
T HE P OWER B REAKDOWN OF P ROTOTYPE C HIP
Fig. 26. The sensitivity of the receiver BER to the data and clock amplitude of
the transmitter output.
The power breakdown from post-layout simulation (within 5%
error from measurement) at 6.5 Gb/s is summarized in Table I.
At 1.2 V supply, the power efficiency was 2.4 mW/Gb/s.
To assess the feasibility of the proposed signaling, the
sensitivity of the receiver performance to the data and clock
amplitudes of the transmitter output was evaluated at 6.5 Gb/s
data rate (Fig. 26). In this experiment, 5 FR4 trace was used
to connect the receiver chip. When the data amplitude is given
to be a small value (< 100 mV), BER is limited only by
the data amplitude and the increase in clock amplitude no
longer affects the performance. When the data amplitude is
larger than 100 mV, the increase of clock amplitude improves
BER. This is primarily because the improved clock to data
amplitude ratio reduces DDCJ incurred by the interference from
the data transition edges in the recovered clock [12]. This also
implies that larger clock amplitude is needed to maintain the
same BER when the data amplitude increases. Secondly, larger
clock amplitude allows stronger injection into the oscillator
increasing ILO’s bandwidth that results in low jitter generation.
491
Fig. 27. The eye diagram of receiver input signal at the minimum transmitter
headroom condition (VHR = 155 mV).
Fig. 28. The RMS jitter of the proposed ILO across data rate to show the effect
of Kvco change.
When clock amplitude is small (< 100 mV), the BER become
a function of data amplitude. In this case, a higher amplitude
ratio of clock to data could result in better BER. The minimum
amplitude ratios of clock to data satisfying BER = 10−12 are
presented as numbers enclosed with quadrilateral.
For a given transmitter headroom (VHR ), the operation re-
gions satisfying three BER criteria were plotted using dotted
lines. If the transmitter headroom is larger than 200 mV, the pro-
posed signaling scheme secures enough operating margin that
satisfies the BER = 10−12 criterion. The minimum headroom
of the transmitter (VHR = 155 mV) satisfying BER = 10−12
actually corresponds to the minimum receiver sensitivity. The
eye diagram (Fig. 27) of received input signal through a 5 FR4
trace at this condition is showing that the minimum receiver
sensitivity is about 20 mV.
The jitter performance of the proposed ILO across data rate
was measured to investigate the effect of change in Kvco value
as discussed in Section III-C. Even though there are other
factors that affect the output jitter of ILO such as injection
strength variation across clock frequency and band-limiting
delay line, we can still see the effect of decreasing VCO gain as
data rate increases (Fig. 28).
The performance of prototype chip is compared with similar
signaling (CM clock embedded) schemes in Table II. The pro-
posed CDR circuit consumes the lowest power and area. Com-
pared to reference-less CDR designs in the literatures (Table III),
the proposed CDR achieved wider frequency range with a
single VCO band, lower jitter, and better power efficiency.
492 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016
TABLE II
P ERFORMANCE C OMPARISON W ITH R ECEIVERS
H AVING S IMILAR S IGNALING
TABLE III
P ERFORMANCE C OMPARISON W ITH R EFERENCE -L ESS
CDR S P UBLISHED IN THE L ITERATURE
V. C ONCLUSION
A reference-less half-rate CDR architecture that utilizes
CM-CES and injection locking technique has been explored
to alleviate design complexity for high accuracy bit rate de-
tection and quadrature phase generation. The use of wide-
band ILO greatly suppresses oscillator phase noise while
the narrowband DPTL reduces steady state jitter. To achieve
continuous-rate and wide range operation, four circuit tech-
niques have been explored: 1) a VCO topology with tunable
active inductance reducing its gain at high oscillation frequency,
2) a wide range DCDL with adaptive range control scheme,
3) a linearized delay control unit with CM-to-delay conversion
technique, and 4) a digitally implemented CFD scheme to
drive free-running VCO toward injection locking. A proto-
type chip has been fabricated in low-power 65 nm CMOS
process. The feasibility of proposed scheme has been proved
by successfully detecting 0.8–6.5 Gb/s data rates over 5-inch
FR4 trace with 231 − 1 PRBS pattern satisfying BER < 10−12 .
Compared to previously published reference-less CDR circuits
in the literature, the proposed design exhibits wider data-rate
range with a single VCO band, lower jitter, and better power
efficiency.
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LEE AND SIM: A 0.8-TO-6.5 Gb/s CONTINUOUS-RATE REFERENCE-LESS DIGITAL CDR
Kyongsu Lee (M’12) received the B.S. degree in
electronic engineering from Kyungpook National
University, South Korea, in 1987, M.S. degree
in electronic engineering from Sogang University,
South Korea, in 1989, and the Ph.D. degree in elec-
trical engineering from the University of Southern
California, Los Angeles, CA, USA, in 2005.
From 1989 to 1998, he was a Senior Research En-
gineer at Hynix Semiconductor, South Korea, where
he worked on high performance digital/analog Macro
IP designs. From 1998 to 2000, he was a Senior IC
Design Engineer at Synopsys, USA, working on full-custom memory circuit de-
signs. From 2006 to 2010, he was a principal engineer at Samsung Electronics,
South Korea, where he worked on DDR3 SDRAM I/O circuits and serial-
links for memory interface circuits. From 2010 to 2013, he was a Postdoctoral
Researcher at Pohang University of Science and Technology (POSTECH),
South Korea, where he worked on analog/digital circuits for the high-speed
links. Since 2013, he has been a Research Professor in Inha University, Incheon,
South Korea. His research interests include high-speed serial/parallel links and
low power RF telemetry circuits for the biomedical devices.
493
Jae-Yoon Sim (M’02–SM’13) received the B.S.,
M.S., and Ph.D. degrees in electronic and electrical
engineering from Pohang University of Science and
Technology (POSTECH), Pohang, South Korea, in
1993, 1995, and 1999, respectively.
From 1999 to 2005, he was a Senior Engineer
with Samsung Electronics, South Korea. From 2003,
to 2005, he was a Postdoctoral Researcher with the
University of Southern California, Los Angeles, CA,
USA. From 2011 to 2012, he was a Visiting Scholar
with the University of Michigan, Ann Arbor, MI,
USA. In 2005, he joined POSTECH, where he is currently an Associate
Professor. His research interests include high-speed serial/parallel links, PLLs,
data converters, and power module for plasma generation.
Prof. Sim has served on the Technical Program Committees of the IEEE
International Solid-State Circuits Conference (ISSCC), Symposium on VLSI
Circuits, and Asian Solid-State Circuits Conference (ASSCC). He received
Special Author-Recognition Award at ISSCC 2013 and was a co-recipient of
the Takuo Sugano Award at ISSCC 2001.