A 18.

6 fJ/bit/dB Power Efficient Active

Inductor-based CTLE for 20 Gb/s High Speed Serial
Link
Deepanraj Thulasiraman, Chiranjeevi G N Javed S Gaggatur, K S Sankara Reddy
Department of Electronics and Communication High Speed Circuits Group
PES Institue of Technology, South Campus, Terminus Circuits Pvt Ltd
Bengaluru, 560100, Karnataka, INDIA Bengaluru, 560094, Karnataka, INDIA

Abstract—A low-power receiver front end (RFE) for a high

speed serial interface with a 3-stage continuous time linear
equalization (CTLE) was designed in 28nm CMOS technology.
The CTLE uses a transconductance-based active inductor for
high frequency operation and for area reduction. The active
inductor can be tuned around 10 GHz while consuming 11.17 mW
from 0.9 V power supply. The CTLE compensates about 19.5 dB
of attenuation due to the channel at a data rate of 20 Gb/s
per link, with a power efficiency of 18.6 fJ/bit/dB, nearly 4X
better power efficiency than the previous works reported in the
literature. It shows prominence in the receivers used for wireline
I/O interfaces like USB 3.2 and PCI Express 4.0.

I. I NTRODUCTION Fig. 1: Block Diagram of a typical high speed serial link

transceiver with the channel characteristics (inset) [3] for
In modern day communications systems consisting of mul- known data rates of 3.125 GHz to 12.5 GHz.
tiple integrated circuits (IC), high-bandwidth communication
between these ICs, e.g. between the high-performance micro-
processors, computer servers and large storage devices, is one
the most critical design issues that the engineers face. With
the continuous scaling of feature sizes in the chip manufac-
turing technology, the speed of on-chip data processing as
well as integration have scaled, but the packaging has not
scaled at the same rate limiting the interconnect bandwidth.
The limitations imposed by the electrical channel (channel
noise and attenuation in the received signal) are increasing
in significance as per I/O data rates, Fig. 1. A significant
contributor to this effect is that the dielectric and resistive Fig. 2: Basic concept of equalization is to compensate the high
losses of the printed circuit board (PCB) traces increase frequency attenuation by the channel
as the operation frequency increases [1]. At speeds of tens
of gigabits per second, the loss on FR4 or Rogers boards active-inductor topologies for high speed designs. Section III
pose a great challenge, requiring heavy equalization. From discusses the circuits design of the proposed modified active-
the circuit point of view, it is simpler to employ the linear inductor and the simulation results are discussed in Section IV.
equalization in transmitter (TX) and receiver (RX), consider Section V summarizes and concludes the paper.
noise amplification and cross talk (XT). Some of the popular
equalization techniques include Feed Forward Equalizer (FFE)
used in TX and Continuous Time Linear Equalizer (CTLE) and II. P RINCIPLE OF E QUALIZATION
Decision Feedback Equalizer (DFE) in RX. The Inter-symbol A. Basics of Equalizers
interference (ISI) can be effectively reduced by the DFE, but
the circuit becomes complex for high speeds. At higher speeds, The equalizers compensate the channel bandwidth limi-
the received signal strength after the channel gets attenuated tations of signal attenuation at high frequencies and signal
to about 32 dB at 8 GHz (PCI Express) [2]. spread, by adding the inverse frequency response of channel
and consequently, removing the effects of ISI. The inverse fre-
On the other hand, CTLE can compensate full frequency quency response is obtained by amplifying the high frequency
band and does not require clock signals. This paper describes components to compensate the channel loss, as shown in Fig. 2.
the design of CTLE using active inductor load for bandwidth The receiver equalization can be classified as linear and non-
extension. The rest of the paper is organized as follows: linear equalization. The linear equalizers have finite impulse
Section II describes the principle of equalization and the response, and have a feed forward structure where the equalizer
978-1-7281-2472-8/19/$31.00
c 2019 IEEE output is not fed back to its input. The non-linear equalizers

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 (a)
(b)

Fig. 3: Continuous Time Linear Equalization for SerDes Receiver: (a) with resistive load (b) with passive inductor load.

have infinite impulse response, and have a feedback structure

where the equalizer output is fed back to its input. This type of
equalizers are used when there is a severe channel distortion,
and mainly used in removal of ISI. The linear equalizers are
further classified as discrete time linear equalizer (DTLE) and
continuous time linear equalizer (CTLE).
The DTLE are constructed on FIR structures, and requires
clocks recovered from the received data. And thus a clock
and data recovery (CDR) circuit is required. As data rate
increases the number of taps in FIR increases, due to which
the circuit becomes complex and consumes more power. This
codependency of CDR and high power consumption can be
eliminated by using CTLE. The CTLE is a simple structure
and hence comparably consumes less power.
Fig. 4: Tunability of CTLE: The peaking frequency, f0 reduces
B. Continuous Time Linear Equalizer as CS increases and the DC gain decreases with the increase
of RS .
The structure of traditional CTLE is source degenerated
differential pair as shown in Fig. 3a where the gm is the
transconductance of input transistors, RD and CL are load The pole and zero frequency values can be adjusted by
resistance and capacitance, RS and CS are source degeneration varying the RS and CS values. Increasing RS moves zero to
resistance and capacitance. This circuit is two pole and a zero lower frequencies thus reducing DC gain and increasing CS
system, which provides peaking at Nyquist frequency. The zero moves zero and first pole to lower frequencies as shown in
gives a +20dB/decade slope and a pole gives -20dB/decade, Fig. 4. However, this topology suffers from bandwidth limi-
thus in total this circuit gives -40dB/decade. The transfer tations and thus, lacking compensation at higher frequencies.
function is given as [4], This problem was rectified by using inductor load as shown in
Fig. 3b. The addition of inductive load increases the bandwidth
of the CTLE by inductive peaking at Nyquist frequency [6].
1
s+ The transfer function of the inductive load CTLE is given
gm R CS
H(s) = !S (1) by,
CL 1 + gm2RS

1 s s
s+ s+ 1+ 1+
RS C S RD C D gm RD ωZ1 ωZ2
H(s) = . . (4)
gm RS 1 + s
   2
gm s + ωZ 2ζ s
H(s) = (2) 1+ ω 1 + s +
CL (s + ωP 1 )(s + ωP 2 ) 2 P 1 ωn ωn2
where where
gm RS   s  s
1 1+ 1 RD CD 1
ωZ = ωP 1 = 2 ωP 2 = (3) ωZ2 = 2ζωn ; ζ = ; ωn = (5)
RS C S RS C S RD C D 2 LD (CD LD )

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 (a)
(a) Traditional Gyrator-C

(b)

(b) Gyrator-C equivalent circuit Fig. 6: Wu Folded active inductor, a) nMOS and pMOS
implementations [5], (b) Small signal equivalent circuit of
Fig. 5: The traditional Gm-C circuits with its small signal nMOS version of Wu active inductor [7].
equivalent [5], [6].

is given by,
C. Folded Transconductance-based Active Inductor
The equation of Yin can be represented by a RL circuit
The active inductor can be realized by the traditional [7], where
Gyrator-C topology [5], [7] as shown in Fig. 5a, where
the Gm1 , Gm2 and GO1 , GO2 are linear transconductance RCgs 1
and their corresponding output conductance respectively, and RP = R; L = ; RS = (9)
1 1
C1 , C2 are port capacitances. At frequencies less than the self- gm − gm −
R R
resonance, the input impedance Zin is equivalent to the passive
circuit shown in Fig. 5b, For the transconductance gm to behave as an inductance
C1 L, at the desired frequency of 10 GHz, it has to satisfy the
L = ; CP = C2 (6) 1
Gm1 Gm2 condition gm < (Fig. 6b). The next section discusses
GO1 1 R
R1 = ; RP = (7) the design and implementation of the active inductor and the
Gm1 Gm2 GO2 CTLE.

In order to attain high frequency operation, the Gm1 and

Gm2 are realized using single-transistor amplifiers, such as
common source (CS), common gate (CG) and common drain
(CD) stages and their intrinsic capacitances acts as C1 and
C2. The CS stage offers negative transconductance and the CG
and CD stages offers positive transconductance. Hence a single
ended grounded active inductor can be implemented by using
CS-CG stages or CS-CD stages [5], as shown in Fig. 6a. The
parameters of the RLC equivalent circuit are derived from the
small signal equivalent circuit of the nMOS version, as shown
in Fig. 6b.
The input impedance is given as,

sRCgs + 1
 is replaced with an active inductor, a PMOS current-reuse
Zin =
sRCgs + gm
1 penalty in the phase noise. The value of the inductance for the
From Zin , we notice that zero frequency ωz = and pole
RCgs
gm
frequency ωP = . And similarly the input admittance, Yin
Cgs
III. C IRCUIT D ESIGN
In high frequency circuit design, passive inductors are used
to increase the selectivity of the signal and act as a tuned
load [8]. Fig. 3b shows an implementation of a CTLE using
passive inductors as the load. The Q-factor and the selectivity
is high due to the usage of a passive inductor, but at the cost
of large area and less tuning range. As the design integration
is getting easier with scaling of the feature sizes of the CMOS
technology, area comes at a premium. The CTLE topology in
Fig. 3b consumes more area due to the use a passive inductor.
To make the CTLE area efficient, the passive inductor
(8) transconductance. The proposed alternative solution saves the
chip area and also increases the bandwidth, with a minor
desired frequency (10GHz) can be tuned by the RD transistor
and the inductance range is given by (9), that depends on the
gm and RD values.

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 Fig. 7: The proposed area-efficient active inductor load-based 3-stage continuous time linear equalization (CTLE) for 20 Gb/s
high speed serial link receiver (HSS-RX) including the tunable resistors RS and RD and the capacitor filter bank CS . The three
stage CTLE is designed to compensate 18 dB out of 30 dB of the channel attenuation occurring at 10 GHz.
The proposed CTLE is designed in 28 nm low power
CMOS technology and the simplified schematic is shown in
Fig. 7. The input transistors M1 -M2 in the first stage, provide
the peaking and DC gain along with the active-inductor based
load M3 -M4 -RD . In order to provide increased gain for the
high frequencies (7GHz to 10GHz), an additional peaking
amplifier stage is implemented by a cross coupled nMOS pair
M5 -M6 , and also a RS0−S2 , RD0−D1 and CS0−S1 banks are
added and rearranged to provide better performance and while
consuming less power. The RS and RD are realized by the
drain to source resistance (RDS ) due to the voltage applied
at the gate. Digital tuning is provided to control the gain and
peaking frequencies which allows the circuit to be tuned during
post-silicon operation.
IV. R ESULTS AND D ISCUSSIONS
Fig. 8: The simulation testbench to measure the performance of
the receiver equalizer using PRBS7 data as input, fed through
the channel (FR4 s-parameter model) having 30 dB attenuation
at 10 GHz frequency and an input terminated receiver front
end.
Fig. 8 shows the simulation testbench for the DUT (CTLE)
where TP1 and TP2 are the test probe points for the input and
output of the DUT, respectively. The far end of the channel
at the receiver is terminated with a resistance of 50 Ω. The
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channel is expected to have as low-pass characteristic, with the
high frequency compenents of the signal getting attenuated and
the low frequency signal not facing any attenuation, as shown
in the upper half of Fig. 9a.
The lower half of the Fig. 9a shows the equalized serial
data with the high frequency components having a boost in
the gain with the low frequency signals attenuated to match
the gain of the high frequency components.
Some of the observed features of the design are:
1) Fig. 9b shows the CTLE gain across all PVT corners
where the peak gain ranges from 2.88 dB to 7.3 dB
for a frequency range of 10 GHz to 20 GHz and the
DC gain spread of 2.5dB.
2) The DC gain tunability of 2.5dB, while keeping the
peaking frequency constant, the design is achieved by
varying RS , as shown Fig. 10a.
3) The peak gain tunability by RD gives a gain
variation from 5.5 dB to 9.5 dB at 10 GHz, keeping
the DC gain constant, is as shown in Fig. 10b.
Fig. 11a and Fig. 11b show the eye-diagrams of the
received signals at a data rate of 20 Gb/s before and after
the CTLE. Refer Fig. 8 for the test probe points T P 1 and
T P 2. It can be observed that the amplitude difference between
the high frequency and low frequency components have been
equalized to maintain the same amplitudes, thereby increasing
the eye height and width and reducing the jitter at the signal
crossovers.
Compared with the other recent works given in Table I, the
performance of the proposed active-inductor based CTLE for
20 Gb/s receiver compensates a higher loss in the channel and
without any eye monitoring circuit. The figure of merit (FoM)
is defined as
T otalP ower
F oM = (10)
DataRate ∗ ChannelLoss
 (a)
(b)

Fig. 9: (a) Transient simulation of a typical high speed serial link receiver with the pre- and post-CTLE outputs. The high
frequency symbols are seen with a higher gain than the low frequency symbols and, (b) CTLE gain for high frequencies across
PVT corners with the maximum low frequency attenuation of 2.5 dB and the peaking gain centered between 10 GHz and 20 GHz,
for a given tuning configuration.

(a) (b)

Fig. 10: Gain for different tuning configurations for a typical corner of operation (a) DC gain controlled by RS having a range
of +0.5dB to -5dB (b) Peaking gain controlled by RD having a range of 5.5dB to 9.5dB. The shift in the peaking frequency is
due to the parasitic capacitance of the switches added to the load capacitance CD .

The proposed figure of merit normalizes the channel loss, TABLE I: Performance Comparison.
transmission data frequency, and power consumption, which
compares the system performance under the same evaluation References [9] [10] [4] This Work
index, and can make a more comprehensive measurement Technology 65nm 65nm 28nm 28nm
Equalization DFE CTLE+DFE CTLE CTLE
[4]. The active-inductor peaking technology expands the com- Adaptation YES YES YES NO NO
pensation ability of the equalizer, which can achieve the Data Rate (Gb/s) 10 10 1.25-12.5 10 20
signal frequency range to 20 Gbps, and channel losses range Channel loss (dB) 16.2 25 6-21 16.2 30
Supply (V) 1.2 – 0.9/1.8 0.9 0.9
from -24 dB to -30 dB. The FoM of the equalizer, with a
Power (mW) 24 66 12 4.1 11.17
power efficiency of 12.6 fJ/bit/dB is clearly superior to the FOM (fJ/bit/dB) 148 264 46 25.3 18.6
other designs, which means that this design achieves better
compensation ability for same data rate.
V. S UMMARY AND C ONCLUSION
This paper shows the implementation of a continuous time
linear equalizer for a 20 Gb/s high speed serial link receiver

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 (a)
Fig. 11: Eye Diagrams as seen at the 20 Gb/s receiver (a) Before CTLE (TP1) (b) After CTLE (TP2), in Fig. 8
with an area efficient active-inductor load. In high speed
serial receivers, inductors are used in CTLE to enhance the
bandwidth of operation, but the passive inductors consume
more chip area. In this work, the passive inductors are replaced
by active inductors for area efficiency and tunablity in the in-
ductance value at the desired frequency. The CTLE is designed
and implemented in 28 nm low power CMOS technology,
with a supply voltage of 0.9 V and power consumption of
4.1 mW for single stage CTLE and 11.17 mW for complete
3-stage CTLE. The CTLE compensates 19.5 dB due to the
channel with a power efficiency of 18.6 fJ/bit/dB, nearly
4X better power efficiency than the previous works reported
in literature. The proposed CTLE shows prominence in low
power implementations of receivers for high speed wireline
I/O interfaces like USB 3.2 and PCI Express 4.0 and above.
ACKNOWLEDGEMENT
The authors would like to thank the members of Terminus
Circuits Pvt Ltd for the technical discussions and the manage-
ment of the PESIT-South Campus for allowing the internship
in Terminus Circuits Pvt Ltd.
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