Microelectronics Journal 114 (2021) 105155

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Input-resistance reduced gm-boosted common-gate transimpedance

amplifier for 100 Gb/s optical communication☆
Joseph Chong, Fariborz Lohrabi Pour *, Dong Sam Ha
Multifunctional Integrated Circuit and System (MICS) Group, The Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24060,
USA

A R T I C L E I N F O A B S T R A C T

Keywords: This paper proposes a transimpedance amplifier (TIA) for a 100 Gb/s optical receiver. The proposed TIA adopts a
gm -boosted gm-boosted common-gate input stage with a diode-connected transistor, which lowers the input resistance
gm-boosted common-gate amplifier (GBCG) resulting in a high input pole frequency. It was designed and fabricated in 32 nm CMOS SOI technology. Mea­
optical communications
surement results indicate that the TIA achieves a bandwidth of 74 GHz and a transimpedance gain of 26 dBΩ
Optical receiver
Transimpedance amplifier (TIA)
while dissipating 16.5 mW under 1.5 V supply voltage. The bandwidth of the proposed TIA is larger by 48% or
more when compared with state-of-the art TIAs.

1. Introduction can be a common-source amplifier with a feedback resistor [4,5,10], its

AN ever increasing network traffic pushes higher data rates for
backbone optical networks. The contemporary Ethernet achieves the
data rate of 100 Gb/s with parallel channels or a single channel utilizing
four-level pulse-amplitude-modulation (PAM-4) [1]. This work proposes
a transimpedance amplifier (TIA) for a future application of a single 100
Gb/s channel with non return-to-zero (NRZ) signals. At the input of a
fiber optics receiver, the photodiode converts an optical signal into an
electrical signal, and the TIA amplifies it into a voltage signal. The
performance of the entire receiver chain is sensitive to the bandwidth
and noise of a TIA. As CMOS technology is able to integrate the receiver
front-end with signal processing blocks such as equalization and error
correction, CMOS TIAs have gained attention in open literatures.
State-of-the-art CMOS TIAs aim for optical network systems with a 40
Gb/s data-rate, in which the rule-of-thumb required bandwidth is 28
GHz [2–9].
The photodiode capacitance (CPD) plays a major role in determining
the bandwidth of a TIA. The capacitance ranges from 50 fF to 200 fF for
high speed design [2,3], which is relatively large compared with other
parasitic capacitances. The input pole due to CPD and the input resis­
tance mandate a low input-resistance TIA topology to achieve high
receiver bandwidth. Candidate CMOS TIA topologies include
closed-loop topologies and open-loop topologies. A closed-loop topology
fully differential structure [11] or an inverter-based amplifier with a
feedback resistor [6,7]. An open-loop topology can be a gm-boosted
common-gate amplifier (GBCG) [3,8] or its variants [9]. The three to­
pologies are shown in Fig. 1, where Rf and RD denote the feedback
resistor and the drain resistor, respectively. Other less commonly used
topologies include an open-loop common source amplifier with π-type
inductor/resistor load [12], and a closed-loop current-mirror-based
amplifier [13].
The input impedance and the gain of closed-loop topologies depend
on Rf, and hence, the gain and bandwidth is directly traded. A lower Rf
leads to a higher pole frequency at the input node for higher bandwidth,
at the cost of lower gain. In contrast, a GBCG amplifier has a low input
resistance associated with the transconductance gm of the transistor,
which enables the topology to reduce the input resistance without
directly trading it with the gain. This indicates that a GBCG amplifier is a
good candidate for high speed applications. This architecture is also
commonly referred to as regulated cascode (RGC) [14], although the
input and output dictates that it is not a cascode amplifier. It is named as
regulated common-gate in the work by Silva and Oliveira [15], and
named as GBCG in several works [16,17].
The auxiliary amplifier of a GBCG amplifier results in a boosted
equivalent transconductance and lower input resistance. Examples of
TIA operate above 20 GHz with the GBCG topology include a TIA with

☆
This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No.B0101-
15-0024, Terabit optical-circuit-packet converged switching system technology development for the next-generation optical transport network).
* Corresponding author.
E-mail addresses: cjoseph8@vt.edu (J. Chong), fariborzlp@vt.edu (F.L. Pour), ha@vt.edu (D.S. Ha).

https://doi.org/10.1016/j.mejo.2021.105155
Received 11 December 2020; Received in revised form 24 March 2021; Accepted 28 June 2021
Available online 12 July 2021
0026-2692/© 2021 Elsevier Ltd. All rights reserved.
J. Chong et al. Microelectronics Journal 114 (2021) 105155

26 GHz bandwidth implemented in 65 nm CMOS technology by Bashiri

and Plett [3], and a 38 Gb/s to 43 Gb/s receiver fabricated in 65 nm
CMOS presented by Chen et al. [8]. This paper presents a GBCG based
CMOS TIA intended for high speed and short distance communications
between network servers with the target data rate of 100 Gb/s. The key
idea of the proposed TIA is a diode-connected bias stage. The proposed
TIA is fabricated in 32 nm CMOS SOI technology, and the measurement
results indicate that the TIA achieves gain of 37 dBΩ and bandwidth of
74 GHz, enabling the data rate of 100 Gb/s. To our knowledge, it is the
first CMOS TIA to achieve the data rate of 100 Gb/s. Simulation results
of an earlier version of the proposed circuit is presented in Ref. [18], and
this paper presents measurement results with additional analysis.
The paper is organized as follows. Section 2 reviews the basic
operation of GBCG TIAs, and analyzes the effect of an input inductor and
an auxiliary amplifier to the bandwidth. Section 3 presents operation
and analysis of the proposed TIA. Section 4 shows measurement results
and compares its performance with other state-of-the art TIAs.

2. Operation principle of a gm-boosted common-gate amplifier

A GBCG amplifier shown in Fig. 2 (a) consists of a common-gate

amplifier M1 with load resistor RD biased with a current source MB,
and a feedforward auxiliary amplifier formed by MX and RX. A photo­
diode is modeled as an input current iIN and a capacitance CPD of 50 fF.
Fig. 2 (b) shows the small-signal equivalent circuit. The model omits
output resistances of the transistors assuming that it is much larger than
resistors RD and RX, and parasitic capacitances other than CGS and CPD
are ignored assuming that it plays a minor role in the frequency
response.
For a conventional common-gate amplifier, the transconductance is
gm = iD/vIN. Through small signal analysis of the circuit shown in Fig. 2 Fig. 2. (a) A conventional GBCG amplifier, and (b) its small-signal equiva­
(b), the auxiliary amplifier boosts the equivalent transconductance to lent circuit.
result in GM = gm1(1 + gmXRX). The transimpedance gain ZT is:
related to the transconductance and the input capacitances. The
vOUT 1
ZT = = RD ⋅ s , (1) decoupling of gain with bandwidth at the input is beneficial for high
iIN 1 + (1 + η) 2
speed applications.
ωi +ωsx ω
i
To further analyze the main contributor to the bandwidth at the
where input node, (1) can be expressed as
CGS1 1
η= (1 + gmX RX ) (2) ZT = RD ⋅ 2, (5)
CPD + CGS2 1 + ω0sQ0 + ωs 2
0

ωi = GM /(CPD + CGS2 ) (3)

where
√̅̅̅̅̅̅̅̅̅̅
ωx = 1/RX CGS1 (4) ω0 = ωx ωi , (6)

and CGS2 is the gate to source capacitance of MX. Equation (1) shows that and
the gain of the TIA is equal to the drain resistor, while the bandwidth is

Fig. 1. Commonly employed TIA typologies for high speed receivers: (a) a common-source amplifier with a feedback resistor, (b) an inverter-based amplifier with a
feedback resistor, and (c) a gm-boosted common-gate (GBCG) amplifier.

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J. Chong et al. Microelectronics Journal 114 (2021) 105155

1
Q0 = √̅̅̅̅. (7)
ωx
1+η ωi

√̅̅̅
Assume maximally flat response by setting Q0 ≤ 1/ 2, the band­
width is equal to the frequency in which |ZT| = RD/2 and can be obtained
as follows.
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
1 1 gm1 gmX
BW ≤ √̅̅̅̅̅̅̅̅̅̅ . (8)
2π ωx ωi ≈ 2π CIN CGS1

where CIN is the equivalent input capacitance. Expression (8) gives the
bandwidth limit, and shows that the bandwidth depends on the capac­
itance of the photodiode and the fT of the transistors M1 and MX. It in­
dicates that a wide bandwidth can be achieved by optimizing both the
pole ωi at the input node and the pole ωx at the drain of MX. Larger bias
current of M1 or MX increases gm, and thus increases the frequency of
those poles, but causes a larger voltage drop on the drain resistor RD,
resulting in lower voltage headroom. Larger bias current also requires
larger transistor, which may be undesirable due to larger capacitance.
When the output capacitance CL is included, the effect of the pole due
to RD and CL (Note ωout = 1/RDCL) can be appended to (1) and is given
below.
1 1
Z T = RD ⋅ ⋅ . (9)
1 + s/ωout 1 + (1 + η) ωs + ωs2ω
i x i

In most cases, ωi and ωx are much smaller than ωout, and hence the
Fig. 3. The proposed TIA with the buffer stage: (a) circuit diagram, (b) small-
bandwidth of ZT is more sensitive to the poles of ZIN.
signal model of the main TIA.
The noise performance of a TIA plays a major role to the sensitivity of
a receiver to the input signal. By including the thermal noise of resistors
RD and RX, and the channel noise of transistors M1, MX and MB, the input- C′′IN = CPD + CGSX + CGSB , (13)
referred noise is
and
i2n,IN ≈ i2n,MB + i2n,RD
(10) Gm + gmB
( ) (R 1
) γ= . (14)
+ i2n,RX + i2n,MX ⋅
X
⋅ Gm
roB 1 + AX
Expression (11) indicates that the resulting ω′′i increases by a factor of
where AX = gmX RX . The expression indicates that the major contributors γ compared with ωi in (1), assuming CPD being much larger than CGS of
to the noise are the current source MB and the resistor RD, and the noise MB. The diode-connected transistor MB lowers the input impedance and
can be reduced slightly with higher roB and AX. hence increases the pole frequency at the input node. Although the gain
ZT decreases by a factor of γ, it is not a major issue for the target
3. Proposed TIA with a diode-connected input stage application such that short distance communications between network
servers. In fact, we proposed a scheme to recover the gain by feeding the
3.1. Gain analysis output of the auxiliary amplifier to another stage in Ref. [18].
Fig. 4 compares the calculated ω′′i to one of a conventional GBCG,
To improve the frequency response, the input stage of a GBCG where CPD is set as 200 fF. For the proposed circuit implemented in 32
amplifier is modified as shown in Fig. 3 (a). The GBCG amplifier is nm SOI CMOS technology, the values for gm and CGS is set as 30 mS and
composed of a CG amplifier M1 with a resistive load RD and an auxiliary 31.25 fF, respectively, and the fT is normalized as one. The ωi of the
amplifier composed of MX, MY, and RX. The cascode configuration for
the auxiliary amplifier aims to reduce Miller effect of CGDX at the input.
The key idea is that by modifying the current source MB into a diode-
connected one, the impedance seen at MB becomes lower and there­
fore improves the frequency response at the input.
The small-signal model shown in Fig. 3 (b) is helpful to understand
its low frequency operation and compare it with a conventional GBCG.
The diode-connected MB is represented as an equivalent resistor 1/gmB.
The resulting ZT of the main TIA is obtained as
RD 1
ZT = ⋅ ( ) , (11)
γ gmB 1 2
1 + 1 + η + CIN ⋅ωx ωs′′ + ωxsω′′
i i

where
Gm
ω′′i = ⋅γ, (12)
C′′IN

Fig. 4. Comparison of the calculated input pole frequency.

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J. Chong et al. Microelectronics Journal 114 (2021) 105155

conventional GBCG is normalized as one. It can be observed that the

advanced 32 nm SOI CMOS technology improves the input pole by
roughly 13%, compared to a technology with half of the fT. On top of
that, the diode-connected topology further improves the frequency
response by 13% compared to a conventional GBCG amplifier with the
same technology.
The proposed circuit includes a shunt inductor LX to boost the fre­
quency response of the auxiliary amplifier, and a series inductor LD to
extend the output node 3-dB frequency of the output node. LX introduces
a zero and a pole resulting in a third order function. Fig. 5 compares the
bandwidth of the proposed TIA and a conventional GBCG amplifier. The
proposed TIA, with the aid of the diode-connected MB and the shunt
inductor LX, increases the bandwidth by about 40% compared with a
conventional GBCG amplifier. As illustrated in the figure, the inductance
of LX should be set properly for the proposed TIA to avoid excessive gain Fig. 6. Low frequency circuit model with noise sources of the proposed TIA.
peaking, resulting reduction of the bandwidth.

3.2. Noise analysis

Fig. 6 shows the low frequency equivalent schematic of the proposed

TIA for noise analysis. The thermal noise of resistors and transistors are
included for noise analysis in the model, and inductors are shorted. The
input-referred noise is obtained as
( )2
gmB
i2n,IN ≈ i2n,MB + i2n,RD ⋅γ2 + i2n,M1 ⋅
gm1 (1 + AX )
( )2 (15)
gmB RX
+(i2n,RX + i2n,MX )⋅
1 + AX
Compared to the noise level in (10), the noise of the proposed design Fig. 7. The buffer stage with a single-ended output.
is higher in two aspects. First, noise from M1 cannot be ignored due to
the lower source resistance 1/gmB. Second, the noise from RD is larger by the last stage from loading the main TIA. In actual applications, a post-
a factor of γ compared with (10) due to the reduced ZT. Therefore, the amplifier replaces the buffer stage and drives a clock and data recovery
proposed TIA would be suitable for short-distance communications. block of the receiver. Different approach can be taken for a post
amplifier to achieve high gain.
3.3. Dummy TIA and buffer stages The dummy TIA in Fig. 7 enables adoption of a differential signal
scheme [8,19]. The dummy TIA is a duplicate of the main TIA, but
The proposed TIA includes a dummy stage and two buffer stages as without the inductors, and its input is not connected to the photodiode.
shown in Fig. 7. The role of the buffer stage for the proposed design is to The replication ensures symmetry and provide identical DC input
enable performance measurement with network analyzers. The buffer voltage to the buffer [20].
stage is a two-stage differential amplifier with shunt peaking inductors, Due to limited instruments available to the authors, only single-
in which the second stage is the single-ended output for measurements. ended output is taken from the second stage buffer and the other
50 Ω resistors are used at the drain of the last stage to match the output is terminated to a 50 Ω resistor RTERM.
impedance of the instrument, and larger transistors are used to minimize
loss. The first stage of buffer is used to isolate the parasitic capacitance of 4. Simulation and measurement results

The proposed TIA was designed and fabricated in IBM 32 nm CMOS

Fig. 5. Normalized gain of a conventional GBCG amplifier, the proposed main
TIA with an optimum LX (= 235 pH) and excessively large LX.
SOI technology. The SOI technology is suitable for high frequency op­
erations owing to low parasitic drain and source junction capacitance. A
photograph of the chip is shown in Fig. 8. The core area of the die
including the TIA and the buffers is 300 μm × 350 μm, and the main TIA
takes the area of 200 μm × 150 μm. A photodiode capacitance is
emulated on the chip. The transistors are biased with approximately 0.3
mA/μm to result in gm of 26.5 mS. The entire circuit consumes 67.5 mW
under 1.5 V supply, where the input stage and the dummy stage dissi­
pate 16.5 mW each, and the first stage and the second stage buffers
consumes 10.5 mW and 24 mW, respectively.
The performance of the chip was measured on a probe station with a
network analyzer for frequencies 1 GHz–40 GHz. Further, the TIA block
is fed using a signal generator with an input power 10 dBm. Frequency
down-conversions are performed for the measurements of frequency
ranges 50 GHz–75 GHz and 75 GHz–100 GHz. Discontinuity in the gain
measurement is due to measurement error introduced by different in­
struments. The transimpedance gain of the proposed TIA with the buffer
stage shown in Fig. 9 is obtained by converting the measured values of

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J. Chong et al. Microelectronics Journal 114 (2021) 105155

Fig. 8. Proposed circuit: Die photo (left) and layout (right).

Fig. 10. Simulated eye diagram of 100 Gb/s input signal to the measured S-
Fig. 9. Measurement result of the transimpedance gain. parameter model of the TIA.

S11 and S21 to Z parameters and assuming S12 and S22 are negligible [21].
The TIA with the buffer stage achieves the gain of 26 dBΩ and the
bandwidth of 74 GHz. The result matches reasonably well with the
simulation result of the TIA with the buffer stage below 90 GHz, which
enables us to predict the gain and bandwidth of the proposed input stage
alone (without the buffer stage) reliably. The simulation result of the
proposed TIA without the buffer stage is also shown in Fig. 9, and it
indicates that the input would achieve the transimpedance gain of 37
dBΩ and bandwidth of 74 GHz.
Utilizing the measured S-parameter response, eye diagram is simu­
lated with a 100 Gb/s, 20 mA, psuedo-random coded input (Fig. 10). A
square-wave input current with rise time of 1 ps is used to simulate a
source with wide range of frequency components. The eye diagram
shows eye height of 167.5 mV with jitter of 4.4 ps. Clear eye opening
indicates that the circuit is able to operate at the desired data-rate. Note
that this simulation does not take into account noise of the circuit, it only
shows inter-symbol-interference due to gain and phase variation across
bandwidth. In summary, the measurement and simulation result indi­
cate that the TIA would achieve the data rate of 100 Gb/s for short Fig. 11. Input referred noise current density.
distance communications between servers of a data center.
The input-referred noise of the proposed TIA with the buffer stage is
Table 1 compares performance and characteristics of recent, state-of-
shown in Fig. 11. The noise figure is measured only up to 20 GHz due to
the-art TIAs for 40 Gb/s and above with measurement results. It is
inaccessibility of measurement instruments. The current density of the
√̅̅̅̅̅̅ difficult to make a fair comparison of the performance due to differences
input-referred noise is measured as 155 pA/ Hz at 20 GHz. When it is
√̅̅̅̅̅̅ in processing technology, gain, bandwidth, and power dissipation.
extrapolated, the estimated input-referred noise is 181 pA/ Hz at 70 Among the TIAs shown in Table 1, the proposed TIA has the largest
GHz. The integrated extrapolated noise across the bandwidth is bandwidth of 74 GHz, and the TIA of [9] has the next largest bandwidth
approximately 38.4 μA, rms, which translates to the noise floor of − 11.1 of 50 GHz followed the one in Ref. [11] of 45 GHz. Among the three
dBm with a 0.5 A/W photodiode. TIAs, the proposed TIA dissipates 67.5 mW, while the TIA of [9]

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J. Chong et al. Microelectronics Journal 114 (2021) 105155

Table 1
Comparisons of TIAs.
Reference JSSC 2019 [10] TCAS 2010 JSSC 2012 [6] JLT 2019 [11] MWSCAS 2014 A-SSCC 2014 Photonics 2015 This Work
[2] [4] [9] [7]

Technology 28 nm Bulk- 0.13 μm 45 nm SOI 55 nm 65 nm CMOS 65 nm CMOS 65 nm CMOS 32 nm SOI

CMOS CMOS CMOS BiCMOS CMOS
Loop Configuration Closed Closed Closed Closed Closed Closed Closed Open
Input Stage Push-pull CS Push-pull CE CS CS/CG Push-pull GBCG
Total Gain (dBΩ) 74 50 (18a) 55 65 55 52 50 26 (37a)
Bandwidth (GHz) 27 29 30 45 40 50 29.6 74 (74a)
Total Noise (μA, 2.3 8.8 3.54 4.5 2.5 5.01 9.2 38
rms)
Power (mW) 34.6 45.7 9 222 107 49.2 3.8 16.5
FOM 0.8 0.6 3.3 0.2 0.4 1.0 7.8 4.5
a
The gain/bandwidth/die size inside a parenthesis is the value of the TIA excluding the buffer stage.

dissipates 49 mW, and the TIA of [11] 222 mW. The total gain of the
proposed circuit is 26 dBΩ and that for other two TIAs of about 50 dBΩ.
The noise of the proposed TIA is higher than other TIAs due to lower
input impedance and a wider bandwidth. Using a figure of merit (FOM =
Bandwidth/Power), the proposed work shows that higher bandwidth is
achieved per power dissipated compared to all other cited works except
[7]. The closed-loop push-pull architecture in Ref. [7] tends to be lower
power but difficult to achieve higher bandwidth due to inherent large
output resistance of the topology. In summary, the proposed TIA offers
higher bandwidth and comparable power dissipation at the cost of low
gain and high noise figure. Hence, it is suitable for high speed commu­
nications between servers in short distance.
5. Conclusion
A wideband gm-boosted common-gate transimpedance amplifier
(TIA) is presented in this paper. The TIA is able to achieve a data rate of
100 Gb/s for an optical receiver. A diode connected transistor is adopted
at the input of the TIA to decrease input resistance, resulting the high
frequency for the dominant pole. The proposed TIA was fabricated in 32
nm CMOS SOI technology. The TIA achieves a bandwidth of 74 GHz
which is approximately 48% wider than the state-of-the art TIAs. The
TIA dissipates total dc power of 16.5 mW under a 1.5 V supply voltage.
Author statement
Joseph Chong: Conceptualization, Methodology, Software, Valida­
tion, Formal analysis, Investigation, Writing - Original Draft. Fariborz
Lohrabi Pour: Software, Formal analysis, Data Curation, Writing - Re­
view & Editing, Visualization. Dong Sam Ha: Writing - Review & Edit­
ing, Supervision, Funding acquisition.
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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