Design of 1.
55 NEF, 2µA, Chopper Based
Amplifier in 40nm CMOS for Biomedical
Multichannel Integrated System
Paweł Wargacki
Department of Measurement and Electronics
AGH University of Science and Technology
30-059 Kraków, Poland
Email: wargacki@student.agh.edu.pl
Abstract—We present a design of a low-noise chopper based
amplifier for biomedical recordings. It is a part of a multi-
channel integrated system fabricated in 40nm CMOS technology.
It features a DC stabilizing loop for compensating electrode
offset and positive feedback for input impedance boosting. The
first stage uses double current reuse. Design consumes 2µA per
channel under 1V supply voltage and occupies only 0.044mm2 of
silicon area. A novel input stage presented in this work combines
a low noise performance of a stacked input pair with the high
DC gain of the folded cascode amplifier. The simulated input-
referred noise is 0.96µV rms in the 0.5–100Hz frequency band
and 2.8µV rms in the 100Hz–10kHz frequency band, respectively,
leading to a noise-efficiency factor of 5.29 (0.5–100Hz) and 1.55
(0.1–10kHz).
Index Terms—chopper amplifier, current reuse, DC stabilizing
loop, DSL, low noise, low NEF
I. I NTRODUCTION
One of the most crucial blocks in biomedical recording
systems is a front-end amplifier. It must feature a high pass
transfer function to cope with dc input offset from electrodes.
It also contributes a majority of the overall system noise, so it
is crucial to minimize its noise performance for a given power.
The most common and robust architecture of the biomedical
front-end amplifier is the one presented in [1], [2]. Their idea
is to form a very low high pass corner frequency using huge
input capacitors with pseudo-resistors in the feedback loop.
However, using such big input capacitors lowers the input
impedance of the system and the use of huge feedback resistors
rises the input referred noise. To minimize the problem of
noise, a current reuse technique is commonly used. The [3]
shows the best NEF reported in the literature reusing current
six times in the input pair. The other way of achieving very
low noise is to use chopper amplifier with a DC Servo Loop
(DSL). The effect of chopping can remove 1/f noise of input
devices while DSL can lower the noise associated with the
feedback resistors [4].
II. IC OVERVIEW
An amplifier covered in this work is a part of 8 channel
integrated system for biomedical recordings of which simpli-
fied block diagram is depicted in Fig. 1 and is continuation
Piotr Kmon
Department of Measurement and Electronics
AGH University of Science and Technology
30-059 Kraków, Poland
Email: kmon@agh.edu.pl
of our former works [5], [6], [7]. It consists of 8 chopper
amplifiers with shared reference input voltage, sample and
hold blocks (S/H) with multiplexer circuit (MUX), a single
8 bit ADC and a RC oscillator generating different clocks
used for: chopping, sampling and multiplexing and driving the
ADC core and logic. In addition to that, a single channel of
chopper amplifier was also implemented outside of the system
for better testability of the design.
Fig. 1: Integrated circuit block idea.
III. C HOPPER ARCHITECTURE
The amplifier architecture presented in this work (Fig. 2)
combines a chopper amplifier equippped with both the DSL
architecture and dual current reuse of the input pair. A high
input impedance of the amplifier is achieved by the use of
positive feedback, that can be adjusted per channel during
calibration to reduce manufacturing mismatch. Moreover, a
switched-capacitor integrator is being used in the DSL to
achieve low high pass frequency without the use of very large
pseudo-resistors. Use of chopping architecture allowed for the
use of small input capacitors. The saved space was used for a
bigger integration capacitor in the DSL to achieve better noise
performance (Cin = 4x1pF, Cf b = 4x10fF, Cdsl = 4x50fF).
A. Gm1
The proposed architecture of Gm1 stage (Fig. 3) uses 2
stacks of complementary input devices, similarly to the solu-
tion shown in [3] and provides an almost four times increase
 increasing their quiescent power to the point of minimum NEF
with the 120nA of bias current.


2 1 gm19 + gm13
Vni Gm1 ≈ 2γkT + +
Gm1 (Gm1 )2
 (3)
1
+
(gm14 + gm20 ) ∗ (Rin cas )2 ∗ (Gm1 )2

gm17 ro17 ro19

Rin cas =
Fig. 2: Schematic of the chopper amplifier. gm14 (gm20 ro20 ro18 )||(gm15 ro15 ro14 )gm16 ro16
(4)

of transconductance when compared to a single transistor

pair design (1). Normally, such structure requires cascode
devices at the output of M1−4 to sum input currents and
a replica-based bias to guarantee PVT robustness. However,
taking advantage of the chopping architecture and the fact
that the signal of interest is around chopping frequency, we
can use capacitors C1−4 , with the value of reactance Xc , as a
simple current adder, with no additional noise contribution. A
maximum transconductance value is limited by the parameter
α (2), which is the ratio of small signal current that is being fed
into the output cascode to the total value of current produced
by the input pairs. A value of α = 0.8 was chosen in the
presented work. The drawback of the used input stage is a
complicated biasing scheme, requiring bulk biasing to decrease
Vgs of input pairs. The bulk biasing voltage is generated
locally from the diode connected transistors M5 , M8 , M9 ,
M12 . The bulk to source voltage is set to minimum to keep Fig. 3: Dual current reuse Gm1 stage of the chopper amplifier.
bulk current under 1nA and not to generate much additional
noise.

Gm1 = 2α(gm1,3 + gm2,4 ) (1) B. Gm2

ro1,3 ||ro2,4 A majority of output voltage ripple of the chopper amplifier

α= (2) is the result of charge sharing event between the output and
(ro1,3 ||ro2,4 ) + Xc + 2Rin cas
the feedback capacitance. To minimize this effect, a big output
Equation (3) shows the approximated input noise of the capacitance Cout = 10pF+2x4pF was used. It results in a 2nd
gm2
amplifier. It can be seen that apart from the input transistors, pole formation with frequency fnd = 2πC load
. The pole has
transistors M19 and M13 contributes their current noise, and to be placed accordingly to (5) in order to produce a safe
the transistors M14 and M20 contribute their voltage noise, al- phase margin of around 70◦ [8]. From the equation (5), it
though their impact is substantially reduced by high transcon- can be seen that with a fixed Cm = 2x8pF and closed loop
ductance of the input stage. To minimize the current noise, gain of Acl = 100. The only way to ensure stability, while
cascode polarizing current was set to 40nA, which is much increasing Cload , is to increase transconductance Gm2 . That
lower than 1µA flowing through input pairs. Such a high input is why a complementary stage was used as the Gm2 amplifier
pair to cascode current ratio usually results in the relatively (Fig. 4). It allowed to reduce bias current to 220nA while still
high cascode input resistance, which in turn decreases value guaranteeing stability.
of α (2). This increases M19 and M20 noise contribution,
which supposed to be reduced by lowering cascode current
in the first place. To fight this problem, a gain boosting GBW
fnd = 3
technique was applied. Transistors M14 , M15 , M18 , M20 form Acl
(5)
a common source amplifier, which by the means of negative Gm2 Gm1
=3∗
feedback lower input impedance of transistor M16 (4). A noise 2πCload 2πCm Acl
contribution of transistors M14 and M20 was optimized by
 Input referred noise [5uV/div] Input referred noise [5uV/div]
DSL off DSL on
80

Input referred noise [uV/ Hz]

√
60

40 (b) Time [2s/div]

20

10−1 100 101 102 103 104 105 106 107

(a) Frequency [Hz]
(c) Time [20ms/div]

Fig. 6: (a) Simulated spectrum of the input-referred noise

(b) Simulated input-referred peak-to-peak voltage noise in
Fig. 4: Gm2 push-pull amplifier. the frequency band of 0.5–100Hz. 8µVp−p is achieved. (c)
Simulated input-referred peak-to-peak voltage noise in the
frequency band of 100–10kHz. 15µVp−p is achieved.
C. Input impedance boosting
A common drawback of chopper amplifiers with capacitive
feedback is their low input impedance. It is equal to the input 200 PFB on DSL on
capacitor reactance at chopping frequency. A positive feedback PFB on DSL off
loop (PFB) can be used to boost the impedance. Figure (5) PFB off

Input impedance [M Ω]
shows a simplified block diagram of a chopper amplifier with 150
the PFB loop. It can be seen that the current If b flowing
between the output and input of the amplifier is a cause of
low input impedance. Current Ipf b has an opposite direction 100
to current If b and can be used to cancel the input current.
Ideally, current Ipf b being equal to If b would result in an
50
infinite input impedance.
Cpf b

Ipf b
0
Ipf b

Cf b 10−1 100 101 102 103 104 105 106

If b Frequency [Hz]
If b

Fig. 7: Simulated amplifier input impedance.

Cin
in− − out+
+ LPF
Av
−
in+ + out−
Fig. 5: Working principle of PFB loop
Ipf b = (Vout − Vin ) ∗ fchop ∗ Cpf b (6)
= Vout ∗ fchop ∗ Cf b = If b
Cin
=> Cpf b =
Acl − 1
For values of Cf b = 10f F and Acl = 100 optimum value of
Cpf b = 10.101f F (6). Such an exact value is impossible to
achieve in an integrated circuit, therefore a one solution would
be to use value of Cpf b equal to Cf b for better matching and a
theoretical input impedance of Zinp f b = 100 ∗ Zin . However,
as stated in [9], due to parasitic capacitances that are hard to
match in a layout, an impedance boost in the order of only
10x can be achieved. For this reason, a 4 bit capacitor bank
was used in our design. It allows for a 10% manufacturing
mismatch and has a granularity that can achieve 100M Ω of
input impedance. (7)
IV. S IMULATION R ESULTS
To verify adapted methods, a thorough simulations were run.
Figure 8 presents the amplifier bandwidth, which is simulated
to be around 10kHz with a low frequency corner of 0.5Hz.
The Fig. 6 shows the input referred noise spectrum in the
given amplifier. It can be seen that whenever the DSL is
turned on, the low frequency noise is increased, which is a
cause of the low frequency noise of the DSL integrator. The
Fig. 7 depicts how both the PFB and DSL affect the input
impedance of the front-end amplifier. It is evident that the
PFB effectively increases the input impedance in the required
frequency bandwidth. We have also verified the CMRR (Fig.
9) and PSRR (Fig. 10) and it can be seen that in a required
frequency bandwidth these are not worse than 65 dB or 90 dB
respectively.
 40 V. IC IMPLEMENTATION

30 The design has been manufactured in 40nm CMOS process

using EUROPRACTICE mini@sic service. A single channel
20 dimensions are 110x400µm, with the majority of space taken
Gain [dB]

by the integrating capacitors in the DSL as well as the output

10 and miller capacitance (Fig. 11). A photo of manufactured
chip can be seen in Fig. 12.
0

−10 DSL off DSL on

2021_BIO_PW_copy:bio_pot_chopper_1u_test:cmrr : 2021_BIO_PW_copy bio_pot_chopper_1u_test 19:02:48 Fri Mar 11
10−1 100 101 102 103 104 105config
106
Frequency [Hz]

Fig. 8: Simulated amplifier

Fri Mar AC11
transfer function.
18:48:40 2022
…aramset harmonic

-25.0
3.0 0.0

4.0 0.0 -50.0

5.0 0.0
CMRR (dB)

6.0 0.0
-75.0

7.0 0.0
-100.0
8.0 0.0

10.0 0.0
-125.0
11.0 0.0

12.0 0.0 -150.0

15.0 0.0
-1 0 1 2 3 4 5 6
17.0 0.0 10 10 10 10 10 10 10 10
18.0 0.0 Frequency (Hz)
2021_BIO_PW_copy:bio_pot_chopper_1u_test:psrr : 2021_BIO_PW_copy bio_pot_chopper_1u_test 11:18:35 Sat Mar 12 2022
20.0 0.0
config
Fig. 9: Common Mode Rejection Ratio simulated over 100
Monte Carlo runs.
Sat Mar 12 11:12:57 2022
mcparamset …
Fig. 11: Layout of the single channel.

-60.0

-90.0
PSRR (dB)

-120.0

-150.0

-1 0 1 2 3 4 5 6
10 10 10 10 10 10 10 10
Frequency (Hz)

Fig. 10: Power Supply Rejection Ratio simulated over 100

Monte Carlo runs.
Fig. 12: Photo of a manufactured test chip.
 VI. P RELIMINARY M EASUREMENT R ESULTS 120

Three basic parameters of the amplifier were measured so

far, i.e. AC transfer function (Fig. 13), input referred noise 100
(Fig. 14) and Common Mode Rejection Ratio (Fig. 15). All
measurements were taken with the DSL switched off using
Signal Hound USB-SA44B+TG44A spectrum analyzer with 80

tracking generator. The AC characteristic shows a correct

amplifier’s bandwidth with no peeking present and with 40dB 60
per decade drop in the high band. The noise measurements
presents great input referred voltage noise√performance with
spectral noise density of around 23nV / Hz. The visible 40

peeking at 50Hz and it’s 3rd harmonic at 150Hz is the result

of a power grid interference and it will be further investigated. 20
It has a fairly large spectral density, however it is very narrow
and it’s spectral power across whole bandwidth is negligible.
0
100 101 102 103 104 105 106
40
Fig. 14: Measured noise with DSL switched off.
35

30 60

25
55

20
50
15

10 45

5
40

0
102 103 104 105
35

Fig. 13: Measured AC transfer function.

30
102 103 104 105
The measured CMRR of the investigated sample is 20dB
lower than the worst case simulated results. The reason for that
Fig. 15: Measured CMRR.
is higher than expected mismatch between two MOM capacitor
C
ratios: C
Cinm
f bm
and Cfinp
bp
. To mitigate this issue, a T-network
feedback might be used. That would allow to use couple
times bigger feedback capacitance while not increasing input
capacitance, which in turn should result in lower mismatch and
higher CMRR of the desgin. We are now performing missing
measurements for a full characterization of the amplifier.
 TABLE I: Comparison with other works.

[2] [10] [9] [3] [4] [11]

Reference This work
TBioCAS’12 JSSC’16 JSSC’11 JSSC’18 CICC’18
Architecture IA CCLNA Chopper CCIA Chopper Chopper
Technology 130nm 65nm 65nm 180nm 180nm 40nm
Supply/ch 1V 1V 1V 1V 1.8V 1V
Current 12.1µA 3.28µA 1.8µA 0.25µA 1.8µA 2µA
Bandwidth 0.05-10.5kHz 1-8.2kHz 0.5-700Hz 10-10kHz 0.3-5kHz 0.5-10kHz
Gain 40dB 52.1dB 40dB 25.6dB 40dB 40dB
0.65µ 0.96µ
5.5µ (0.3-200Hz) (0.5-100Hz)
Noise[Vrms ] 2.2µ 4.13µ —
(10-10kHz) 2.14µ 2.8µ
(0.2k-5kHz) (100-10kHz)
2.37 5.29
1.07 (0.3-200Hz) (0.5-100Hz)
NEF 2.9 3.19 3.3
(10-10kHz) 1.56 1.55
(0.2k-5kHz) (100-10kHz)
CMRR 80dB >80dB 134dB 84dB >100dB >50dB (1kHz)
>90dB (DC)
PSRR >80dB 78dB 120dB 76dB >70dB
>50dB (1MHz)
Input Impedance 4MΩ — 30MΩ — 440MΩ 50MΩ
Max EDO ∞ — 50mV ∞ 50mV 50mV
-68dB
THD — 1% — — <0.5%
5mVpk−pk
Area/ch 0.072mm2 0.042mm2 0.1mm2 0.097mm2 0.2mm2 0.044mm2

VII. C ONCLUSION
In this paper, a low-noise, low-power, chopper amplifier
was presented that was implemented in 8 channel integrated
system. A novel input stage presented in this work combines
a low noise performance of a stacked input pair with the high
DC gain of√ the folded cascode amplifier. It has a noise density
of 30nV / Hz. In a DC coupled mode with the DSL switched
off it consumes 1.3µA and with the DSL switched on 2µA.
The simulated NEF of 1.55, with the DSL switched on, is
comparable to the state of the art (see Table I).
ACKNOWLEDGMENT
The presented work has been supported by the Na-
tional Science Center, Poland under Contract No. UMO-
2016/23/D/ST7/00488.
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