Journal of Electronic Materials

https://doi.org/10.1007/s11664-021-09337-1

ORIGINAL RESEARCH ARTICLE

Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power

Analog Circuits
Ankit Dixit1 · Pavan Kumar Kori1 · Chithraja Rajan1 · Dip Prakash Samajdar1

Received: 10 March 2021 / Accepted: 8 November 2021

© The Minerals, Metals & Materials Society 2021

Abstract
In this article, analog/radio frequency (RF) performance metrics along with linearity analysis of a silicon-on-insulator lightly
doped drain (LDD)-finFET are investigated through 3D TCAD simulations. The inclusion of LDD regions in the finFET
architecture reduces the electric field by 15.3% in the locality of the drain junction. RF efficiency metrics including intrinsic
gate delay, transconductance generation factor , unity–gain bandwidth, and energy and power dissipation, along with the
subthreshold performance of the proposed device, are compared with the traditional finFET. Device linearity parameters
including second- and third-order voltage intercept point, third-order intercept point, and third-order intermodulation point
are analyzed to test their accuracy and reliability. Look-up table-based Verilog-A simulations are performed to obtain the
circuit-level performance of the finFET structure. Mixed-signal circuits including ring oscillator and operational transcon-
ductance amplifier are designed and investigated for 22-nm LDD-finFET technology and compared with the existing works
available in the literature. We achieved an improvement of 27.59% in oscillation frequency and a maximum common-mode
rejection ratio (CMRR) of 83.45 dB as compared to Si-MOSFET-based circuits.

Keywords  Gate capacitance · intrinsic gate delay · operational transconductance amplifier · LDD-finFET · linearity
analysis · ring oscillator · transient behavior · Verilog-A

Introduction impact-ionization metal–oxide–semiconductor (IMOS),

With the downscaling of semiconductor device channel
length, the transistor operation speed increases at the cost
of severe short-channel effects (SCEs). In order to chase
Moore’s law for next-generation devices, these challenges
need to be addressed. Many new device structures have
been proposed to overcome these SCEs, such as tunnel
field-effect transistor (TFET), junctionless transistor (JLT),
­(WFin), superior gate control is achieved to regulate device
* Dip Prakash Samajdar
dipprakash010@gmail.com
Ankit Dixit
ankit.dixit@iiitdmj.ac.in
Pavan Kumar Kori
1912304@iiitdmj.ac.in
Chithraja Rajan
chithraja.rajan@iiitdmj.ac.in
1
VLSI Design and Nano Scale Computational Lab,
Department of Electronics and Communication Engineering,
PDPM Indian Institute of Information Technology, Design
and Manufacturing, Jabalpur 482005, India
fin field-effect transistor (finFET), and negative capaci-
tance (NC) finFET, operating on the well-known physical
mechanisms.1–5 In addition to these devices, in the sub-
10-nm regime, gate-all-around (GAA) and carbon nano-
tube FET structures are popular because of their excellent
electrical behavior.6–8 However, out of all proposed solu-
tions, fin-shaped channel architecture addresses numer-
ous complications of nanoscale devices.9 As the effective
fin width depends on both fin height (­ HFin) and fin width
subthreshold behavior. In addition, small gate capacitance
and low threshold voltage improve the analog performance
of the finFET as compared to a conventional complemen-
tary metal–oxide–semiconductor (CMOS) device. Downs-
caling of semiconductor devices to the nanoscale regime
also causes high electric field and greater charge velocity
inside the channel region, which has led to the adoption
of advanced device structures such as lightly doped drain
(LDD) during the fabrication process.10, 11 Also, LDD-based
structures counteract SCEs, specifically hot carrier effects
in the device.12

13
Vol.:(0123456789)

For high-speed applications such as communication,
amplification, and biosensing,13,14 device reliability should
be examined for radio frequency (RF) and linearity perfor-
mance.15–17 In our previous work, an LDD-finFET device
capacitance model was developed, and we found that the
LDD-based structure reduced device fringing fields to a
great extent, and hence reduced the total gate (­ Cgg) and gate-
to-drain ­(Cgd) feedback capacitance.12 These capacitances
are critical for defining high-frequency RF performance
metrics such as energy and power dissipation, intrinsic gate
delay, transconductance generation factor (TGF), unity-gain
bandwidth (UGB), and gain–bandwidth product (GBP).18, 19
All these figures of merit (FoMs) are highly dependent on
­Cgg and applied drain supply ­(VDD), and to obtain an ideal
device, these factors need to be scaled down accordingly
for nanoscale devices. Moreover, for a good communication
system design, linear and low-distortion circuit blocks are
essential, for which the linearity of a device is measured by
analyzing harmonic distortion present in the circuit.17,20,21
Hence, to check device reliability in the high-frequency
regime, linearity performance should be analyzed.
In our device-circuit simulation setup, we first extracted
­Id–Vg, ­Id–Vs, and node capacitance–voltage (C–V) charac-
teristics from technology computer-aided design (TCAD)
simulation setup, and later, for circuit simulation, a look-up
table (LUT)-based Verilog-A model was created using the
industry standard Cadence (Spectre) tool. In our previous
work, LDD-finFET-based inverter voltage transfer curve
(VTC) and switching characteristics were investigated.8 In
this work, we focused on the design of the inverter-based
ring oscillator and operational transconductance amplifier
Fig. 1  Cross-sectional view of the LDD-finFET device. (a) Side view and (b) top view.
13
A. Dixit et al.
(OTA). Further, we observed that the Verilog-A-based model
of circuit simulation gives faster and fair results as compared
to the mixed-mode simulation of TCAD environment.
Device Structure and Simulation Setup
Figure 1 shows a 3D cross-sectional view of the silicon-on-
insulator (SOI) LDD-finFET with 26-nm gate length and
a fin with height of 30 nm and width of 10 nm.12 A 15-nm
buried oxide (BOX) layer is deposited over the silicon sub-
strate to reduce the likelihood of leakage between gate and
body contact. The total length of 50 nm of the fin comprises
the channel length, which is varied from 22 nm to 30 nm,
and the source (S) and drain (D) regions. Silicon nitride
­(Si3N4) is used as a spacer material between the S/D and gate
contacts to provide insulation between contacts, and also to
enhance the drain current capability by enhancing the fring-
ing field across the gate contact.22 High-k material H­ fO2 is
selected as a gate oxide material to reduce the SCEs in the
nanoscale regime and compensate the effect of interface trap
charges.3 Polysilicon is replaced with titanium nitride (TiN)
as an electrode material above the contact regions because
of its tunable work function between 4.30 eV and 4.65 eV.23
The proposed device is designed using the Sentaurus Struc-
ture Editor,24 and Poisson’s equations are solved using the
Sentaurus Device TCAD t­ool25 on the SOI-based structure
for reduced off-state current. Standard physical models of
drift and diffusion are used along with high-field saturation
and doping dependence mobility models. Auger and dop-
ing dependence Shockley–Read–Hall (SRH) models are also
Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power Analog Circuits

used to include generation and recombination mechanisms
of minority charge carriers. All simulations are carried out
at 300 K with standard material parameter files. Table I
lists the device dimensions and simulation parameters. For
accurate simulation of the device, a 22-nm fabricated silicon
­finFET26 device was first calibrated using simulation, which
is depicted in Fig. 2.
Results and Discussion
In nanoscale devices, to minimize the electric field in
the interface of the source/drain and channel junction, an
LDD-based structure is preferred in the fabrication process.
Reduced electric field in the interface attenuates electron
velocity in the channel, as depicted in Fig. 3, which signifi-
cantly helps to reduce SCEs such as hot carrier effect, drain-
induced barrier lowering (DIBL), and subthreshold swing
in the device.27 Comparative contour plots of the electron
velocity and electric field between the conventional finFET
and LDD-finFET are illustrated in Fig. 3a, b, c, d. It is evi-
dent from the plots that the electric field at the source/drain
and channel junction has been reduced significantly for the
LDD-based architecture.
Device performance is mostly measured in terms of its
analog FoMs including drain current, threshold voltage,
transconductance, and I­on/Ioff ratio. Therefore, all these
parameters are first investigated through the analysis of the
­Id–Vg and ­Id–Vs characteristics. Figure 4a and b shows drain
current and transconductance curves as a function of gate
Table I  Device dimensions and structural parameters
Parameter Symbol Conven- LDD-finFET
tional
finFET
voltage for a varying channel length from 22 nm to 30 nm in
intervals of 4 nm. The minimum threshold voltage of 0.240
V is extracted by the constant current method for drain cur-
rent at 1­ x10−7 A and maximum transconductance of 0.273
mS is obtained by taking the derivative of the drain current
with respect to gate voltage for ­LG = 22 nm as depicted in
Fig. 4b. The LDD structure increases drain/source resist-
ance, and therefore, a maximum drain current of 0.146 mA
is observed for the conventional finFET.
RF Analysis
To inspect the circuit-level performance in the RF domain,
AC transient analysis of the device is necessary. In this
subsection, the RF behavior of the LDD-finFET including
intrinsic gate delay, intrinsic gain, power and energy dissipa-
tion, cutoff frequency, and TGF are analyzed in detail.15,28,29
All these parameters strongly depend on the C–V charac-
teristics of the device, which are plotted in Fig. 5. From the
device point of view, power and energy dissipation should
be as low as possible and cutoff frequency should be high.
It can be inferred from our previous work that for a similar
channel length, the gate capacitance of the LDD-finFET
comprises the outer and inner fringing capacitances, and
hence, total capacitance increases as compared to the con-
ventional finFET structure. A comparative analysis of RF
FoMs for different channel lengths is tabulated in Table II
and plotted in Fig. 6. It is evident that lower gate length
causes inferior gate capacitance and therefore results in
reduced gate delay and power/energy product. On the other
hand, the output characteristics of the LDD-finFET show
a greater value for the output conductance value, thereby
resulting in higher intrinsic gain.

Drain doping ­(cm−3) ND 1 × ­1020 1 × ­1020

Source doping ­(cm−3) ND 1 × ­1020 1 × ­1020
LDD doping ­(cm−3) ND – 1 × ­1019
Channel doping ­(cm−3) NA 1 × ­1016 1 × ­1016
Drain length (nm) LD 10 10
Source length (nm) LS 10 10
Channel length (nm) LG 26 22–30
LDD length (nm) LLDD – 3
Fin height (nm) HFin 30 30
Fin width (nm) WFin 10 10
Substrate thickness (nm) tSub 10 10
BOX thickness (nm) tbox 15 15
Gate oxide thickness (EOT) tox 1 1
(nm)
Spacer thickness (nm) tsp 2 2
Gate electrode work function φG 4.52 4.52
Fig. 2  A 22-nm SOI finFET calibration with experimental ­data26 at
(eV)
low ­(VDS = 0.05 V) and high (­ VDS =0.8 V) drain voltage.

13
 A. Dixit et al.

Fig. 3  Comparison of electron velocity and electric field for conventional finFET (a, c) and LDD-finFET (b, d).

(a) (b)

Fig. 4  Comparative analysis of (a) drain current and (b) transconductance of the LDD-finFET as a function of gate voltage for channel lengths of
22 nm, 26 nm, and 30 nm.

13
Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power Analog Circuits

Linearity Analysis gives higher transconductance as compared to conventional

Device reliability is another important factor which needs
to be considered to analyze device performance. Distor-
tion occurs in the device due to the presence of interface
trapped charges and shifts the gate bias point. In high-fre-
quency wireless and mobile communication, these effects
can significantly affect the performance of system. At the
device level, where the gain of device determined by the
input transconductance ­(gm) and output conductance ­(go),
different orders of transconductance derivatives ­(gmn) are
used to predict these nonlinearities in any semiconductor
device. To achieve higher linearity and lower intermodula-
tion distortion, higher-order transconductance derivatives,
e.g., ­gm2, ­gm3, etc., should be minimal. The finFET device
0.12
LG = 22 nm
LG = 26 nm
0.10
Gate Capacitance (fF)
CMOS devices at shorter channel lengths. Therefore, the
linearity performance analysis of finFET devices is carried
out to predict its performance for applications in communi-
cation systems. Figure 7 shows the variation in higher-order
transconductance derivatives for different channel lengths.
The linearity performance and intermodulation distortion of
the LDD-finFET are observed by determining FoMs includ-
ing second- and third-order voltage intercept point (VIP2
and VIP3), third-order intercept point (IIP3), and third-order
intermodulation point (IMD3),18,30 which are obtained from
Eqs. 1–4 and plotted in Fig. 8. For an ideal system, VIP2,
VIP3, and IIP3 should be high, whereas lower IMD3 results
in lower distortion. For RF IC applications, R ­ s is generally
taken as 50 Ω.16 The different intercept and intermodulation
points are defined as follows:31
gm1 n
1 𝜕 Ids
VIP2 = 4 ∗ , gmn = (1)
gm2 n
n! 𝜕Vgs

LG = 30 nm
0.08
√
g
VIP3 = 24 × m1 (2)
gm3
0.06
( )
2 gm1
IIP3 = × (3)
0.04 3 gm3 × Rs

0.02
]2
VDS = 0.7 V 9
[
IMD3 = × VIP3 × gm3 × Rs (4)
2
0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V)

Fig. 5  Capacitance–voltage curves for different gate lengths of 22

nm, 26 nm, and 30 nm for the SOI LDD-finFET at V ­ DS =0.7V.

Table II  Comparative analysis Parameter Conventional LDD-finFET LDD-finFET LDD-finFET

of AC transient parameters for finFET
different finFET devices
LG (nm) 26 22 26 30
Cgg (aF) 92.7 84.8 96.4 106.0
Cgd (aF) 6.9 12.9 14.3 15.3
Intrinsic gate delay (µs) 0.201 0.115 0.710 2.03
Dynamic power dissipation (pW ) 44.75 41.55 47.21 51.79
Power–delay product (aJ) 1.75 1.20 3.24 18.45
Energy dissipation (aJ) 44.75 41.55 47.21 51.79
Energy–delay product 1.75 1.20 3.24 18.4
(×10−24 J − s)
Unity–gain bandwidth (GHz) 456.9 526.0 442.6 378.0
Gain–bandwidth product 4.60 3.77 3.40 3.31
(T Hz)
TGF (V –1) 74.45 38.04 43.47 48.04
Intrinsic gain (dB) – 36.7 38.8 41.3

13
 A. Dixit et al.

Fig. 6  (a) Drain current and output conductance as a function of GBP as a function of gate-to-source voltage for LDD-finFET for dif-
­VDS, (b) intrinsic delay and intrinsic gain, (c) energy dissipation and ferent channel lengths. The results show that LDD-finFETs exhibit
energy–delay product, (d) dynamic power dissipation and power– low energy and power dissipation coupled with high intrinsic gain
delay product, (e) TGF and input transconductance, and (f) UGB and and operating frequency.

13
Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power Analog Circuits

Vds = 0.7 V gm1 (A/ V) Vds = 0.7 V gm1 (A/ V) Vds = 0.7 V
0.006 0.006 0.006 gm1 (A/ V)
LG = 22 nm LG = 26 nm
Derivative of transconductance

gm2 (A/ V2) gm2 (A/ V2) LG = 30 nm gm2 (A/ V2)

Derivative of transconductance

Derivative of transconductance
0.004
gm3 (A/ V3) gm3 (A/ V3) 0.004 gm3 (A/ V3)
0.004

0.002 0.002 0.002

0.000 0.000 0.000

-0.002 -0.002 -0.002

(a) (b) (c)

-0.004 -0.004 -0.004
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V) Gate Voltage (V) Gate Voltage (V)

Fig. 7  First-, second-, and third-order transconductance of the LDD-finFET for channel lengths of (a) 22 nm, (b) 26 nm, and (c) 30 nm.

Fig. 8  (a) VIP2, (b) VIP3, (c) IIP3, and (d) IMD3 as a function of gate-to-source voltage for LDD-FinFET for different channel length. The vari-
ation determines the range of linearity and various harmonics distortions in the device.

13
 A. Dixit et al.

10-3
Line: Simulation 10-4 Line: Simulation
10-4
Symbol: Verilog Model Symbol: Verilog Model
10-5 10-5

Drain Current (A)

10-6 (a) (b)
Drain Current (A)
N-type LDD-FinFET
P-type LDD-FinFET 10-6
-7
10
10-8 10-7

10-9 VDS = -0.05V 10-8 VDS =0.05V

-10
10 VDS = -0.35V VDS =0.35V
10-9
10-11 VDS = -0.50V VDS =0.50V
10-12 VDS = -0.70V 10-10 VDS =0.70V
10-13 10-11
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V) Gate Voltage (V)

Fig. 9  Calibration of LUT-based Verilog models (symbols) with TCAD simulations (solid symbols) for transfer characteristics of 22-nm LDD-
finFET device at ­VDS = ±0.7 V: (a) p-type, (b) n-type.

Table III  Oscillation frequency dependency on load capacitance (CL)

Capacitance (fF) 5 1 0.5 0.4

ƒosc (GHz) 2.14 12.9 34.75 52.44

fosc=52.44 MHz
0.8

0.6
Voltage (V)

0.4

Fig. 10  The proposed three-stage voltage-controlled ring oscillator 0.2

(VCRO) circuit based on the 22-nm LDD-SOI-finFET CMOS pair.

0.0
Circuit Design 0.0 2.0x10-11 4.0x10-11 6.0x10-11 8.0x10-11 1.0x10-10
Time (sec)
Three‑Stage Ring Oscillator

Fig. 11  Output from the three-stage ring oscillator designed using a

The ring oscillator is an important circuit component to
check the device capability for high-density IC fabrication,
as it helps to estimate the unit delay in an individual gate,
which is essential for designing circuits such as phase-locked
loop (PLL) and voltage-controlled oscillator (VCO). In the
circuit simulation framework, we calibrated our Verilog-
A model of ­Id–Vg and ­Id–Vd characteristics with TCAD-
simulated data. Good agreement between the modeled and
simulated results was obtained, as shown in Fig. 9.
Figure 10 shows the schematic of a conventional three-
stage ring oscillator designed in the Cadence Virtuoso
22-nm SOI LDD-finFET.
environment. Each terminal of the device is properly biased
and the output node is fed back to the first stage of the cir-
cuit. The load capacitance of each stage is assumed to be
ideal and to have the same value. The oscillation frequency
(ƒosc) of the oscillator is theoretically calculated in Eq. 5,
where N is the number of stages and τp is the propaga-
tion delay of each stage.32 The effect of load capacitance
is studied, and it is found that higher operating frequency

13
Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power Analog Circuits

Table IV  Comparison of oscillation frequency of LDD-finFET with Cadence Virtuoso. A LUT-based Verilog-A approach is fol-
the literature lowed to analyze the circuit operation similar to that of the
Device structures Simulation setup ƒosc ring oscillator. The OTA comprises two stages with a dif-
(GHz) ferential amplifier ­(M1–M4) along with the common-source
Technology Stage VDD (V)
node (nm) amplifier ­(M5–M6) as shown in Fig. 12. The output of the
differential amplifier is an amplified version of the difference
This work 22 3 0.70 52.44 of the input given to the inverting and non-inverting terminal
MOSFET33 90 3 1.5 6.02 (i.e., ­M1 and ­M2). Transistors M ­ 3 and ­M4 work as active
Si-MOSFET34 30 3 1.0 41.10 load transistors whose function is to provide high output
MOSFET35 180 3 1.8 2.45 resistance for good impedance matching with the next stage
DG ­MOSFET36 50 9 1.0 7.00 amplifier. The current-based common-source stage of the
amplifier, which consists of M­ 6 and M­ 7, takes a single-ended
signal with a constant gain feed from the differential stage
and raises the output level to the maximum possible swing.
Phase compensation due to the negative feedback config-
uration is achieved by the Miller compensation capacitor
­Cc connected between the differential and common-source
stage. The circuit comprises transistors M ­ 5 and M­ 8 working
as a current mirror to satisfy all the biasing conditions of
the circuit.
Figure 13 presents the Bode plots for the obtained gain,
phase, and common-mode rejection ratio (CMRR). Note that
these parameters exhibit steady values over a wide range
of frequencies. Table V compares the important parameters
with the available literature. It can be observed that our pro-
posed device has ~35.58% higher CMRR and ~79.16% lower
power dissipation as compared to the 30-nm SOI finFET.37

Fig. 12  The proposed OTA (VCCS) circuit based on the 22-nm SOI

LDD-finFET. Conclusions

In this paper, a 22-nm LDD-finFET is investigated by deriv-

is obtained for smaller values of ­Cn, as given in Table III.
Figure 11 shows the output of the last stage of the ring oscil-
lator for N = 3. The results are also compared with the works
available in the literature and are listed in Table IV. Clearly,
the proposed device exhibits higher ƒosc in comparison to the
conventional MOSFETs.
1
fosc =
2.N.𝜏p
Operational Transconductance Amplifier (OTA)
The OTA is one of the main building blocks of any elec-
tronic circuit, as it produces gain in the output current with
respect to differential input voltage applied to the circuit. It
also serves as a voltage-controlled current source (VCCS)
in many electronic circuit applications. Here a 22-nm fin-
FET with effective width (­ Weff= ­2Hfin+Wfin) of 70 nm and
fin height of 30 nm is used to design an OTA circuit using
ing the gate capacitance of the device. AC transient analysis
for different channel lengths reveals low intrinsic gate delay,
low energy and power dissipation, high intrinsic gain, and
high cutoff frequency, which makes the device a suitable
candidate for RF applications. A minimum power–delay
product of 1.20 aJ and maximum UGB of 526 GHz are
obtained for a channel length of 22 nm, whereas maximum
(5) TGF of 48.04 ­V−1 and intrinsic gain of 41.03 dB are attained
for a channel length of 30 nm. The FoMs of linearity analy-
sis, VIP2, VIP3, IIP3, and IMD3, are analyzed for the pro-
posed device, which clearly demonstrate higher linearity
and low distortion across a wide range of bias voltage to
ensure its capability for power amplifier and RF integrated
circuit design. The latter part of the paper focused on the
circuit-level simulation of a three-stage ring oscillator and
OTA. Our proposed structure exhibits an increase of ~27%
in oscillation frequency as compared to the 30-nm Si-MOS-
FET device. Similarly, the designed OTA delivers maximum
CMRR (~ 83.45 dB) and minimum power dissipation (~
22.50 µW) as compared to the reported works.

13
 A. Dixit et al.

50 200
40 (a) 180
160 (b)
30
41.20 dB 140
20

Phase (Deg)
120 Phase Margin = 58.52
Gain (dB)

10 100
0 80
60
-10
40
-20 VDD = 0.5 V
20 VDD = 0.5 V
-30 CL = 10 pF CL = 10 pF
0
-40 -20
100 101 102 103 104 105 106 107 108 109 1010 100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz) Frequency (Hz)

90

(c)
80
83.45 dB
70
CMRR (dB)

CMRR = Ad-ACM
60

50
VDD = 0.5 V
40 CL = 10 pF

100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)

Fig. 13  Extracted Bode plot for (a) gain, (b) phase margin, and (c) maximum CMRR of 83.45 dB with UGB of 78.41 MHz has been
common-mode rejection ratio (CMRR) of the proposed OTA (VCCS) achieved as compared to similar process technology.37
circuit based on the 22-nm SOI LDD-finFET at ­VDD = 0.7V. The

Table V  Performance Performance This work CMOS 38 SOI finFET 38 SOI finFET CMOS 39 FinFET 40
comparison of the LDD-finFET- parameters 37
based OTA with the available
literature Technology (nm) 22 32 32 30 90 45
Supply voltage (V) 0.70 1.5 1.5 1.0 – 1.0
Load capacitor (pF) 10.0 1 1 0.2 – 1
Dc gain (dB) 41.19 9 13 57 17 83
CMRR (dB) 83.45 35.00 35.53 61.55 – –
Phase margin (degree) 58.52 – – 69.81 61.20 60
Unity–gain bandwidth (MHz) 78.41 1.0 161.3 13.17 – 77.4
Power dissipation (µW) 22.50 – – 108 – 103

13
Design Principles of 22‑nm SOI LDD‑FinFETs for Ultra‑Low‑Power Analog Circuits
Conflict of interest  The authors declare that they have no conflict of
interest.
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