DC and RF Performance Optimization of Strained

Si/Si1-xGex Heterojunction SOI P-TFET

Ashish Kumar Singh*, Manas Ranjan Tripathy, Prince Kumar Singh, Kamalaksha Baral, Sweta Chander, Satyabrata Jit#
Department of Electronics Engineering
Indian Institute of Technology (BHU)
Varanasi, India
Email: *ashishkrsingh.rs.ece17@iitbhu.ac.in, #sjit.ece@iitbhu.ac.in

Abstract This paper proposes DC and RF performance Aluminum ( m= 4.1 eV) is used as a gate metal. The gate
optimization of single gate strain Si/Si1-xGex P- channel gate- stretches a length of 20 nm over the oxides. The Si1-xGex
drain underlap Tunnel Field Effect Transistor (TFET) using layer stretches out from source-channel intersection to drain
2D TCAD simulation tool. Here, in the heterodielectric gate channel intersection, the thickness of a Si1-xGex layer is 20
structure, the ION current is improved by effectively situating
nm. The length of HfO2 oxide is 40nm and a SiO2 oxide is
the gate over the source edge. Gate-drain underlap structure
provides reduced ambipolar conduction in the proposed P- 60 nm.
channel Tunnel Field Effect Transistor (P-TFET) device. The
proposed device demonstrates great execution with an ION/IOFF
of 1014 and average subthreshold swing (SS) of 53mV/dec. In
addition, we have also optimized analog/RF figure of merit
characteristics such as parasitic capacitances,
transconductance, and transit frequency of the proposed
Heterojunction SOI P-TFET (HJ-SOI P-TFET).

Keywords Subthreshold Swing (SS), ON-state Current,

OFF-state Current, ION/IOFF Ratio, Silicon-on-Insulator (SOI),
Band-to-Band-Tunneling (BTBT), Analog/RF figure-of-merit
(FOM).

I. INTRODUCTION
Contrasted with MOSFET, TFETs have a few points: i) Fig. 1. 2-D Schematic structure with dimension and doping profile of HJ-
It is reasonable for the low power application on account of SOI P-TFET.
the lower leakage current (because of the higher obstruction
of the reversed p-i-n junction in TFET). ii) The great TABLE I. DIFFERENT PARAMETERS OF THE PROPOSED
execution can be accomplished with 2nm gate oxide, which HETEROJUNCTION SOI P-TFET
unwinds the need of high-k dielectrics. iii) The tunneling
Parameters Values
impact and the speed overshoot may improve the working
Source Doping (NS) 1021 cm-3
speed of the device [1, 2].
Drain Doping (ND) 5x1018 cm-3
The TFETs responsible for low drive currents because of Channel Doping (PCH) 1016 cm-3
reverse biased of p+-i-n+ diode and for the predominant of Silicon Thickness (tSi) 20nm
the transistor, sharp doping profile is required [3]. There are Gate Oxide Thickness (tox) 2nm
lots of models have been offer to beat this restriction. Some Buried Oxide Thickness (tBox) 10nm
relevant devices among them are TFETs with high-k [4], Gate workfunction ( m) 4.1eV
DGTFETs [4]-[6], band-gap engineered TFETs [7]-[8], Gate Length (LG) 30nm
HMTFETs [9], HJTFETs [10] and Pocket doped TFETs Source Length (LS) 35nm
[11], respectively. The ambipolar current value is high when Drain Length (LD) 35nm
the gate dielectric uses high-k value. Henceforth, gate-drain Channel Length (LCH) 30nm
underlap structure is used which provides reduced
ambipolar current [12]. In this paper, we have used strained
In PTFET operation, all the terminal voltage is measured
Si1-xGex channel instead of Si channel. The value of ON-
with respect to the source and here we ground the source
current and OFF-current can change by changing Ge-mole
terminal. SOI reduces the parasitic capacitance of device so
fraction value. In the second portion of this work, we talked
about proposed device engineering and energy band that it can be used in high-performance RF applications [13]
and it provides high temperature compatibility of the device
diagram and in the third segment we discussed the results of
[14].
the simulation.
Fig. 2 demonstrates the energy-band graphs of the P-
II. DEVICE STRUCTURE AND BAND DIAGRAM channel TFET, in the OFF-state, there is no gate voltage
applied, so there is no band bending occurs in channel
In the structure, we incorporated all the measurement and
region then overlapping is not possible between the channel
doping values. The structure comprises N+ source and P+
valence band and source conduction band, so no tunneling
drain with the stressed Si1-xGex channel. Two gate dielectric
phenomenon occur, only reverse biased in p-i-n structure is
has been along the side set: HfO2 (k=22) and SiO2 (k=3.9).
responsible for small leakage current. In the ON-state, when

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