Doping and doping less III-V Tunnel Field effect

Transistors(TFET): Investigation on reasons for ON

current improvement
N.Anjani devi
Electronics and communication SreenivasaRao Ijjada
engineering Electronics and communication
GITAM deemed to be University engineering
Vizag, AP GITAM deemed to be University
anjali.nagineni@gmail.com Vizag, AP
sijjada@gitam.edu.in

Abstract— The low band gap material Tunnel FETs shows
fundamentally different mechanism than conventional Si TFETs.
InAs/Si TFETs are designed in this work. And ON current ION=1.0
x10-5 A/µm is attained. This drain current doesn’t meet ITRS
requirements. The random dopant fluctuation (RDF) is limiting
the ON current by effecting VTH. Hence doping less InAs/Si TFET
is designed by employing charge plasma to induce the carriers into
source and drain. The RDF effects are hence removed and ON
current of 2.6x10-3 A/µm and subthreshold slope SS of 19.5
mV/dec are obtained.
Keywords— TFET, RDF, charge plasma, hetero TFET
Introduction
To overcome the theoretical constraints and limitations like
short channel Effects ,Tunnel field effect transistor (TFET)
shows enhances performance and replaces conventional
MOSFET. However, still random carrier fluctuations shows
degradation of device performance by increasing IOFF. To
overcome this problem doping less Tunneling FET are also
studied. Gate field plate structure is introduced in Si TFETs
and ON current improvement is noted in compared to Si
TFETs [1]. The effect of using high K dielectric and its
induced fringing fields improves the ON current in Si TFETs
[2]. The operating principle and its designing is described in
[10]. The designs are trying to improve gate controlling
tunneling by that ON current can be improved. But the I-V
characteristics shows very weak temperature dependence [3].
The variation in performance parameters ON current, OFF
current, Subthreshold swing are due to variations in gate
oxide K value, material, oxide thickness. The effect
geometrical variations are discussed in [4-5]. But another
significant effect to be considered with device scaling is “
Random dopant Fluctuations(RDF)”. The RDF impacts the
I-V characteristics which is non negligible. The double gate
TFET is investigated for RDF effects and threshold voltage
variations, transconductance shifts, subthreshold shifts are
reported in [6]. Hence, without doping, charge plasma TFETs
are designed and analysed [7-9]. This paper investigates the
reasons for ON current improvement and also subthreshold
slope shifts by designing and simulating both doping , doping
less III-V Tunnel FTES.
For the simulation InAs/Si hetero junction dual gate Tunnel
FET is designed with hfo2 gate oxide. Chanel thickness is
2nm, gate thickness is 2nm., Silicon thickness tsi is 20nm,
gate length is 40nm. Technology computer aided design
(TCAD) is used to simulate both designs. InAs is considered
as source material to ensure low bandwidth and high
tunneling probability. But channel and drain are Si only
which makes the device hetero junction. The Si on drain side
makes the device more sustain with ambipolar current. The
40nm InAs/Si HTFET is shown in fig 1. The drain current
can be continuously evaluated without any deviations in
geometrical measurements using dynamic non-local BTBT
model [4].
Fig 1: Dual gate hetero InAs/Si TFET
Fermi dirac distributions of source and channel fs, fch has
much effect on tunneling probability and hence on drain
current ID or ION . The total tunneling current is given as (1)
[10]
𝑉𝐵(𝑠)
𝐼𝑇 ∝ ∫𝐶𝐵(𝑐ℎ) 𝑃𝑇 (𝐸)[fs (𝐸) − 𝑓𝑐ℎ (𝐸)]𝑑𝐸 (1)
And the SS depends and exhibits different trends with fermi
dirac distributions[11]. To attain desirable SS value, let us
consider source valance band maximum is very much greater
than E 𝐹𝑝,𝑠 + 3𝑘𝑏 𝑇. In this condition SS shows progressively
increasing from 0mV/dec. and it given as (2).
𝐸𝑓𝑝,𝑠 −𝐶𝐵𝑐ℎ,𝑚𝑖𝑛
𝑆𝑆 ∝ 𝑙𝑛(10). (2)
𝑞

I. DEVICE SPECIFICATIONS AND SIMULATIONS

i. Conventional TFET

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The channel conduction band lies with in 3kBT < C Bch,min <
V Bs,max − 3kBT . Which leads to SS value to 60mV/dec at
300K.
Hence, Fermi-Dirac distribution in doped TFTEs have
considerable impact and large source doping leads to larger
gate voltage sweep. Thus the sub 60mV/dec values for
subthreshold swing can be attained by double gate Tunnel
FETs.
Using non local band to band tunneling algorithm the drain
current is extracted from I-V characteristics. The transfer
characteristics are shown in fig2.
Fig 2: simulated output characteristics in TCAD and captured
saturation
The Transfer characteristics obtained with two different
BTBT models is shown in fig 3. The non -local tunneling path
model and dynamic barrier tunnel model are used to analyse
the characteristics. The barrier height can be effectively
changed using barrier tunnel model and so the characteristics
are improved over non local BTBT model.
Fig 3: VGS vs ID at V =1.0V for two different BTBT models
ii. Doping less Charge plasma InAs/Si TFET:
In the process of attaining large ON currents with TFETs,
many architectures were described [12-15]. The hetero
junction InAs/Si doping less charge plasma dual gate TFET
is shown in fig 4.
 There is no period after the “et” in the Latin
abbreviation “et al.”.
Fig 4: The cross sectional view of charge plasma dual gate
Tunnel FET
The charge plasma TFET without doping is demonstrated in
this work. To avoid random dopant fluctuations effect and so
that to overcome VTH variations charge plasma induced TFET
is considered.
The gap between source and gate electrode is Lgap,S and drain
and gate electrode is Lgap,D. The gate drain gap is always
greater than source gate gap. The reason is to increase the
tunneling probability from source to channel, the gap is less
compared to other side.
The LGAP is the spacer oxide thickness at source an drain
side. LGAP, S is 3nm and LGAP,D is 15nm. Gate workfunction
plays important role in improving characteristics and
workfunction 𝟇=4.5 for both gates. At the channel length of
50nm, the Tox=3nm,TSi= 10nm are considered. All the
simulation parameters are same as the device in fig 1. except
the carrier concentration of n i=1.0x1015cm-3. The Drain
characteristics at VGS=1.0v to 1.3V at the intervals of 0.1V
are shown in fig 5.
Fig 5: The output characteristics of charge plasma InAs/Si
TFET
iii. Effective Work function engineering to improve Ion:
High-K dielectric constant gate oxide such as HfO2 to
replacement of the polysilicon gate by a metal gate.The
effective work function (EWF) of the gate stack combination
are used in the device.
EWF = 𝑠(∅𝑀 − ∅𝑠 ) + ∅𝑠
Where
EWF of metal Fermi energy and the Si conduction band is
𝜒𝑠𝑖 + ∅𝑛 .
 n-type barrier height (∅𝑛 ) = 𝑠(∅𝑀 − ∅𝑠 ) + (∅𝑠 − 𝜒𝑠 ).
The metal work function ∅𝑀 , the semiconductor oxide
reference energy ∅𝑠 , and a Schottky pinning factor S, 𝜒𝑠 is
the oxide’s electron affinity, and s is a reference energy.
The output current characteristics of proposed devices are
compares and are shown in fig 2. It is clearly revealed from
characteristics the ON state current of proposed devices is
high when compared to Si-TFET. And also the OFF state
current is not going to increase in any proposed Hetero
devices. This improvement in ON state current is attributes to
increase in mobility of tunneling carriers. The InAs material
has higher mobility and lower mass as compared to silicon,
SiGe. By using the low band gap material InAs as source
region, the tunneling probability BTBT rate increases. The
transconductance of all the three devices are shown in fig. It
is important parameter and it used to analyse the cut-off
frequency. The transconductance of device-3 is attains the
maximum value as the ID of that device is high compare to
other devices.
II. RESULTS AND DISCUSSION:
In the conventional InAs/Si the source and drain regions are
uniformly doped and source doping profile should be sharp
to improve the tunneling probability. Where as in doping less
TFET the metal electrodes used to induced carriers are only
on top side makes the carrier distribution asymmetric. The
metal electrodes can be further extended to opposite side to
ensure uniform carrier concentration. At VDS=1.0V and
VGS of 0V the ON current of conventional and doping less
TFETs are nearly 1.1x10-5 A/μm. But in doping less TFET
the drain current depends on following factors.
i. LGAP , spacer between gate and drain, gate and
source
ii. 𝟇, Workfunction of source, drain , gate metal
electrodes
iii. The metal electrode length
Hence by varying above factors the drain current in doping
less TFET is improved. At LGAP of 3nm,15nm for source and
drain and work function of 4.5eV the ON current I greatly
improved to.
The comparison of performance parameters for conventional
and doping less charge plasma TFET are shown in table 1.
Table 1: comparison of performance parameters of fig.1 and
fig.4
Design ION(A/µm) IOFF(A/µ SS(mV
m) /dec)
Convention 1.0x10-5 1x10-17 41.54
al
InAs/Si
TFET
Doping less 2.6x10-3 3.64x10- 19.5
InAs/Si 15
Hence this point of view tunnel FET plays the most imminent
role in providing least leakage current but there is necessity
to increase drive current. In hetero tunnel FET the
ambipolarity and unacceptable increment in OFF current
along with ON current are addressed in this paper and by
employing dual electrodes more uniform tunneling also
obtained.
III. CONCLUSION:
The low band gap material InAs greatly improves tunneling
probability and ON current is improved in InAs/Si
conventional TFET compared to Si TFET. Random dopant
fluctuations (RDF) is one of constrain to ON current
improvement. VTH variations can be overcome by supressing
RDF. Hence doping less charge plasma InAs/Si dual gate
TFET is designed to avoid RDF effects. Even though the
drain current characteristics are very much similar in both the
devices, by varying spacer thickness and metal electrode
work function ION of 2.6x 10-3 A/µm is achieved and also SS
of 19.5mV/dec is obtained. By inclusion of some effective
methods, such as dielectric engineering and gate metal
work function engineering, the results can be improved
further and higher ON-state current, steeper
subthreshold slope, and lower threshold voltage can be
achieved.
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