Received: 21 December 2016 Revised: 21 June 2017 Accepted: 20 July 2017

DOI: 10.1002/jnm.2283

RESEARCH ARTICLE

Impact of source pocket doping on RF and linearity

performance of a cylindrical gate tunnel FET

Sidhartha Dash1 | Annada Shankar Lenka2 | Biswajit Jena1 | Guru Prasad Mishra1

1
Device Simulation Lab, Department of
Electronics and Communication Engg,
Siksha ‘O’ Anusandhan University,
Khandagiri, Bhubaneswar, India
2
Department of Electronics and
Instrumentation Engg, Siksha ‘O’
Anusandhan University, Khandagiri,
Bhubaneswar, India
Correspondence
Guru Prasad Mishra, Device Simulation
Lab, Department of Electronics and
Communication Engg., Siksha ‘O’
Anusandhan University, Khandagiri,
Bhubaneswar, India.
Email: gurumishra@soauniversity.ac.in
Abstract
The paper presents a cylindrical gate tunnel (CGT) field effect transistors
(FETs) with a highly doped pocket layer introduced in the source region. The
presence of pocket doped layer in the source provides higher lateral electric
field and band‐to‐band tunneling (BTBT) generation rate in the vicinity of
tunneling junction which in turn increases the drain current and
transconductance significantly. Also, the linearity and radio frequency (RF)
performance of the CGT FET with source pocket doping (CGTS) have been
extensively investigated. The different linearity and RF figure of merits such
as gmn, VIP2, VIP3, IIP3, ZCP, 1‐dB compression point, GBWP, TFP, unity gain
cut‐off frequency, and maximum oscillation frequency of the present device are
extracted and compared with the results of conventional CGT. The results
exhibit superior linearity and RF performance along with improved current
carrying capability of the proposed device. Thus, the device can be one of the
possible contenders to replace bulk MOSFET in high‐frequency microwave
applications. The accuracy of both the devices is validated by TCAD Sentaurus
simulator.

KEYWORDS
drain current, linearity performance, pocket doping engineering, radio frequency parameters

1 | INTRODUCTION

In recent times, cylindrical gate tunnel (CGT) field effect transistors (FETs) have attracted many researchers because of
its steep subthreshold slope, low OFF‐state leakage current, and superior scaling capability.1-5 As a result of reduction in
leakage current, CGT reduces power consumption considerably and thus makes it a suitable candidate to replace
MOSFET for low‐power applications. The current flow in CGT is primarily due to interband tunneling mechanism
where the charge carriers tunnel from valence band of source to the conduction band of channel in the ON‐state. The
input gate bias can control the band bending in the channel and thus responsible for switching of the device.2,3 However,
the device exhibits low drain current characteristics because of band‐to‐band tunneling (BTBT) mechanism which could
not meet the ITRS requirement. Recently, a number of techniques such as use of low band‐gap material in the source,6,7
hetero‐gate dielectric engineering,8 hetero‐junction mechanism,9,10 gate‐to‐source overlap,11 gate‐to‐drain overlap,12 and
pocket doping engineering13-19 have been proposed by researchers to overcome the low drain current issue. Out of the
several methods, the pocket doping engineering (introducing highly doped delta layer in the source) exhibits significant
improvement in drain current and switching ratio with proper selection of position of pocket layer in the source.13 The
presence of heavily doped pocket layer in the source region provides high lateral electric field at the tunneling junction

Int J Numer Model. 2018;31:e2283. wileyonlinelibrary.com/journal/jnm Copyright © 2017 John Wiley & Sons, Ltd. 1 of 14
https://doi.org/10.1002/jnm.2283
2 of 14 DASH ET AL.

and thus increases the probability of tunneling of charge carriers along the channel.13,14 Although the design and
optimization of cylindrical gate TFET with source pocket‐doping are already reported,13 their RF characterization and
linearity analysis is yet to be explored.
Nowadays, the rapid growth of wireless communication technology has created greater demand for low distortion
and high linearity systems. However, FETs are the basic building block for the deign process of these systems.20-22
The existence of higher‐order harmonics in the output signal leads to the nonlinear behavior of the transistors. The
improvement in linearity and distortion performance ensures the minimal impact of higher‐order harmonics and
inter‐modulation terms on the reliability of the device.23,24 So it is highly required to estimate the performance
degradation due to the nonlinearity in the output. Similarly, power dissipation can be further lowered in high‐frequency
applications with significant reduction of parasitic capacitances. Also, in short channel devices, the reduction in coupling
between source and drain leads to considerable decrease in leakage current.25 Thus, the RF performance in terms of
unity gain cut‐off frequency (ft) and maximum oscillation frequency (fmax) needs to be examined for its suitability in
high‐frequency microwave applications.
In this paper, a highly doped pocket layer is developed in the source region of conventional CGT to improve the drain
current and transconductance performance. The drain current of the proposed CGT FET with source pocket doping
(CGTS) is evaluated using BTBT mechanism. Further, the linearity and radio frequency (RF) performance of the present
device have been investigated extensively, and the results are compared with the results of CGT having same dimension
to exhibit its superior efficiency. This paper is organized as follows: Section 2 provides the detailed device structure and
brief analytical modeling. Section 3 reveals the detailed simulation setup and its linearity and RF performance investi-
gation because of the presence of source pocket region. However, the linearity and RF analysis of the present device
are carried out in terms of a number of important figure of merits.

2 | DEVICE STRUCTURE A ND ANALYTICAL MODELING

Figure 1A,B illustrates the schematic cross‐sectional and TCAD simulated structure of an n‐channel CGT FET with a
highly doped pocket layer developed in the source region. Here the pocket‐doped source region is heavily p++ doped

FIGURE 1 (A) 2‐D cross‐sectional (B)

simulated structure of an n‐channel
cylindrical gate tunnel FET with source
pocket doping (CGTS)
DASH ET AL. 3 of 14

(Np = 1021 cm−3) with thickness of L = 1 nm and is placed at a distance of Le = 2 nm from the tunneling junction to
provide optimized performance in terms of threshold voltage, subthreshold swing, and drain current.13 Here, the source
(p+), channel (p), and drain (n+) regions are doped with impurity concentration of Ns = 5 × 1019 cm−3, Nc = 1015 cm−3,
and Nd = 5 × 1019 cm−3, respectively. The silicon body diameter (tsi), gate oxide thickness (tox), and channel length (Lc) are
10, 2, and 50 nm, respectively. The length of the source (Ls) and drain (Ld) are considered as 20 nm each. Here, SiO2 is
used as the gate oxide material having dielectric constant of 3.9. The work function of the metal gate contact is consid-
ered to be 4.2 eV for both CGT and CGTS. In this paper, the impact of 2‐DEG quantum effect on the device performance
is ignored as the entire device is developed using silicon (no band‐gap variation).26
The drain current of the proposed device can be determined using Kane0 s non‐local BTBT model3,4,13,14 as

  
Ak E g − BEkgqz
I D ¼ q∫GdV ¼ q∫E z e dV (1)
qz

Here, G represents the band‐to‐band generation rate of charge carriers in the vicinity of tunneling junction. Similarly,
Eg is the band‐gap energy of the material used as channel (silicon). Ak and Bk are known as fitting parameters having
magnitude of 3.57 × 1027 m−1/2 V−5/2 s−1 and 3.2 × 109 V/m. The lateral surface electric field (Ez) is defined as the electric
field in the intrinsic channel along z‐axis (0 to Lc) which plays an important role in the calculation of drain current and
transconductance of the device.3,4 CGTS enhances the surface electric field at the tunneling junction with the
introduction of highly doped pocket layer and thus improves the current driving capability as compared with CGT.
However, it can be determined by differentiating the surface potential in the channel.13


 
dφs ðzÞ A ðλzÞ B −ðλzÞ
E z ðr; zÞ ¼ − ¼− e − e (2)
dz λ λ

The coefficients A and B in Equation 2 are found to be

 
eð λ Þ K 1 eð− λ Þ −K 2
Lc Lc

A¼ (3)
1−eð λ Þ
2Lc

 
eð λ Þ −K 1 eð λ Þ þ K 2
Lc Lc

B¼ (4)
1−eð λ Þ
2Lc

where

qN c λ2 qN c λ2
K 1 ¼ V bis þ V fb þ −V gs & K 2 ¼ Vds þ V fb þ −V gs − V bid (5)
ϵsi ϵsi

Here, Vgs, Vds, and Vfb are known as the gate to source voltage, drain to source voltage, and flat‐band voltage,
respectively. Similarly, Vbis and Vbid represent the built‐in‐potential developed at the source‐channel and channel‐drain
interface. The characteristic length of the cylindrical body (λ) can be expressed as3,4
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ffi
u
ut si 2 ϵsi ln 1 þ 2tox
t t si
λ¼ (6)
8ϵox

Here, ϵsi and ϵox denote the dielectric permittivity of silicon and SiO2 layer, respectively. Substituting the value of
surface electric field (Ez) in Equation 1, we get
   
Bk q 1 Bk q 1
− E g −λ z − E g þλ z
AAk E g e BAk E g e
Id ¼ − ∫ dV þ ∫ dV (7)
λ z λ z

where V represents the 3‐dimensional tunneling volume inside the cylindrical body (V ¼ πr 2 z for 0 ≤ r ≤ t si
2 & 0 ≤ z ≤ Lc Þ.
4 of 14 DASH ET AL.

0   1 0   1
Bk q 1 Bk q 1
− E g −λ z − E g þλ z
2πAAk E g tsi =2 B z2 e
C 2πBAk E g tsi =2 B z2 e
C
Id ¼ − ∫0 B @∫z1 dzC
Ardr þ ∫0 B @∫z1 dzC
Ardr (8)
λ z λ z

0  1 0  1
Bk q 1 Bk q 1
− E g −λ z − E g þλ z
πt si AAk E g z2 B
2
e C B
Cdz þ πt si BAk E g ∫z2 Be
2 C
Id ¼ − ∫z1 B
@ A z1 @
Cdz
A (9)
4λ z 4λ z

The drain current of the proposed device can be determined by ignoring the effect of polynomial term (1/z) in the
range of [z1 − z2].
! !
πt si 2 AAk E g Rz2 −Rz1 πt si 2 BAk E g Qz2 −Qz1
Id ¼ Bk q
− Bk q
(10)
Eg − λ Eg þ λ
4λ 1 4λ 1

where
 
Bk q 1
− E g −λ z
e
Rz ¼
z

and
 
Bk q 1
− E g þλ z
e
Qz ¼ (11)
z

However, the magnitude of exponential factors Rz2 and Qz2 at a larger value of z = z2 will have negligible impact on
the solution as compared with the values at z = z1. Thus, the drain current expression can be simplified to
! !
πt si 2 AAk E g Rz1 πt si 2 BAk Eg Qz 1
Id ¼ − Bk q þ Bk q (12)
Eg − λ þ λ1
4λ 1 4λ Eg

Here, z1 represents the shortest tunneling distance which primarily is a function of gate bias. It is defined as the
distance from the tunneling junction to the point in the channel where the valence band of source and the conduction
band of channel are in‐line to each other. The shortest tunneling distance is determined using the energy band structure
in the ON‐state and minimum surface potential (φsm). The value of z1 is found to be13
0  r
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 1
Eg Eg 2
B K 1 þ φsm þ q −V bis þ K 1 þ φsm þ q −V bis −4ABC
z1 ¼ λloge B
@
C−Ls
A (13)
2A

However, the minimum surface potential (φsm) is achieved in the pocket doped region (p++) due to the presence of
high electric field. This minimum potential is the result of abrupt decline in the impurity concentration at the same
interface and is found to be13

qNs λ 2
φsm ¼ −A2 cosðzm Þ−B2 sinðzm Þ (14)
ϵsi

where zm represents the instantaneous position along the z‐axis at which minimum surface potential occurs. Similarly,
A2 and B2 are known as the coefficients of surface potential in the pocket doped region and can be expressed as13
DASH ET AL. 5 of 14

sin P3 ðS2 cosðP1 −P2 Þ−S1 Þ þ S3 sin P1

A2 ¼ (15)
sinðP3 −P1 Þ

− cos P3 ðS2 cosðP1 −P2 Þ−S1 Þ−S3 cos P1

B2 ¼ (16)
sinðP3 −P1 Þ

where,
LS −ðL þ Le Þ LS −Le LS
P1 ¼ ; P2 ¼ ; P3 ¼ (17)
λ λ λ

qN p Lλ2 qN s λ2 qN p Lλ2 qN s λ2
S1 ¼ V bis − ; S2 ¼ − ; S3 ¼ V bis − (18)
ϵsi ϵsi ϵsi ϵsi

3 | RESULTS AND DISCUSSION

In this paper, the 2‐D simulation of CGT and CGTS are carried out using TCAD device simulator from Synopsys.27 The
simulation considers different physical models to estimate surface potential, electric field, BTBT generation factor, and
drain current for both the devices. Here, the non‐local BTBT model implements the non‐local generation of electrons
and holes by phonon‐assisted BTBT process. The BTBT generation rate is obtained from the non‐local path integration
of the tunneling distance (from valence band to conduction band). The field‐dependent mobility model, velocity
saturation model, transverse field model, and band‐gap narrowing concentration models are also considered in the
device simulation process. Shockley‐Read‐Hall (SRH) recombination model defines the generation and recombination
of carriers which depends on the doping profile and temperature variation. The Fermi‐Dirac statistics is used to simulate
very highly doped material (pocket‐doped region) in the source end. In this paper, the analog, linearity, and RF
performance of the present device are compared with the results of conventional CGT having same dimension to validate
the improved efficacy in high‐frequency application. Here, we have considered the normalized drain current with regard
to the device width for the results comparison.
Figure 2 shows the comparison of BTBT generation rate for both the devices in the ON‐state with 50‐nm channel
length. It is noteworthy that the present device provides a higher BTBT generation rate in the vicinity of tunneling
junction as compared with CGT. It indicates a significant improvement in tunneling junction area with the introduction
of pocket‐doped region. This is due to the presence of higher electric field along z‐axis at the source‐channel interface.
The enriched tunneling area further leads to increase in tunneling current from source to drain end.
Figure 3 illustrates the variation of normalized drain current (log Id) and transconductance (gm) of the source pocket‐
doped CGT FET with change in gate voltage for Vds = 1 V. The present device exhibits better ON‐current performance as

FIGURE 2 Comparison of BTBT generation rate for CGT and CGTS in the ON‐state
6 of 14 DASH ET AL.

FIGURE 3 The variation of drain current and transconductance as a function of gate bias for both CGT and CGTS

compared with conventional CGT. This is primarily because of the reduction in shortest tunneling distance and
improvement in tunneling volume in the channel. The presence of heavily doped pocket layer in the source region
provides higher electric field at the tunneling junction and leads to decrease in shortest tunneling distance.13,14 This
allows more electrons to tunnel from the valence band of source region to the conduction band of channel region and
thus improves drain current significantly. Transconductance (gm) of a device plays a significant role in the design of
an amplifier because of its impact on intrinsic gain, bandwidth, and noise performance. It also denotes the current
driving capability of the device. As Vgs increases beyond threshold, more number of charge carriers injected from the
source region across the tunneling junction, which leads to improvement in the drain current and thus gm as shown in
Figure 3. It is also evident that CGTS provides better transconductance in comparison with CGT as a result of larger
tunneling volume in the channel which shows improvement in device reliability.

a. Linearity performance of CGTS

In the present era of advanced communication, the linearity analysis plays a crucial role in determining the efficiency
of the device as the non‐linear part of the output may distort the desired signal. The improvement in linearity
performance illustrates negligible impact of higher order harmonics and inter‐modulation parameters. This also reduces
the distortion at the output stages in high‐frequency operations. The device can provide better linearity, if the
transconductance remains constant with regard to the variation in input gate voltage. However, the transconductance
and drain current of CGT FET primarily vary with the change in input voltage reflecting the non‐linear behavior. To
study the non‐linearity behavior of the present CGTS device, the drain current in Equation 12 can be considered as a
time varying non‐linear function.28,29

I d ¼ I 0 þ gm1 V gs þ gm2 V gs 2 þ gm3 V gs 3 þ … þ … (19)

where I0 represents the dc current and Vgs is the applied input gate to source voltage. The Taylor series coefficient gmn is
defined as the nth‐order transconductance of CGTS and can be formulated by differentiating drain current for a constant
drain voltage.

∂I d
gm1 ¼ gm ¼ (20)
∂V gs V ds ¼ constant

∂n I d
gmn ¼ where n ¼ 2; 3; 4; … (21)
∂V gs n V ds ¼ constant

The third‐order transconductance contributes largely to the nonlinearity of a device as it leads to inter‐modulation in
high‐frequency applications.28 It also determines the optimum DC bias point and zero crossover point (ZCP). In the
present paper, the linearity performance of CGTS is investigated by using higher order transconductance parameters
DASH ET AL. 7 of 14

(gm1 , gm2 , gm3). The analysis is further extended to evaluate different device figure of merits such as second‐order
voltage intercept point (VIP2), third‐order voltage intercept point (VIP3), third‐order input intercept point (IIP3), and
1‐dB compression point which can be defined as28-30

4gm1
VIP2 ¼ (22)
gm2

sffiffiffiffiffiffiffiffiffiffiffiffi
24gm1
VIP3 ¼ (23)
gm3

2g m1
IIP3 ¼ (24)
3g m3 Rs

rffiffiffiffiffiffiffi
g
1−dB compression point ¼ 0:22 m1 (25)
gm2

Here, Rs is considered as 50 Ω for most of the RF applications.29,30 These device FOMs are required to be as high as
possible for achieving better linearity performance and minimal distortion in high‐frequency operations.28-31
Figure 4 illustrates the variation of third‐order derivative of transfer characteristics (gm3) with respect to Vgs. gm3 is
one of the key parameters which determine the lower limit on the distortion and position of ZCP. ZCP is defined as
the input gate bias at which gm3 becomes zero and plays a crucial role in the selection of DC bias point to achieve
optimum device operation.28 The introduction of pocket‐doped region in CGT leads to shift the ZCP towards lower gate
bias slightly (from 0.945 to 0.930 V) and the optimum DC bias point is achieved earlier. It is known that for higher gate
voltages, the gain goes on reducing as the amplifier gets saturated and introduces nonlinearity in the output. Thus, the
investigation of linearity performance is utmost important for higher gate bias. The third‐order transconductance should
be as low as possible at higher gate voltages to achieve higher linearity and low distortion.30 It is noteworthy from
Figure 4 that the value of gm3 for CGTS reduces for higher gate bias (beyond ZCP) as compared with CGT, which
indicates a substantial reduction in nonlinearity created by higher order harmonics. However, the present device shows
poor nonlinearity performance for lower gate bias.
Figure 5A,B illustrates the variation of gm3/gm1 (the ratio of the third‐order and first‐order derivatives of the transfer
characteristics) and gm2/gm1 (the ratio of the second‐order and first‐order derivatives of the transfer characteristics) in
logarithmic scale w.r.t. gate to source voltage. It is observed that the ratio decreases with increase in gate voltage for both
the devices. However, CGTS provides lower amplitude of gm3/gm1 and gm2/gm1 ratio as compared with the conventional
CGT device which indicates reduction in nonlinearity due to second‐order and third‐order harmonics. This also reveals
reduction in slope of gm3/gm1 and gm2/gm1 which means the nonlinearity due to gm3 and gm2 reduces faster as compared
with change in transconductance.

FIGURE 4 gm3 as a function of gate bias for both devices at Vds = 1 V

8 of 14 DASH ET AL.

FIGURE 5 The variation of (A) gm3/gm1 and (B) gm2/gm1 ratio in logarithmic scale with change in gate to source voltage

FIGURE 6 The variation in (A) VIP2 and (B) VIP3 for CGT and CGTS w.r.t. gate to source voltage

Figure 6A illustrates the variation of VIP2 with respect to the change in Vgs at a constant drain voltage for CGT and
CGTS devices. The VIP2 can be defined as the extrapolated gate bias at which the fundamental signal and second‐order
harmonic signal voltages are equal. This can be expressed as a critical voltage after which the distortion products will
dominate the fundamental signal. Also, it is a measure of linearity which enumerates the second‐order distortion formed
by nonlinear systems. It is evident that the present device exhibits improved VIP2 performance as compared with CGT
and thus displays better linearity. Here, the peak value of VIP2 in CGTS is enhanced by 29% as compared CGT at Vgs = 1 V.
Similarly, Figure 6B shows VIP3 as a function of gate to source voltage for both the devices. The VIP3 can be expressed as
the input gate voltage at which the first‐order and third‐order harmonic voltages are identical. It relates nonlinearity
caused by the third‐order nonlinear harmonic signal to the linearly amplified signal. The CGTS device provides higher
maximum amplitude of VIP3 (enhanced by 32% for Vgs = 0.9 V) as compared with CGT as shown in Figure 6B. Thus, the
high linearity and low distortion are achieved with the introduction of heavily doped pocket layer in the source region of
a conventional CGT device along with better analog performance.
Figure 7A shows the variation of IIP3 with respect to Vgs at constant drain voltage, and the results of CGTS is
compared with the results of CGT. The IIP3 can be determined as the input power point at which the fundamental term
is equal to the third‐order nonlinearity term in signal power. It is one of the important FOMs which are used to measure
the extent of nonlinearity of a device. To achieve higher linearity and minimal distortion, the amplitude of IIP3 should be
as high as possible. The magnitude of IIP3 increases with increase in gate voltage for both the devices as evident in
Figure 7A. However, the peak value of IIP3 for the present device is higher by 3 dBm (Vgs = 0.95 V) as compared with
conventional CGT as shown in the inset of Figure 7A. The improved IIP3 characteristics of CGTS indicate its suitability
in the high‐frequency applications.
DASH ET AL. 9 of 14

FIGURE 7 (A) IIP3 and (B) 1‐dB compression point as a function of gate to source voltage at Vds = 1 V

Similarly, Figure 7B illustrates the variation of 1‐dB compression point for the present device w.r.t. gate voltage, and
the results are compared with CGT results. The 1‐dB compression point is one of the key figures of merits which deter-
mines the onset of distortion. It is defined as the input power level at which gain reduces by 1‐dB from its reference small
signal value. It is sensitive to higher input power levels as the amplifier gain reduces. But the gain remains constant for
the low input levels. The CGT with source pocket‐doping exhibits higher 1‐dB compression point as compared with
conventional model as shown in Figure 7B. The higher 1‐dB compression point for the present device improves its
sustainability for high input power after which gain of the amplifier reduces. Thus, the device can handle a much wider
range of input voltages without distortion which is useful in most of the microwave applications.

b. RF performance of CGTS

In this section, the impact of source pocket doping on the RF performance of CGT FET has been investigated using
small‐signal NQS model.
Figure 8 illustrates the NQS equivalent circuit of a conventional MOSFET. In recent times, it has been reported that
MOSFET0 s small‐signal model can be used further to evaluate and investigate the RF performance of TFET.32 Thus, the
NQS model is considered for the extraction of small‐signal parameters of CGT and CGTS device using Y‐parameter
analysis. Cgs, Cgd, and Cds are known as the intrinsic gate to source, gate to drain, and drain to source capacitances within
the core circuit, respectively. Whereas Cgse and Cgde represent the extrinsic gate to source and gate to drain capacitances.
Here, Rgd is the effective channel resistance. Similarly, Rg, Rs, and Rd are defined as the gate, source, and drain
resistances, respectively. The effective gate resistance is the addition of effective channel resistance and gate electrode
resistance. The time constant τ, gm, gds, and r0 represent the charge transport delay in the tunneling region,
transconductance, drain to source conductance, and output resistance (drain to source), respectively.

FIGURE 8 Nonquasistatic (NQS)

model of conventional MOSFET to extract
small‐signal parameters of CGTS device
10 of 14 DASH ET AL.

The extraction of intrinsic small‐signal parameters for both CGT and CGTS is achieved by Y‐parameters of
equivalent 2‐port model. However, it is absolutely required to de‐embed the extrinsic components of Figure 8
(Cgse , Cgde , Rg , Rs , Rd) for the accurate extraction of intrinsic analog/RF parameters of the core circuit. The
Y‐parameters for the equivalent 2‐port network of the NQS model can be expressed in terms of simple equations
as follows32:

2

Y 11 ≈ Rgd 2πf Cgd þ j2πf Cgs þ Cgd (26)

2
Y 12 ≈ −Rgd 2πf Cgd − j2πf Cgd (27)

2

Y 21 ≈ gm −Rgd 2πf Cgd − j2πf Cgd þ τgm (28)

2

Y 22 ≈ gds þ Rgd 2πf Cgd þ j2πf C gd þ Cds (29)

The small‐signal intrinsic parameters (gm , gds , Cgd , Cgs , Cds , Rgd , and τ) play a significant role in the RF perfor-
mance investigation of CGTS. These parameters can be directly evaluated using Equations (21–24) and the TCAD
simulated Y‐parameters. The intrinsic analog/RF parameters are found to be

dI d
gm ¼ ¼ ReðY 21 Þjf 2 ¼0 (30)
V gs V ds ¼ constant

dI d 1
gds ¼ ¼ ¼ ReðY 22 Þjf 2 ¼0 (31)
V ds V gs ¼ constant r0

ImðY 11 Þ þ ImðY 12 Þ
Cgs ¼ (32)
2πf

ImðY 12 Þ
Cgd ¼ − (33)
2πf

ImðY 22 Þ
Cds ¼ − Cgd (34)
2πf

ImðY 11 Þ
Cgg ¼ C gs þ C gd ¼ (35)
2πf

ReðY 12 Þ
Rgd ¼ −
2 (36)
2πf Cgd


1 ImðY 21 Þ
τ¼− þ Cgd (37)
gm 2πf

Here, Cgg is the total gate capacitance which is very essential in determining unity gain cut‐off frequency of the pro-
posed device. The external capacitances (Cgse and Cgde) can be determined using Equations (35–36) for zero gate bias
(Vgs = 0V). Here, the effect of overlap capacitance on the RF performance is neglected as the present device is designed
with a non‐overlapping gate over drain interface.32 In this paper, a number of RF figure of merits (FOMs) such as unity
gain cut‐off frequency (ft), maximum oscillation frequency (fmax), transconductance frequency product (TFP), and gain
DASH ET AL. 11 of 14

bandwidth product (GBWP) have been evaluated. These RF FOMs can be estimated with the help of intrinsic small‐
signal parameter as32-35
g g
ft ¼
m ¼ m (38)
2π C gs þ C gd 2πCgg

ft
f max ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

ffi (39)
4Rg gds þ 2πf t C gd

gm
GBWP ¼ (40)
2πCgd


gm
TFP ¼ f t (41)
Id

Figure 9 illustrate the variation in different gate capacitance values of both CGTS and CGT w.r.t. gate voltage.
With increase in gate voltage, the inversion layer is created from the drain side towards the source side significantly.
Thus, the capacitance (Cgd) formed between gate and inversion layer of both devices increases as shown in Figure 9A.
The values of Cgd for the proposed device are smaller than the conventional CGT. On the contrary, it is evident
from the Figure 9B, the gate to source capacitance (Cgs) reduces marginally with increase in gate voltage. This is due to the
reduced coupling between gate and source with the formation of inversion layer. The present device provides
low values Cgs compared with CGT as a result of large extension of inversion layer. This extension is due to the
introduction of a highly doped pocket layer in the source side and thus leads to decrease in coupling between gate
and source. However, the total gate capacitance (Cgg = Cgs + Cgd) follows the dominant gate to drain capacitance
behavior as displayed in Figure 9C. The values of total gate capacitance for CGTS are much less compared with
CGT due to the formation of extensive inversion layer (larger inter‐band tunneling volume). However, Cgs plays a
pivotal role in the cut‐off frequency calculation.
Cut‐off frequency (ft) is one of the important parameters for estimating RF performance of a device used for high
speed digital applications.32-35 It can be defined as the critical frequency at which short‐circuit current gain becomes
unity (0 dB). Figure 10A illustrates the comparison of cut‐off frequency between conventional CGT and proposed
CGTS for Vds = 1V. It is evident that ft of CGTS is several orders of magnitude greater than CGT. This is because
of both the significant improvement in transconductance and reduction in total gate capacitance values. The pres-
ence of highly doped pocket layer in the source region leads to rise in effective tunneling volume and thus gm
increases as shown in Figure 3. Further improvement in ft can be achieved by reducing interface trap charges in
the semiconductor‐insulator interface. Similarly, maximum oscillation frequency (fmax) is a key RF FOM which char-
acterizes the device suitability for tuned RF amplifiers and oscillators. It is the frequency at which the maximum
unilateral power gain drops to 0 dB (unity). The variation of maximum oscillation frequency w.r.t. gate voltage for

FIGURE 9 Extraction of different gate capacitances of CGTS as a function of gate voltage: (A) gate to drain capacitance, (B) gate to source
capacitance, and (C) total gate capacitance. The results are compared with the results of CGT device
12 of 14 DASH ET AL.

FIGURE 10 (A) Cut‐off frequency (ft) and (B) maximum oscillation frequency (fmax) of CGTS as a function of gate voltage

both the devices is shown in Figure 10B. The present device provides higher value of fmax as compared with conventional
model at constant Vds. This is as a result of lower Cgg and higher ft at high gate voltages. Thus, the CGT device with
source pocket doping exhibits higher ft and fmax, which enhances the high‐frequency performance of the device and
makes it suitable for high speed microwave applications.
Gain bandwidth product (GBWP) plays a crucial role in the evaluation of RF performance for a certain dc gain. As
 
GBWP α Cgmgd , it can improve with the increase in transconductance and reduction in the gate to drain capacitance
value. The comparison of GBWP variation of both the devices with regard to gate voltage is shown in Figure 11A.
The GBWP of CGTS is higher by 1 decade as compared with conventional cylindrical‐gate TFET due to improved
transconductance performance (Figure 3) and reduced gate to drain capacitance magnitude (Figure 9A).
Transconductance frequency product (TFP) is an important FOM in high‐frequency operations which signifies a
trade‐off between power and bandwidth. To achieve better RF performance, TFP needs to attain a higher value. The
variation of TFP for both the devices w.r.t. gate voltage is shown in Figure 11B. It is seen that TFP for both the devices
increases linearly with rise in Vgs (up to the inversion region), and after reaching the maximum value, it starts decreas-
ing for the higher gate bias. It is also evident from Figure 11B that the proposed device provides higher TFP as
compared with the conventional CGT. This is as a result of higher current driving capability and higher cut‐off
frequency of CGTS device. At Vgs = 0.975V, TFP of CGTS is higher by ~70 GHz/V as compared with CGT. Thus, it
can be concluded that RF figures of merits improve with the introduction of highly doped pocket layer in the source
region of cylindrical gate TFET.

FIGURE 11 (A) Gain bandwidth product (GBWP) and (B) transconductance frequency product (TFP) of CGTS and CGT device as a
function of gate voltage
DASH ET AL. 13 of 14

4 | CONCLUSIONS

This paper reveals the potential benefits of cylindrical gate TFET with source pocket doping (CGTS) device in terms of
analog, linearity, and RF performance. The linearity and RF analysis of the proposed device are carried out by investi-
gating the performance of a number of parameters like gmn, VIP2, VIP3, IIP3, ZCP, 1‐dB compression point, GBWP,
TFP, ft, and fmax. CGTS exhibits higher reliability with improved immunity against nonlinearity present in the output
as compared with conventional CGT. Similarly, the RF performance improves significantly with the introduction of
highly doped pocket layer in the source of CGT. Thus, CGTS can be one of the emerging devices to be used in wireless
communication systems on account of its improved drain current, RF, and linearity performance.

ORCID
Guru Prasad Mishra http://orcid.org/0000-0003-0326-7619

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How to cite this article: Dash S, Lenka AS, Jena B, Mishra GP. Impact of source pocket doping on RF and
linearity performance of a cylindrical gate tunnel FET. Int J Numer Model. 2018;31:e2283. https://doi.org/10.1002/
jnm.2283