Silicon (2023) 15:1–23

https://doi.org/10.1007/s12633-022-02028-4

REVIEW PAPER

A Review of Tunnel Field‑Effect Transistors for Improved ON‑State

Behaviour
Kadava R. N. Karthik1 · Chandan Kumar Pandey1 

Received: 30 March 2022 / Accepted: 12 July 2022 / Published online: 23 July 2022
© The Author(s), under exclusive licence to Springer Nature B.V. 2022

Abstract
Tunnel Field-effect transistor (TFET) is regarded as the most promising candidate which can possibly replace the traditional
MOSFET from current IC technology. It has gained much attention from the researchers because of its ability to achieve
steep subthreshold slope, a greater immunity towards the short-channel effects and low standby power dissipation. Although
TFET promises a lot of advantages over other contenders of MOSFET, the current transport mechanism i.e., band to band
tunneling (BTBT) leads to its two major roadblocks such as low ON-state current and ambipolarity. This article presents
a detailed survey on the various techniques suggested by the researchers to improve the ON-State current along with sub-
threshold swing in Tunnel FETs.

Keywords  Ambipolarity · Band-to-band Tunneling · Subthreshold swing · Tunnel FET

1 Introduction the current conduction in TFETs mainly relies on inter-band

As current technology has entered into the sub-nanometre
regime, further scaling of MOSFET’s dimensions makes the
device more vulnerable to the various second-order effects,
like channel-length modulation, hot carrier effect, and
drain induced barrier lowering (DIBL), which significantly
degrade the device performances. Moreover, the presence of
Boltzmann tyranny in MOSFET limits the scaling of power
supply which eventually causes its inability to achieve the
subthreshold swing (SS) lower than 60 mV/decade at 300 K.
To achieve a steep subthreshold slope, some researchers
came up with a few novel devices, such as impact ioniza-
tion MOS devices [1], suspended gate MOSFETs [2], Nano-
electromechanical FETs [3], Nanowire MOSFET [4, 5], DG-
MOSFET [6], GAA-Nanowire FET [7], JL-GAA-FET [8]
and Tunnel FETs [9].
Among all the contenders of MOSFET, TFET is found
to be more capable of addressing the aforementioned issues
faced by the current fiercely scaled MOSFET technology. As
* Chandan Kumar Pandey
chandankumarpandey@gmail.com
Kadava R. N. Karthik
karthik.kadava@gmail.com
1
School of Electronics Engineering, VIT-AP University,
Amaravati, Andhra Pradesh, India
tunneling mechanism across the source-channel interface, it
is supposed to have overcome the Boltzmann limit faced by
MOSFETs in which thermionic emission of the charge car-
riers gives rise to the current conduction. However, TFETs
suffer from its two major shortcomings, such as ambipolarity
and less current conduction during on-state. Many research-
ers have come up with various techniques to address the
issue of ambipolar conduction in TFETs, which mainly
includes incorporating a dielectric pocket at drain-channel
interface [10, 11], overlapping the drain with gate [12], and
creating a heavily doped pocket region at channel-drain
interface [13]. To improve ON-state current, researchers
have suggested a number of techniques like Hetero-gate die-
lectric [14], low bandgap source material [15], gate-source
overlap [16], heavily counter-doped pocket at source-channel
interface [17]. Hetero gate Junction-less TFET [18], Stacked
gate Junction-less TFET [19], SOI-TFET with interface trap
charges [20]. The challenges in TFET along with some pos-
sible solutions are shown in the Fig. 1.
In Tunnel FETs, current conduction mainly depends upon
the tunneling probability which acts as a deciding factor for
the rate of charge carriers tunneling at channel-source inter-
face. The tunneling barrier at channel-source interface is
approximated by a triangular shape and based on the WKB
approximation, the tunneling probability is analytically rep-
resented as [21]:

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2 Silicon (2023) 15:1–23

Fig. 1  Challenges in TFET and

Possible Solutions

⎛ � �� 3∕2 ⎞
Sneh Saurabh et al. proposed a structure of TFET with
⎜ 4 𝜆ch + 𝜆 dop 2m∗n Eg ⎟ dual material gate and named it as DGTFET [22]. A cross
TWKB = exp⎜− � � ⎟ (1) section view of DGTFET is shown in Fig. 2. They observed
⎜ 3ℏ Eg + Δ𝜙 ⎟
⎝ ⎠ that tunneling probability of the charge carriers through
channel-source interface attains a maximum value when the
where, m* represents the effective mass of majority charge work function of gate metal closer to source is taken to be
carriers, ­Eg is energy bandgap of source material, e and ℏ are 4.0 eV while a metal with larger work-function is used on the
the electronic charge and reduced Planck’s constant while λ drain side. When the work function difference between Tun-
represents the width of the tunneling region. nel Gate (TG) is reduced, the conduction band of the channel
For the improvement in ON-state current, T(E) needs to region comes closer to valence band of the source region,
be made close to unity and this can be achieved by using a thus boosting the ON-state current. They also observed that
material with a smaller effective mass, steep doping profile OFF-state current increases if the work-function of source-
in the source region, materials with smaller energy bandgap side gate metal is chosen to be more than 4.4 eV (as depicted
­(Eg), and a great electrostatic command of gate on the input in Fig. 3), thereby degrading the device performances. It
tunneling interface. Based on the various techniques used to mainly happens due to a fact that work-function difference
improve the tunneling probability and so the ON-state cur- between TG and AG causes an energy (potential) barrier in
rent, we have grouped the various works done by researchers the channel at their interface, which eventually provides a
into the following categories:

1. Gate Engineering
2. Spacer Engineering
3. Dielectric Engineering
4. Channel Engineering
5. Source Engineering

2 Gate Engineering

In this technique, researchers have used a wide range of met-

als for gate terminal, which was found improving the On-
state behaviour through a better electrostatic control on the
tunneling interfaces by gate terminal. Fig. 2  Schematic 2-D view of DMG-DGTFET [22]

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Silicon (2023) 15:1–23 3

Fig. 4  Electron energy-diagram during ON-State along horizontal

Fig. 3  Drain current for varying work-unction of Auxiliary gate [22] direction [22]

stoppage for the movement of charge carriers during OFF- percent only. Moreover, body thickness may be calibrated
state and this barrier is reduced when work-function of TG is to get the optimum ON-state current.
increased beyond a certain value i.e. 4.4 eV. The respective Nigam et al. studied and analysed the technique of triple
band diagram is shown in the Fig. 4. Furthermore, strain metal gate with DG-TFET for different combinations of gate
introduced in the channel material caused an increment in work function and named it as DMCG-TFET [24]. When
the inter-atomic distance of silicon atoms and so the mobility, a gate metal with high work function of 4.6 eV was sand-
which eventually improves the ON-State Current. Moreover, wiched between the two gate metals having the same low
it was also observed that TFET with dual-material can show work function of 4.0 eV, tunneling width at both tunneling
a greater immunity towards the various short channel effects. interfaces was found to be increased during the OFF-state,
Here, gate leakage current is not taken into the consideration which further causes a notable reduction in sub-threshold
while optimising the gate dielectric material. However, an leakage, as shown in Fig. 7. Moreover, they observed that
accurate calibration is needed to decrease the subthreshold due to source-side gate having low work-function, the pro-
leakage by varying the workfunction of gate metal. Further posed technique offers a prominent improvement in analog
this model does not predict the behaviour of the device for and HF performances as well. In this model Trap assisted
Sub-20 nm technology node. Nonlocal BTBT model was Tunneling and SRH recombination were used, which are
used, and strained silicon model was adopted while simulat- directly proportional to the temperature and due to this, as
ing the structure. the temperature increases OFF-state increases exponentially.
Bagga et al. [23] came up with an idea of triple- material
for the gate terminal in DG-TFET. In their proposed struc-
ture (shown in Fig. 5), a metal with higher work-function
is sandwiched between the two metals with low work func-
tion used on both drain and source terminals. A metal hav-
ing low work-function closer to source terminal improves
the band-bending at input tunneling interface, which even-
tually improves BTBT probability of the charge carriers.
An improved tunneling probability further enhances cur-
rent conduction during on-state, which is clearly evident in
Fig. 6. In addition, a metal having high work-function used
in centre of gate creates barrier in channel which blocks
reverse tunnelling current from drain to channel while device
is operating in subthreshold region, thereby enhancing the
current-switching ratio. Quantum effects are neglected in
this model because the error variation was less than one Fig. 5  Schematic of TMG-TFET [23]

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4 Silicon (2023) 15:1–23
Fig. 6  Transfer characteristics [23]
Since BTBT is not directly dependent on the temperature,
ON-state current is not significantly affected with increasing
temperature. In this work, nonlocal BTBT has been used,
and SRH and Auger recombination were also included to
enable minority charge carrier’s recombination effects. Band
gap narrowing was used because of heavily doped source
and drain.
Ko et al. investigated the device performances of a verti-
cal TFET with triple metal gates and they called it as TMG-
TFET [25], as represented in the Figs. 8 and 9. From the
results obtained through simulation, they observed that by
tuning the work function and length of TMG, a steep SS of
Fig. 7  ID-VG curve in DMCG-TFET for varying workfunction of con-
trol gate [24]
13
Fig. 8  Birds eye and cross-sectional view of device structure [25]
43.5mv/decade and a current-switching ratio of ∼ ­108 can
be achieved in vertical TFETs. The same can be observed
from Fig. 10. The lower work-function metal on the source
side makes the energy band profile steeper at the input tun-
neling interface, which results into more BTBT rate of the
charge carriers during ON-state. They have also shown in
their work that ambipolar conduction can be significantly
mitigated by properly setting the length and work-function
of TMG. An improvement in SS and ­ION/IOFF can be realized
from the band diagram taken during OFF- and ON-state,
which is visible in Fig. 9. In this model, the impact of gate
near the drain was found to be insignificant when compared
with the other two gates. However, because of the three gate
Fig. 9  Energy-band Diagram at VDS = 0.5 V [25]
Silicon (2023) 15:1–23
Fig. 10  Transfer characteristics for optimized TMG-TFET [25]
metals with each of 7 nm length, the channel has a limit of
miniaturisation which does not allow a channel length less
than 20 nm. Nonlocal BTBT model was used in this work
and carrier distributions near the insulator-semiconductor
interface is considered by including Modified carrier con-
finement model.
3 Spacer Engineering
Spacers are usually used to isolate gate terminal from drain
and source regions which are made up of nitrides and oxides.
However, spacers have a significant impact on the various
device parameters as well. In this section, we have analysed
some of the works done by researchers related to the spacer
engineering.
Abhijit et al. studied and analysed the Tunnel FET struc-
ture by separating the gate from drain and source using a
High-κ ­HfO2 spacer which is shown in Fig. 11. In their work
[26], they observed that channel resistance decreases due
to high-κ value of spacers, which further improves the ON-
state Current. They also observed that spacer on drain side
along with gate-drain overlap (shown in Fig. 12(a)) has no
impact on the transfer characteristics for ­VGS > 0. Further-
more, they also observed that the small V ­ GS can control the
Field-induced barrier lowering (FIBL) at edge of the gate
on drain side where lateral tunneling continues to domi-
nate over vertical tunneling, thus resulting to an improved
OFF- and ON-state behaviours. In this model, FIBL plays a
major role in generating the tunneling current, which mainly
depends on the degree of spacer overlap. The space over-
lap induces a vertical electric field which depletes the drain
region, thereby increasing the tunneling barrier width at
5
Fig. 11  Structure of n-channel silicon TFET [26]
channel-drain interface. As a consequence of this, OFF-state
current was reduced in their proposed device, as depicted
in the Fig. 12(b). A large overlap between drain and spacer
increases the parasitic capacitance between the gate and
drain terminals, and so is the delay time, which eventually
degrades the switching speed.
In this paper [27], researchers demonstrated a Tunnel
FET structure using dual-κ (kappa factor) spacers. They
used a High-κ spacer near the gate-source/drain edge, while
a low-κ spacer was used on the outer edge of the both sides.
They observed a dense fringing field (depicted in Fig. 13))
which increases the ON-state current when a high-κ spacer
moves toward the junction in an underlap structure. They
also mentioned that a further increment in the gate voltage
improves the tunneling probability of charge carriers which
results in the improved current conduction during the on-
state, as shown in Fig. 14. The proposed structure improves
the gate coupling resulting in a good control of gate over
the source-channel interface. Although, ON-state current is
found to be improved but it potentially degrades the liFE-
Time of the circuit due to High-κ value materials used for the
device. Increment in the ON-state current mainly happens
due to the reduction in tunneling barrier length at source-
channel junction which can be observed from band diagram
shown in Fig. 15. Since position of the spacer decides the
tunneling current, so an optimum position of the same needs
to be found out. Moreover, convergence of the fringing fields
while reducing the channel length causes an increment in
leakage current.
Anghel et al. proposed an engineering technique using a
low-κ and a high-κ dielectric materials for spacer and gate
oxide [28], respectively which is shown in the Fig. 16(a).
Due to the presence of the double gate, volume inversion
occurs within the channel, which contributes to the ON-state
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6 Silicon (2023) 15:1–23

Fig. 12  (a) Impact of vary-

ing overlap between spacer
and drain in the n-TFET
EOT = 0.4 nm [26]. (b) Band
diagram showing less Tunneling
distance for (0 nm) overlap [26]

current. They compared their proposed structure with the
other two existing structures among which one structure
is without a spacer but having a thin oxide over the entire
device, and another structure with a spacer of high-κ. In
these two existing structures tunneling takes place in the
depth of the body, where Tunneling probability is very low
due to more tunneling width, and this is the reason why
ON-state current is not significantly improved, as depicted
in Fig. 17. A low-κ spacer used in the proposed architec-
ture diminishes the fringing electric fields and as a result
of this, depletion is not created at source-channel tunneling
interface.
The deprivation of depletion region near the channel-
source interface causes tunneling of mobile carriers to occur

Fig. 13  Device schematic using

single-κ spacer, placing Dual-κ
spacer in DG-TFET, and Dual-κ
spacer interface with source
doping [27]

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Silicon (2023) 15:1–23
Fig. 14  Comparison of transfer characteristics [27]
at the surface of TFET where transverse electric field is
maximum (tunneling width is very low), which further con-
tributes to the ON-state current. The same can be realised
from the energy band diagram plotted in Fig. 18. They also
noticed that scaling the thickness of the low-κ spacer does
not have much influence on ON-state behaviour, whereas
scaling the High-κ dielectric thickness has a significant influ-
ence on the same. The nonlocal band to band model com-
bined with bandgap narrowing and quantum density gradient
models were used.
Kim et al. proposed a structure of TFET by using two
asymmetric spacers [29], as shown in the Fig. 19. A high-κ
spacer is used near the source side which produces the
Fig. 15  Comparability of energy-band diagram for all three structures
[27]
7
Fig. 16  2-D structure of TFET with (a) High-κ gate dielectric and
Low-κ spacer (b) High-κ gate dielectric, and (c) ­HfO2 as high-κ value
material and S
­ iO2 as Low-κ value Material [28]
fringing field deep in the body, thus improving the ON state
current. A spacer with Low-κ is used on drain-side to reduce
the subthreshold leakage. Initially, both ON-state current
and ambipolarity were found increasing due to the use of
a High-κ spacer towards the source and drain side. High-κ
spacer was found producing the large magnitude of elec-
tric field at a relatively smaller ­VGS (i.e. 0.35 V) whereas
Low-k spacer makes the tunneling happen at V ­ GS = 0.9 V,
thus reducing the OFF-state leakage current. To solve the
Fig. 17  Comparison of transfer characteristics [28]
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8 Silicon (2023) 15:1–23
Fig. 18  Variation in tunneling width when VGS is changed from (0 to
1.6 V) [28]
problem of ambipolarity, a low-κ value spacer was used on
the drain side, which additionally mitigated the fringing field
between gate and drain and so, drain-gate parasitic capaci-
tance. Transfer characteristics in their device for varying
κ-values and spacer thickness are revealed in Figs. 20 and
21, respectively. The output characteristics is also shown in
Fig. 22. In this structure thickness of the High-κ value spacer
needs to be optimised to reduce the fabrication efforts. The
impact of substantial doping on bandgap narrowing in the
source area is studied by including the Slotboom model.
Drift–diffusion model, SRH recombination models, dynamic
Fig. 19  The schematic of the optimized TFET [29]
13
Fig. 20  Transfer characteristics at V
­ DS = 1.0 V [29]
nonlocal BTBT were used and Trap Assisted tunneling
(TAT) model was neglected while simulating the structure.
4 Dielectric Engineering
Boucart et al. [30] investigated and proposed a new Tun-
nel FET structure with double gate which is depicted in
Fig. 23. The proposed structure used a high-κ dielectric
material as gate-oxide and optimized the thickness of sili-
con body. They observed that gate-oxide of high-κ die-
lectric improves coupling capacitance between channel
and gate, thus enhancing the ON-state current which is
Fig. 21  ID-VG behaviour for varying spacer thickness at κ = 25 [29]
Silicon (2023) 15:1–23
Fig. 22  Output characteristics for varying k-value of spacer at
­VGS = 1.0 V [29]
revealed from Fig. 24. Furthermore, the double-gate struc-
ture causes volume inversion in the channel, which further
enhances ON-state current. They also noticed that sub-
threshold swing is significantly improved in their proposed
device as compared with a MOSFET of the same dimen-
sions. However, leakage currents have been neglected
while doing the simulation, which may become dominant
when length of the channel is downscaled.
Fig. 23  Proposed Structure of DG-TFET with High-κ dielectric mate-
rial [30]
9
Fig. 24  Transfer characteristics of DG-TFET [30]
Hesameddin et al. investigated and developed a high-per-
formance steep tunnel FET structure to improve the ON state
current and named their structure as Dielectric Engineered
Tunnel FET (DE-TFET) [31]. A low-κ dielectric material is
stuffed between the two high-κ gate dielectric materials, as
shown in Fig. 25(a). Due to this horizontal dielectric stack
technique, a high electric field is developed at the top of
the tunneling interface which leads to an improvement in
the ON-state current and the same can be realized from
Fig. 25(b). The impact of high electric field on the ON-state
Fig. 25  (a) Schematic of DE-TFET (Dielectric Engineered Tunnel
FET). (b) Interpretation of electric field intensification using a low-κ
dielectric next to high-κ dielectrics [31]
13
10
current can be realized from Fig. 26(a) in which the transfer
characteristics of the proposed device is shown, and respec-
tive band diagram is depicted in Fig. 26(b). The existence of
a Low-k dielectric sandwiched between the two high-k gate
dielectrics causes for a considerable increment in the electric
field (€2 < €1), thus improving the BTBT during ON-state.
Here in this structure, input tunneling width only depends
on the width of low-κ dielectric material. Additionally, they
observed that this technique can solve the problem asso-
ciated with chemical doping. Despite a fact that the oxide
thickness has less impact on the performance of DE-TFETs
than ED-TFETs, a thinner oxide is still advantageous for
improved device performances.
Fig. 26  (a) ­ION/IOFF ratio of DE-TFET [31]. (b) Band diagram at
Electric field of 0.9 V/nm
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Silicon (2023) 15:1–23
Zhijiong Luo et al. investigated a P-type Tunnel dielectric
TFET structure which they named as TD-TFET [32]. The
cross-section view of Conventional and proposed structure
can be seen in Fig. 27. In conventional TFET (shown in
Fig. 27(a)), drain and Source regions are usually doped with
opposite polarities, and tunneling of mobile carriers happens
through semiconductor at channel-source interface, which
further causes the ON-state drive current. TD-TFET, on the
other hand, employs a thin dielectric at input tunneling inter-
face through which tunneling of mobile carriers happens,
which causes a drive current in the device. In fact, a thin
dielectric layer near the source-channel interface (as shown
in Fig. 27(b)) makes the tunneling barrier width narrower,
thus enhancing the ON-state current. This phenomenon is
found to be analogous to inserting a thin dielectric mate-
rial between metal and semiconductor, which modulates the
Schottky barrier. This further results into the reduction of
resistance between semiconductor and metal, thus improving
the ON-sate current, as shown in Fig. 28. They also observed
that ambipolarity is significantly suppressed along with an
improved subthreshold swing.
Narang et al. investigated and demonstrated a TFET
structure having multiple layers of dielectric and named
as gate stack architecture GS-DG-TFET [33]. The multi-
layer dielectric stack is built with a low-κ ­( SiO2) and a
high-κ ­( HfO 2) dielectric to improve the On-state cur-
rent, as depicted in Fig. 29. An increment in the electric
field at the input tunneling interface enhances the rate of
charge carriers tunneling at source-channel interface, thus
improving the ON-state current. Even band-bending at
Fig. 27  (a) Schematic of conventional TFET and (b) Modified struc-
ture of Tunnel Dielectric-based Tunnel FET [32]
Silicon (2023) 15:1–23
Fig. 28  Transfer characteristics of conventional and TDTFET [32]
channel-source tunneling junction is also found to be more
notable in stacked gate architecture due to an improved
gate-channel coupling capacitance. In addition to this, they
also noticed that GSDG-TFET could obtain a minimum
tunneling width for even for a low gate voltage, the tun-
neling probability is shown in Fig. 30 from which it is
evident that tunneling probability can be improved with
the help of gate-stack. The same can be observed from
Fig. 31 which shows a notable improvement in I­ D-VG char-
acteristics of the proposed device. It was found that ON-
state current increases approximately by ten times when
a low-κ dielectric material is used under a high-κ material
Fig. 29  Schematic of proposed DG-TFET [33]
11
Fig. 30  Tunneling Probability as a function of ­(VGS) for low-κ and
stacked-gate DG-TFET [33]
by keeping the EOT (Effective-Oxide Thickness) of the
proposed device same as that of the Conventional one.
In this paper [34], Wei et al. investigated a U-shaped
TFET structure, which was already available in the litera-
ture. They demonstrated the same structure by incorporating
heterogeneous gate-dielectric material to reduce the Miller
capacitance, as shown in Fig. 32. However, the ON-state cur-
rent in both the structures was found to be the same. When a
thin ­N+ pocket was placed near the source-channel interface
of the proposed structure. Tunneling of the charge carriers
Fig. 31  Transfer characteristics of GS-DG-TFET [33]
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12
Fig. 32  Schematic structure of HG-UTFET [34]
happened in both parallel and perpendicular directions to the
channel. Due to this two-way tunneling processes, the ON-
state current is significantly improved. Moreover, a High-κ
­HfO2 further improved the control of gate over the source,
thus enhancing the contribution of vertical tunneling. Next,
the low K-value dielectric material i.e., ­SiO2 used near the
drain region caused a reduction in the gate-to-drain parasitic
capacitance ­(Cgd), thereby improving the switching charac-
teristics of the device. A comparison of transfer characteris-
tics between UTFET and HGUTFET is shown in Fig. 33(a),
and the output characteristics in Fig. 34. They also verified
the device performances by simulating an inverter circuit,
and they observed that inverter based on HG-UTFET has
45.6 percent less miller capacitance and so, 30.7 percent
less fall time than those of the UTFET based inverter. The
capacitance comparison was represented as in Fig. 35.
5 Channel Engineering
In this paper [35], the authors proposed and investigated
a TFET having covered source-channel with the help of
a trench gate and named this structure as CSC-TFET (as
shown in Fig. 36). This covered source–channel region was
found boosting the ON-state current when a positive gate
bias is given. They observed that BTBT of the charge car-
riers happens In both parallel and perpendicular directions
along the covered source region. Therefore, dimensions of
the trench gate play an important role in deciding the width
of tunneling window, and so drive current in the investigated
device. ­ID-VG behaviour of planar TFET and CSC-TFET
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Silicon (2023) 15:1–23
Fig. 33  (a) ­ID-VG Curves for N type U-TFET and HG-UTFET [34].
(b): Electron density (4.9E + 18) of HG-UTFET and N-type U-TFET
in inset [34]
can be seen from Fig. 37. They also observed that the rate
of electrons tunneling through source-channel interface is
directly proportional to the summation of the length of the
source and depth of the trench gate. I­ D-VG plots for varying
length of covered source and Si thickness can be seen in
Figs. 38 and 39(a), respectively. The BTBT electron genera-
tion rate was clearly seen in Fig. 39(b).
In this paper [36], Kim et al. proposed a TFET structure
with many variable parameters to enhance the ON-state
current. Primarily they designed an L-shaped channel and
extended the gate beyond source deep in the body which is
revealed in the Fig. 40(a). As a result of the gate extension,
electric field crowding was found at the edge of source
corner resulting in the tunneling of charge carriers at this
corner as well, which further degrades the device perfor-
mances. To avoid this stumbling problem, they placed a
heavily doped pocket between the corner of source and
Silicon (2023) 15:1–23
Fig. 34  (ID vs ­VDS) of N type U-TFET and HG-UTFET [34]
gate to mitigate this corner tunneling, which is shown
in Fig. 40(b). In this Tunnel FET structure, the height of
source ­(HS) can be further increased to improve current
conduction during on-state without affecting the thresh-
old voltage. Moreover, they also noticed that reducing
the channel length could further ameliorate the ON-state
current, as depicted in Fig. 37. In addition, they found
that this TFET structure is more immune to second order
effects. They observed that SS is minimized to 26 mV/dec
at 300 K, and the ON-state current is approximately twice
of that in the conventional L-Shaped channel TFET. ­ID-VG
plots of the proposed device for varying channel length is
depicted in Fig. 41.
Fig. 35  Gate capacitance of N type U-TFET and HG-UTFET [34].
13
Fig. 36  Schematic of CSC-TFET [35]
Yun et al. examined the L-shaped channel TFET [37]
and proposed an F-shaped channel Tunnel FET structure
which is shown in Fig. 42. Here in this structure, ON-state
current prominently depends upon the length of the tun-
neling region. In particular, as tunneling length is short-
ened, fully-depleted tunnel region of Si shows a reduced
capacitance, thus lowering the surface potential at fixed VGS,
Fig. 37  ID-VG plot of a CSC and planner TFET [35]
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14 Silicon (2023) 15:1–23

Fig. 38  ID-VG Curves for varying length of covered source by fixing

­TSi = 2 nm [35]

and the average SS. An optimum length of the tunneling

region was found to be 4 nm at which the ON-state cur-
rent was observed to be better, as shown in the Fig. 43. In
addition, they discovered that thickness of the source also
plays a significant role in determining the ON-state current.
As thickness of the source was decreased, fringing fields
at the corners of the source region start merging, thereby
lowering the turn-on voltage (­ VON), which eventually con-
ferred a significant enhancement to the ON-state current,
as evident in Fig. 44. Furthermore, they demonstrated that
adding multiple number of the sources with limited space
between them (as shown in Fig. 42(b) also improves the Fig. 39  (a) ­ID-VG plots at fixed LS (length) of 20 nm and varying ­Tsi
ON-state current with better ­VON. Increment in ­TE and ­TI [35]. (b): Band to Band electron generation date
improves the ON-state current which is clearly visible in
Figs. 45 and 46. In their work, they have made a fair compar-
ison between the proposed F-shaped and existing L-shaped
channel TFETs and found that V ­ ON and on-state current of
the F-shaped TFET [31] are 0.4 V less and 4.8 times more,
respectively than those of the L-shaped TFET [36], as shown
in Fig. 47. In this model, trap-assisted tunneling contributes
to the degradation in SS with increasing temperature in the
subthreshold region. Nonlocal BTBT, Band-gap narrowing
model, SRH recombination model, doping dependent Mobil-
ity models were used for clear examination.
Ashita et  al. came up with an idea of improving the
ON-state current using source-channel overlap along
with a counter-doped pocket. As shape of the tunneling
interface between source and intrinsic channel looks like
Inverted-C, they called it as Inverted-C TFET (ICTFET)
[38], as shown in Fig. 48. In their proposed structure, they
extended the intrinsic channel into source between the Fig. 40  (a) L-shaped TFET (b) L-shaped TFET with pocket doping
counter-doped pocket regions. As a result, tunneling width [36]

13
Silicon (2023) 15:1–23
Fig. 41  ID-VG curve of L-shaped TFET for varying channel length
[36]
at source-channel interface was narrowed, which further
enhanced the ON-state current. The proposed structure has
both lateral and vertical tunneling paths while the conven-
tional GoSo TFET [39] had only vertical tunneling, which
requires a higher voltage supply to start the tunneling pro-
cess. They observed that the ON state current in the pro-
posed ICTFET is four times of that in the GoSo TFET [39],
as shown in Fig. 49. Additionally, they observed that various
analog and RF parameters like miller capacitance, transcon-
ductance and cut-off frequency are also improved for the
proposed device as compared with those of the conventional
GoSo TFET. To capture quantum effects, a modified local
density model was employed, and a nonlocal BTBT model
was used to capture both lateral and vertical tunnelling
currents.
Fig. 42  Schematic of F shaped channel TFET [37]
15
Fig. 43  (ID-VG) curve by varying length of tunnel region (LT) [37]
In the paper [40], the researchers came up with an idea
of graded Si/Ge heterojunction [41] (as shown in Fig. 50)
in which mole fraction of the Ge contents was reduced
while traversing from source to drain through the channel.
When length of the channel was taken sufficiently long, they
observed better performances of the device even without
using the graded junction. However, they noticed that vari-
ous short channel effects started dominating for a sub-20 nm
channel length. In their work, they have demonstrated that
the graded heterojunction caused a narrow tunneling barrier
at the source-channel interface which further enhanced the
tunneling rate of charge carriers and so is ON-state current.
Fig. 44  Transfer characteristics by varying thickness of source (TS)
[37]
13
16
Fig. 45  Transfer characteristics by varying space above and below the
source (TE) [37]
Furthermore, tunneling width at the channel-drain interface
was found wider due to relatively large band gap channel
region, thereby reducing the OFF-state current in the pro-
posed device. They also observed that barrier height and
width of the tunnelling interfaces depend on magnitude of
the gate voltage. Therefore, the bandgap is observed as a
step function of the gate voltage. In addition, they found
that tunneling of charge carriers in the long channel device
starts in the body and reaches the surface, whereas, in the
device of sub-20 nm channel, this tunneling originates at
the surface and moves into the body. This diverse tunneling
pattern of the charge carriers is the main reason for such a
Fig. 46  Transfer characteristics by varying distance between two
sources (TI) [37]
13
Silicon (2023) 15:1–23
Fig. 47  Transfer characteristics of F shaped TFET in comparison
with L shaped TFET [37]
steep slope and improved ON-State current in the proposed
device. Transfer characteristics of uniform Ge, abrupt Si/
SiGe and graded Si/Ge heterojunction TFET are shown in
Figs. 51, 52, and 53, respectively.
In this paper [42], the authors demonstrated a graded-
channel Tunnel FET structure (GCH-TFET) in which
they introduced a small broken-gap heterojunction
near the channel-source tunneling junction, as shown
in Fig.  54. This broken-gap heterojunction provides
a steep band-bending at the input tunneling interface
which eventually improves the tunneling probability
and so is the ON-state current. They also observed that
the same minimum tunneling width, which was found
Fig. 48  Schematic of (a) GOSO TFET and (b) Inverted-channel
TFET [38]
Silicon (2023) 15:1–23
Fig. 49  Transfer characteristics [38]
in the conventional NBGH-TFET to start the BTBT,
is achieved at a relatively higher gate potential in the
proposed GCHTFET. Consequently, when the device
turns on, lateral electric field in the tunneling region
was found higher than that in NBGH-TFET and even-
tually, a steeper SS was observed in their device. The
probable fabrication steps can be found in [43, 44],
Furthermore, they also found that graded channel com-
ponent diminishes the electron affinity of channel and
band gap of the channel increases while moving from
source to drain. An increased bandgap channel region
near the drain side causes a higher barrier height at
Fig. 50  Graded SiGe-TFET structure, and comparison of Band dia-
gram of all three models [40]
17
Fig. 51  Gate voltage, drain current curves of uniform Ge TFET [40]
the channel-drain interface, which ultimately blocks
the leakage current in GCH-TFET during OFF-state.
Such a graded channel helps for sudden excitation of
BTBT of charge carriers. Additionally, they used a rela-
tively wide band-gap material for the drain region to
reduce the ambipolarity and SRH recombination in their
device. Improved ON-state and OFF-state current are
shown in Figs. 55 and 56. Parameters for the material
have been taken from the experimental work reported in
[45]. It was also found that turn-on voltage is large for
the graded channel which eventually degrades the SS.
Fig. 52  Gate voltage, drain current curves of abrupt Si/SiGe [40]
13
18
Fig. 53  Transfer characteristics of graded channel (Si + Ge) hetero-
junction TFET devices of varying channel length [40]
6 Source Engineering
Kim et al. came up with a novel Tunnel FET structure
in which Germanium (Ge) was used as the source mate-
rial in fully raised mode [46], as unveiled in Fig. 57. Due
to the low band gap of Ge-source, their proposed device
intended to achieve a higher ON-state current. However,
they demonstrated in their work that ON-state current can
be further increased by taking the Germanium-source in
fully and partially elevated modes. In partially-elevated
and planner source TFETs, lateral tunneling was first
found to occur between the lower corner of the source
and the channel when gate voltage was effectively low.
Fig. 54  (a) Schematic of GCH-TFET (b) Band diagram of GCH-
TFET [42]
13
Silicon (2023) 15:1–23
Fig. 55  Transfer characteristics showing reduced OFF-State current
[42]
This lateral tunneling mainly occurred due to a significant
potential drop of the drain voltage across source-channel
interface and later vertical tunneling started dominat-
ing over the lateral tunneling once the gate voltage was
increased beyond a certain value. This is the reason that
average SS was found more in the partially-elevated and
planner structures. But they found that drain voltage was
mostly dropped within the fully-elevated Germanium-
source which enhanced the vertical tunneling by getting
coupled with the applied gate voltage, and lateral tun-
neling was almost undone due to an insignificant poten-
tial drop across the source-channel interface, as shown in
Fig. 56  Transfer characteristics showing improved ON-State current
[42]
Silicon (2023) 15:1–23
Fig. 57  Device structure of partially and fully raised germanium
source [46]
Fig. 58. Furthermore, this fully elevated Ge-source was
found showing an improved energy delay performance,
thus allowing for the ultra-low power applications. How-
ever, the proposed device is found to be less favourable for
high frequency application because of the low ON-state
current.
In this paper [47], Wu et al. proposed a structure of tunnel
FET with two source materials having different energy gap
in the stacked manner and they called it as hetero stacked
tunnel FET (HS-TFET), as shown in Fig. 59. They used sili-
con in the upper layer of source while germanium, a rela-
tively smaller energy gap material, was used in the underly-
ing layer. As the tunneling of charge carriers mainly occur at
the surface of the channel when gate voltage is low, a larger
Fig. 58  Raised Germanium source Tunnel FET Transfer characteris-
tics [46]
19
Fig. 59  Schematic of source-stack TFET [47]
band gap material in the upper layer of source causes a lower
subthreshold leakage current. Further, the tunneling width is
found narrower in deep of the channel at higher gate voltage,
the underlying Ge layer provides a higher tunneling rate of
the charge carrier in HS-TFET as compared with Si in the
conventional TFET. Based on the simulation results, they
claimed that an optimized structure of HS-TFET is capable
to achieving at least two decades more I­ ON than that in the
conventional TFETs even without compromising with the
leakage current. A comparison between the Transfer char-
acteristics of these device is shown in Fig. 60.
In this paper [48], Bagga et al. proposed a Tunnel FET
structure using double source regions to enhance the ON-
state current, as shown in Fig. 61. Double source regions
along with the intrinsic channel, provides a larger tunneling
area which, in turn, increased the ON-state current in their
Fig. 60  Transfer characteristics of Ge source TFET, Si TFET, and
Hetero stacked TFET [47]
13
20 Silicon (2023) 15:1–23

Fig. 61  Schematic of Double source TFET [48] Fig. 62  Output characteristics for increased VGS [48]

proposed device. In this device, tunneling occurs in the per-

pendicular direction to the gate electrode in tunnel gap (LTG)
which was also found contributing to the charge carriers tun-
neling from source to drain. They observed that by increas-
ing the height of the source, ON-state current can be further
increased. It was also found that an increment in the width of
gate causes the reduction in ON-state current. Furthermore,
it was also illustrated that an increment in the doping reduces
the channel resistance, and due to this, tunneling width at
source-channel interface found decreases, which further
improves the tunneling probability and so, the ON-state cur-
rent. As compared to the U-Shaped-Gate TFET, an oxide layer
was inserted between source and drain regions which worked
as an isolator, thus helping to avoid a direct coupling between
these two regions, and as a result of this the leakage current is
reduced. Output characteristics and transfer characteristics are
shown in Figs. 62 and 63, respectively. A clear comparison
was observed between TSR-TFET and other models in the
Fig. 63  Transfer characteristics by varying VDS Voltage [48]
literature which is tabulated in Table 1 [48].
In this paper [51], researchers have come up with a new
structure of TFET to improve the ON-state current, and here by the gate from both top and bottom sides, thereby ena-
the source is extended into the channel, as shown in Fig. 64. bling the vertical tunneling along with lateral component.
Due to the source-extension, channel was found surround- It was observed that drain current is mostly shared by the
ing the source from three sides, and source was overlapped charge carriers tunneling from corner of the source-channel
Table 1  Performance Performance parameters PT-TFET [48] LT-TFET [49] ML-TFET [50] TSR-TFET [48]
comparison of TSR-TFET with
existing structures Turn on Voltage 0.525 0.265 0.61 0.225
Ion(µA/µm) 0.3002 5.28 0.466 10.3
Ion/Ioff 108 109 108 1010
SSavg(mv/dec) 97.3 69.02 68.47 66.25

13
Silicon (2023) 15:1–23 21

Fig. 64  Device structure of source extension TFET [51]

Fig. 66  Energy band diagram [51]

current almost remains unchanged when width of the source-

extension is increased beyond 30 nm. Moreover, they dem-
onstrated that this structure of TFET could improve the
various analog/RF parameters such as, transconductance,
gain-bandwidth product (gm/(2*Pi*10*Cgd)) and cut-off
frequency (f t = gm/(2*Pi*Cgg)) and so on. The respective
Band diagram is depicted in Fig. 66. However, the proposed
device shows a maximum gain-bandwidth product (GBP) of
3.3GHZ at gate voltage of 1.2 V and thereafter, it degrades
due to reduction in gm. A clear contrast was found between
ESDG-TFET and other models in the literature, as shown
in Table 2 [51].

Fig. 65  Transfer characteristics by varying SW [51]
interface fronting the drain terminal. It is clearly depicted
in Fig. 65 that SS of the device is improved while ON-state
7 Conclusion
In this article, different techniques to improve the ON-state
current and SS in Tunnel FETs have been analysed and
discussed using the concept of device physics. By using a
proper combination of the dielectric materials used for the

Table 2  Comparison of the Performance parameters Ion/Ioff SSavg (mV/dec) gm (µs/µm) FT (GHZ) GBP (GHZ) Lattice Heat
ESDG-TFET with previous capacity (J/K-
models cm3)

GoSo n-TFET [52] ∼105 100  −  −   −  −   −  −  1.72

T-TFET [53] ∼107 14.07  −  −   −  −   −  −  1.68
GoSCOP- TFET [38] ∼109 48 0.4 1.19  −  −  1.96
TG-TFET [54] ∼1010 24.4 232 11.9 2.3 1.54
HGDG-TFET [55] ∼1010 52 4.4 5 1.8 1.39
FTJTFET [56] ∼1011 40 0.18 28  −  −  1.65
DG-TFET [57] ∼1011  −  −  25 13  −  −  1.46
ESDG-TFET [51] ∼1012 12.24 238 37.7 3.4 1.73

13
22
gate-oxide and spacer, ION can be significantly improved,
and subthreshold leakage can also be reduced, which fur-
ther improves the current switching ratio. It is concluded
in this article that a dielectric pocket placed at the channel-
source interface can improve the tunneling probability by
reducing the tunneling width. Furthermore, a low-κ and
high-κ dielectric materials for the gate-oxide near to drain
and source, respectively can simultaneously reduce the
ambipolar conduction and enhance the ION along with SS
in Tunnel FETs. Shape of the channel can play a signifi-
cant role in improving the On-state behaviour by enabling
the tunneling of charge carriers in both lateral and vertical
directions. It is also concluded in this work that ION and
SS in Tunnel FETs can be improved by placing a smaller
band-gap material at the place, where tunneling of the
charge carriers mainly happen. Furthermore, an extension
of source into the channel can enable the line tunneling
along with point tunneling, which enhances the overall
tunneling area, thus improving the On-state performances
of Tunnel FETs. Finally, it is concluded that the major
roadblock of Tunnel FETs i.e. ON-state current can be
significantly improved and matched with that in the con-
ventional MOSFET with the proper selection of an engi-
neering technique.
Acknowledgements  The authors would like to express their gratitude
to VIT-AP University, Amaravati for providing the Sentaurus TCAD
simulator for simulation work.
Author Contributions  Both the authors have equally contributed to the
manuscript.
Data Availability  All necessary data and material are included in the
manuscript.
Declarations  tices Microstruct 113:261–270
Ethics Approval  On behalf of co-author, the corresponding author
claims that there are no ethical issues.
Consent to Participate  Both the authors have equally contributed to
the manuscript.
Consent for Publication  Both the authors give consent for publication.
Disclosure of Potential Conflicts of Interest  On behalf of co-author,
the corresponding author claims that there is no conflict of interest.
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