Introduction To VLSI Design

and
Design Challenges

By
A.D.Darji, PhD (IIT Bombay)

9/17/2020 VLSI Design Lab, SVNIT

Any Device, Any Time, Any Where

9/17/2020 VLSI Design Lab, SVNIT

 Babbage Difference Engine

9/17/2020 VLSI Design Lab, SVNIT

From Tubes

9/17/2020 VLSI Design Lab, SVNIT

 ENIAC
(Electrical Numerical Integrator And Calculator)

• Developed in 1946 by John Mauchly

9/17/2020 VLSI Design Lab, SVNIT

To Transistors

Modern-day electronics began with the

invention in 1947 of the transfer resistor, also
known as the bi-polar transistor , by Bardeen
et.al at Bell Laboratories

9/17/2020 VLSI Design Lab, SVNIT

 TX-0 (MIT) and the Transistor 1 (Manchester)

9/17/2020 VLSI Design Lab, SVNIT

What is Integrated Circuit?

9/17/2020 VLSI Design Lab, SVNIT

 First Useful IC 1961

9/17/2020 VLSI Design Lab, SVNIT

Summary : Transistor Revolution

• Transistor –Bardeen (Bell Labs) in 1947
• Bipolar transistor – Schockley in 1949
• First bipolar digital logic gate – Harris in 1956
• First monolithic IC – Jack Kilby in 1959
• First commercial IC logic gates – Fairchild 1960
• TTL – 1962 into the 1990’s
• ECL – 1974 into the 1980’s
TTL had a higher integration density than ECL

Power – puts an upper limit on the number of gates that can be reliably
integrated on a single die

9/17/2020 VLSI Design Lab, SVNIT

 History of CMOS
• omplementary metal–oxide–semiconductor (CMOS), also known
as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is
a type of metal–oxide–semiconductor field-effect
transistor (MOSFET) fabrication process that uses complementary and
symmetrical pairs of p-type and n-type MOSFETs for logic
functions.[1] CMOS technology is used for constructing integrated
circuit (IC) chips, including microprocessors, microcontrollers, memory
chips (including CMOS BIOS), and other digital logic circuits, and replaced
earlier transistor-transistor logic (TTL) technology.
• CMOS technology is also used for analog circuits such as image
sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and
highly integrated transceivers for many types of communication.

9/17/2020 VLSI Design Lab, SVNIT

• Mohamed M. Atalla and Dawon Kahng invented the MOSFET at Bell

Labs in 1959, and then demonstrated the PMOS (p-type MOS)
and NMOS (n-type MOS) fabrication processes in 1960. These processes
were later combined and adapted into the complementary MOS (CMOS)
process by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in
1963. RCA commercialized the technology with the trademark "COS-MOS"
in the late 1960s, forcing other manufacturers to find another name,
leading to "CMOS" becoming the standard name for the technology by the
early 1970s.
• CMOS eventually overtook NMOS as the dominant MOSFET fabrication
process for very large-scale integration (VLSI) chips in the 1980s, and has
since remained the standard fabrication process for
MOSFET semiconductor devices in VLSI chips. As of 2011, 99% of IC chips,
including most digital, analog and mixed-signal ICs, are fabricated using
CMOS technology.[2]

9/17/2020 VLSI Design Lab, SVNIT

• Two important characteristics of CMOS devices are high noise
immunity and low static power consumption.[3] Since
one transistor of the MOSFET pair is always off, the series
combination draws significant power only momentarily during
switching between on and off states. Consequently, CMOS
devices do not produce as much waste heat as other forms of
logic, like NMOS logic or transistor–transistor logic (TTL),
which normally have some standing current even when not
changing state. These characteristics allow CMOS to integrate
a high density of logic functions on a chip. It was primarily for
this reason that CMOS became the most widely used
technology to be implemented in VLSI chips.

9/17/2020 VLSI Design Lab, SVNIT

MOSFET Technology
• MOSFET transistor - Lilienfeld (Canada) in 1925
and Heil (England) in 1935
• CMOS – 1960’s, but plagued with manufacturing
problems
• PMOS in 1960’s (calculators)
• NMOS in 1970’s (4004, 8080) – for speed
• CMOS in 1980’s – preferred MOSFET technology
because of power benefits
• BiCMOS, Gallium-Arsenide, Silicon-Germanium
• SOI, Copper-Low K, …
9/17/2020 VLSI Design Lab, SVNIT
 Moore’s Law

9/17/2020 VLSI Design Lab, SVNIT

Moore’s Law
• In 1965, Gordon Moore predicted that the number
of transistors that can be integrated on a die would
double every 18 to 14 months (i.e., grow
exponentially with time).
• Amazingly visionary – million transistor/chip barrier
was crossed in the 1980’s.
– 2300 transistors, 1 MHz clock (Intel 4004) - 1971
– 16 Million transistors (Ultra Sparc III) -1998
– 42 Million, 2 GHz clock (Intel P4) - 2001
– 125 Million 3 4Ghz (Intel P4 Prescott)- 2004
– 234 Million, IBM Cell processor - 2005
– 1.7 Billion, 1.6Ghz (Intel Itanium-2)-2006

9/17/2020 VLSI Design Lab, SVNIT

 Carnegie Mellon

Intel x86 Evolution: Milestones

Name Date Transistors MHz
 8086 1978 29K 5-10
 First 16-bit Intel processor. Basis for IBM PC & DOS
 1MB address space
 386 1985 275K 16-33
 First 32 bit Intel processor , referred to as IA32
 Added “flat addressing”, capable of running Unix
 Pentium 4E 2004 125M 2800-3800
 First 64-bit Intel x86 processor, referred to as x86-64
 Core 2 2006 291M 1060-3333
 First multi-core Intel processor
 Core i7 2008 731M 1600-4400
 Four cores (our shark machines)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 17

Intel x86 Processors, cont.

Carnegie Mellon

 Machine Evolution
 386 1985 0.3M
 Pentium 1993 3.1M
 Pentium/MMX 1997 4.5M
 PentiumPro 1995 6.5M
 Pentium III 1999 8.2M
 Pentium 4 2000 42M
 Core 2 Duo 2006 291M
 Core i7 2008 731M

 Added Features
 Instructions to support multimedia operations
 Instructions to enable more efficient conditional operations
 Transition from 32 bits to 64 bits
 More cores
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 18
 Intel x86 Processors, cont.
Carnegie Mellon

 Past Generations Process technology

 1st Pentium Pro 1995 600 nm
 1st Pentium III 1999 250 nm
 1st Pentium 4 2000 180 nm
 1st Core 2 Duo 2006 65 nm Process technology dimension
 Recent Generations = width of narrowest wires
(10 nm ≈ 100 atoms wide)
1. Nehalem 2008 45 nm
2. Sandy Bridge 2011 32 nm
3. Ivy Bridge 2012 22 nm
4. Haswell 2013 22 nm
5. Broadwell 2014 14 nm
6. Skylake 2015 14 nm
 Upcoming Generations
 Kaby Lake 2016? 14 nm
 Cannonlake 2017? 10 nm
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 19

2016 State of the Art: Skylake

Carnegie Mellon

 Mobile Model: Core i7

 2.6-2.9 GHz
 45 W

 Desktop Model: Core i7

 Integrated graphics
 2.8-4.0 GHz
 35-91 W

 Server Model: Xeon

 Integrated graphics
 Multi-socket enabled
 2-3.7 GHz
 25-80 W
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 20
 Carnegie Mellon

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 21

Integrated Circuit Complexity

9/17/2020 VLSI Design Lab, SVNIT

 Integrated Circuit Complexity

9/17/2020 VLSI Design Lab, SVNIT

Intel 4004 Microprocessor (1971)

4004 In (1971) versus 8086 in (1978)

1 MHz clock rate 10 MHz clock rate
5volt VDD 5volt VDD
10 micron 3 micron
5K transistors 29K transistors

9/17/2020 VLSI Design Lab, SVNIT

 Intel Pentium (IV) Microprocessor

P5 in 1994 versus P6 (Pentium Pro) in 1996

75 to 100 MHz clock rate 150 to 200 MHz clock rate
91 mm**2 196 mm**2
3.3M transistors 5.5M transistors
(1M in cache) (external cache)
0.35 micron 0.35 micron
4 layers metal 4 layers metal
3.3volt VDD 3.3volt VDD
>20W typical power dissipation 387 Pins
9/17/2020 VLSI Design Lab, SVNIT

Quad Core Processors

9/17/2020 VLSI Design Lab, SVNIT

 Moore’s Law in Microprocessors
Transistors on lead microprocessors double every 2 years

1000

100
2X growth in 1.96 years!

10
Transistors (MT)

P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

9/17/2020 VLSI Design Lab, SVNIT Courtesy, Intel

Evolution in DRAM Chip Capacity

human memory
human DNA
100000000
64,000,000

10000000
4X growth every 3 years! 16,000,000 0.07 m
4,000,000
0.1 m
1000000 1,000,000
0.13 m
K b it c a p a c ity /c h ip

book 256,000 0.18-0.25 m

100000
64,000
0.35-0.4 m
16,000
10000 0.5-0.6 m
4,000 encyclopedia
0.7-0.8 m
1000 1,000 2 hrs CD audio
1.0-1.2 m 30 sec HDTV
256
100 1.6-2.4 m
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year
 Die Size Growth
Die size grows by 14% to satisfy Moore’s Law

100

P6
Die size (mm)

486 Pentium ® proc

10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
9/17/2020 Courtesy, Intel
VLSI Design Lab, SVNIT

Clock Frequency
Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years

P6
Frequency (Mhz)

100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Courtesy, Intel
9/17/2020
VLSI Design Lab, SVNIT
 Power Dissipation
Lead Microprocessors power continues to increase
100

P6
Pentium ® proc
10
Power (Watts)

486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

9/17/2020 VLSI Design Lab, SVNIT Courtesy, Intel

Power Density
10000
Rocket
Nozzle
1000
Power Density (W/cm2)

Nuclear
100 Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

VLSI Design Lab, SVNIT Courtesy, Intel
9/17/2020
 Design Productivity Trends
10,000 100,000

1,000 Logic Tr./Chip 10,000

Logic Transistor per Chip (M) Tr./Staff Month.
100 1,000

(K) Trans./Staff - Mo.

Complexity

Productivity
10 58%/Yr. compounded 100
Complexity growth rate

1 10

x x
0.1 1
xx 21%/Yr. compound
x
x x
x Productivity growth rate
0.01 0.1

0.001 0.01
1989

1991

1993

1995
1997

1999

2001
2003

2005
1981

1983
1985

1987

2007

2009
Complexity outpaces design productivity

VLSI Design Lab, SVNIT

Courtesy, ITRS Roadmap
9/17/2020

Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4

For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999

doubling every two years)

http://www.itrs.net/ntrs/publntrs.nsf
Microprocessor Evolution

45 nm Nehalem CPU

Multiple cockling Domain (11 PLL) and Local control

 SRAM Dynamic Sleep Transistor

5-10x leakage reduction during

“retention/standby”

Integrated Power Gates

 Nehalem Turbo Mode

Nehalem Power Control Unit

PC Platform Comparison

Microprocessor Evolution
The Old Era of Microprocessor Scaling

The New Era of Microprocessor Scaling

 Device: The MOS Transistor
Gate oxide

Polysilicon
Gate
Source Drain Field-Oxide
n+ n+ (SiO2)

p substrate
p+ stopper

Bulk contact

CROSS-SECTION of NMOS Transistor

9/17/2020 VLSI Design Lab, SVNIT

Why Scaling?
• Technology shrinks by ~0.7 per generation
• With every generation can integrate 2x more functions
on a chip; chip cost does not increase significantly
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population does not double every two
years…
• Hence, a need for more efficient design methods
– Exploit different levels of abstraction

9/17/2020 VLSI Design Lab, SVNIT

 Scaling Trends

Transistor dimensions scale to improve performance, reduce

power and reduce cost per transistor
9/17/2020 VLSI Design Lab, SVNIT

MOSFET Scaling

Classical MOSFET scaling was first described in 1974

9/17/2020 VLSI Design Lab, SVNIT

 30 Years of MOSFET Scaling

9/17/2020 VLSI Design Lab, SVNIT

Future Scaling Challenges

9/17/2020 VLSI Design Lab, SVNIT

 Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

9/17/2020 VLSI Design Lab, SVNIT

9/17/2020 VLSI Design Lab, SVNIT

 Major Design Challenges
• Microscopic issues • Macroscopic issues
– ultra-high speeds – time-to-market
– power dissipation and – design complexity
supply rail drop (millions of gates)
– growing importance of – high levels of abstractions
interconnect – reuse and IP, portability
– noise, crosstalk – systems on a chip (SoC)
– reliability, manufacturability – tool interoperability
– clock distribution

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs

Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M
9/17/2020 VLSI Design Lab, SVNIT

Summary
• Digital integrated circuits experience
exponential growth in complexity (Moore’s
law) and performance
• Design in the deep submicron (DSM) era
creates new challenges
– Devices become somewhat different
– Global clocking becomes more challenging
– Interconnect effects play a more significant role
– Power dissipation may be the limiting factor

9/17/2020 VLSI Design Lab, SVNIT

 Fundamental Design Metrics
• Functionality
• Cost
– NRE (fixed) costs – One time cost factor, design effort, Mask
Generation
– RE (variable) costs -silicon processing, packaging, test, part cost
proportional to product volume and chip area
• Reliability, robustness
– Noise margins
– Noise immunity
• Performance
– Speed (delay)
– Power consumption; energy
• Time-to-market
9/17/2020 VLSI Design Lab, SVNIT

Cost of Integrated Circuits

• NRE (non-recurring engineering) costs
– Fixed cost to produce the design
• design effort
• design verification effort
• mask generation
– Influenced by the design complexity and designer productivity
– More pronounced for small volume products
• Recurring costs – proportional to product volume
– silicon processing
• also proportional to chip area
– assembly (packaging)
– test
fixed cost
cost per IC = variable cost per IC + -----------------
volume
9/17/2020 VLSI Design Lab, SVNIT
 NRE Cost is Increasing

9/17/2020 VLSI Design Lab, SVNIT

Silicon Wafer
Single
die

Wafer

From http://www.amd.com

9/17/2020 VLSI Design Lab, SVNIT

 Recurring Costs
cost of die + cost of die test + cost of packaging
variable cost = ----------------------------------------------------------------
final test yield
cost of wafer
dies per wafer × die yield
cost of die = -----------------------------------

 × (wafer diameter/2)2  × wafer diameter

dies per wafer = ----------------------------------  ---------------------------
die area  2 × die area

die yield = (1 + (defects per unit area × die area)/)-

9/17/2020 VLSI Design Lab, SVNIT

Cont.
• Alpha depends upon the complexity of the
manufacturing process (and is roughly proportional
to the number of masks). A good estimate for
today’s complex CMOS process is alpha = 3.
• Defects per unit area is a measure of the material
and process-induced faults. A value between 0.5 and
1 defects/cm2 is typical today but strongly depends
upon the maturity of the process

9/17/2020 VLSI Design Lab, SVNIT

 Yield Example
 Example
 wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
 = 3 (measure of manufacturing process complexity)
 252 dies/wafer (remember, wafers round & dies square)
 die yield of 16%
 252 x 16% = only 40 dies/wafer die yield !

 Die cost is strong function of die area

 proportional to the third or fourth power of the die area

9/17/2020 VLSI Design Lab, SVNIT

Reliability
Noise in Digital Integrated Circuits
• Noise – unwanted variations of voltages and currents at the
logic nodes
 from two wires placed side by side
 capacitive coupling v(t)
- voltage change on one wire can
influence signal on the neighboring wire
- cross talk
 inductive coupling i(t)

- current change on one wire can

influence signal on the neighboring wire

VDD
 from noise on the power and ground supply rails
 can influence signal levels in the gate

9/17/2020 VLSI Design Lab, SVNIT

 Example of Capacitive Coupling
• Signal wire glitches as large as 80% of the supply voltage will
be common due to crosstalk between neighboring wires as
feature sizes continue to scale

Crosstalk vs. Technology

Pulsed Signal
0.12m CMOS
0.16m CMOS

Black line quiet

Red lines pulsed 0.25m CMOS
Glitches strength vs technology 0.35m CMOS

From Dunlop, Lucent, 2000

9/17/2020 VLSI Design Lab, SVNIT

Static Gate Behavior

• Steady-state parameters of a gate – static behavior – tell how
robust a circuit is with respect to both variations in the
manufacturing process and to noise disturbances.
• Digital circuits perform operations on Boolean variables
x {0,1}
• A logical variable is associated with a nominal voltage level
for each logic state
1  VOH and 0  VOL

VOH = ! (VOL)
V(x) V(y)
VOL = ! (VOH)

 Difference between VOH and VOL is the logic or signal

swing Vsw
9/17/2020 VLSI Design Lab, SVNIT
 DC Operation
Voltage Transfer Characteristics (VTC)
 Plot of output voltage as a function of the input voltage

V(y) V(x) V(y)

f
VOH = f (VIL)
V(y)=V(x)

Switching Threshold
VM

VOL = f (VIH)

VIL VIH V(x)

9/17/2020 VLSI Design Lab, SVNIT

Mapping Logic Levels to the Voltage Domain

 The regions of acceptable high and low voltages are delimited
by VIH and VIL that represent the points on the VTC curve
where the gain = -1

V(y)
"1" VOH Slope = -1
VOH
VIH

Undefined
Region
Slope = -1
VIL
VOL
"0" VOL
VIL VIH V(x)

9/17/2020 VLSI Design Lab, SVNIT

 Noise Margins
 For robust circuits, want the “0” and “1” intervals to be a s
large as possible
VDD VDD

VOH "1"
NMH = VOH - VIH
VIH
Noise Margin High Undefined
Region
Noise Margin Low VIL
NML = VIL - VOL
VOL
"0"
Gnd Gnd
Gate Output Gate Input

 Noise margin represents the levels of noise that can be sustained when gates are cascaded
 Large noise margins are desirable, but not sufficient …

The Regenerative Property

 A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level

v0 v1 v2 v3 v4 v5 v6

v2
5

v0
3
V (volts)

1 v1

-1
0 2 4 6 8 10
t (nsec)
9/17/2020 VLSI Design Lab, SVNIT
 Conditions for Regeneration
v0 v1 v2 v3 v4 v5 v6
v1 = f(v0)  v1 = finv(v2)

v3 f(v) finv(v)
v1 v1
v3
finv(v) f(v)

v2 v0 v0 v2

Regenerative Gate Nonregenerative Gate

 To be regenerative, the VTC must have a transient region with a gain

greater than 1 (in absolute value) bordered by two valid zones where the
gain is smaller than 1. Such a gate has two stable operating points.

9/17/2020 VLSI Design Lab, SVNIT

Noise Immunity
 Noise margin expresses the ability of a circuit to
overpower a noise source
 noise sources: supply noise, cross talk, interference, offset

 Absolute noise margin values are deceptive

 a floating node is more easily disturbed than a node driven by a
low impedance (in terms of voltage)

• Noise immunity expresses the ability of the system to process

and transmit information correctly in the presence of noise

• For good noise immunity, the signal swing (i.e., the difference
between VOH and VOL) and the noise margin have to be large
enough to overpower the impact of fixed sources of noise

9/17/2020 VLSI Design Lab, SVNIT

 Directivity
• A gate must be undirectional: changes in an output level
should not appear at any unchanging input of the same
circuit
– In real circuits full directivity is an illusion (e.g., due to
capacitive coupling between inputs and outputs)

• Key metrics: output impedance of the driver and input

impedance of the receiver
– ideally, the output impedance of the driver should be zero
– input impedance of the receiver should be infinity

9/17/2020 VLSI Design Lab, SVNIT

Fan-In and Fan-Out

 Fan-out – number of load gates
connected to the output of the
driving gate
 gates with large fan-out are slower
N

 Fan-in – the number of inputs to

the gate M
 gates with large fan-in are bigger
and slower

9/17/2020 VLSI Design Lab, SVNIT

 The Ideal Inverter
• The ideal gate should have
– infinite gain in the transition region
– a gate threshold located in the middle of the logic swing
– high and low noise margins equal to half the swing
– input and output impedances of infinity and zero, resp.
Vout

Ri = 

Ro = 0

Fanout = 

NMH = NML = VDD/2

Vin
9/17/2020 VLSI Design Lab, SVNIT

The Ideal Inverter

• The ideal gate should have
– infinite gain in the transition region
– a gate threshold located in the middle of the logic swing
– high and low noise margins equal to half the swing
– input and output impedances of infinity and zero, resp.
Vout

Ri = 

Ro = 0

g=- Fanout = 

NMH = NML = VDD/2

Vin
9/17/2020 VLSI Design Lab, SVNIT
 Delay Definitions
Vin Vout

Vin
Propagation delay?
input
waveform

Vout

output
signal slopes?
waveform

9/17/2020 VLSI Design Lab, SVNIT

Delay Definitions
Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr

Delay is a function of fan-in and fan-out (increases load)

 Modeling Propagation Delay
• Model circuit as first-order RC network
vout (t) = (1 – e–t/)V
R
where  = RC
vout
C
Time to reach 50% point is
vin
t = ln(2)  = 0.69 

Time to reach 90% point is

t = ln(9)  = 2.2 

 Matches the delay of an inverter gate

9/17/2020 VLSI Design Lab, SVNIT

Power and Energy Dissipation

• Power consumption: how much energy is consumed per
operation and how much heat the circuit dissipates
– supply line sizing (determined by peak power)
Ppeak = Vddipeak
– battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T  p(t) dt = Vdd/T  idd(t) dt
– packaging and cooling requirements
• Two important components: static and dynamic
E (joules) = CL Vdd2 P01 + tsc Vdd Ipeak P01 + Vdd Ileakage
f01 = P01 * fclock
P (watts) = CL Vdd2 f01 + tscVdd Ipeak f01 + Vdd Ileakage
 Power and Energy Dissipation
• Propagation delay and the power consumption of a gate are
related
• Propagation delay is (mostly) determined by the speed at
which a given amount of energy can be stored on the gate
capacitors
– the faster the energy transfer (higher power dissipation)
the faster the gate
 For a given technology and gate topology, the product
of the power consumption and the propagation delay is
a constant
 Power-delay product (PDP) – energy consumed by the gate
per switching event

 An ideal gate is one that is fast and consumes little

energy, so the ultimate quality metric is
 Energy-delay product (EDP) = power-delay 2

Summary
• Digital integrated circuits have come a long
way and still have quite some potential left
for the coming decades
• Some interesting challenges ahead
– Getting a clear perspective on the challenges
and potential solutions is the purpose of this
course
• Understanding the design metrics that
govern digital design is crucial
– Cost, reliability, speed, power and energy
dissipation
9/17/2020 VLSI Design Lab, SVNIT