Design and Analysis of DG Tunnel FET

Mini Project

Master of Technology (VLSI)

Submitted by

RAJA SEKHAR: (23ECE2006)

MAYANK LOHANI: (23ECE2009)

Under the Supervision of

Dr. Anirban Chatterjee
Associate Professor

Department of Electronics and Communication Engineering

National Institute of Technology Goa

Nov., 2023

Department of Electronics & Communication Engineering, NIT Goa

`

Contents
Abstract ................................................................................................................................ 3
Introduction .......................................................................................................................... 3
Literature Survey .................................................................................................................. 3
Device Structure.................................................................................................................... 4
Simulation Results ................................................................................................................ 6
Conclusion ............................................................................................................................ 7
References ............................................................................................................................ 7

Department of Electronics & Communication Engineering, NIT Goa

Abstract

A 2-dimensional model of double gate Tunnel Field Effect Transistor (DG TFET) with 30-
nm-channel length which has a low subthreshold swing than the Metal Oxide Field Effect
Transistor (MOSFET). The electrical characteristics are demonstrated by the device using
device simulator VisualTCAD. The device structure was constructed using VisualTCAD
schematic and the characteristics were examined and simulated using VisualTCAD Simulator.
Results were analysed and presented to show that difference of subthreshold swing of TFET
and MOSFET.

Introduction

CMOS has been in use for the last few decades due to its high performance and low power
consumption. As technology advances and CMOS downscaling becomes more sophisticated,
a new emerging device known as the tunnel field effect transistor (TFET) has been
introduced that can replace CMOS. TFETs are the most suitable candidate for low power
applications due to their superior performance, such as low power dissipation and low
leakage current.
TFETs are ultralow-power devices that have attracted a lot of interests in recent years [2].
TFETs, in principle, can exhibit sub-kT/q subthreshold slope near OFF-state, which may
achieve a higher Ion/Ioff ratio with the reduced gate voltage range. However, a physics-based
analytical study of TFET is essential toward the understanding of the device operation.
Tunnel FETs are gated p-i-n diodes, or less commonly, gated p-n diodes. To switch the device
on, the diode is reverse biased, and a voltage is applied to the gate. Since a reverse bias is
needed across the p-i-n structure in order to create tunneling, and since an NMOS operates
when positive voltages are applied to the drain and gate, the n-region of a Tunnel FET is
referred to as its drain, and the p+ region as its source for an n-type device.

Literature Survey
The short channel effects, velocity saturation, drain induced barrier lowering are the problems
which are existing with MOSFET as scaling is done which limits the sub-threshold slope of
MOSFET to 60mv/decade. In MOSFET channel length (L), channel width (W), gate oxide

Department of Electronics & Communication Engineering, NIT Goa

thickness (tox), depth of source/ drain junction and voltage are scaled by 1/k factor and
channel doping concentration is by k where k is constant. When the above mention scaling
factors are applied to drain current equation, and then drain current scaled by 1/k factor,
which is given by
µCoxW(VG−Vth)2
ID = - (1)
2𝐿

Where VG is gate voltage, Vth is threshold voltage, Cox is capacitance of unit area and µ is
mobility of carrier.

Device Structure
The representation of cross section of DG TFET is shown in fig. 1. The channel width and
length of the device is taken as 30nm. The device structure of TFET resembles that of the
MOSFET with one exception. In the MOSFET, source and drain are doped with the same
type of dopants and the dopant types are opposite to that of substrate, while in a TFET, source
and drain are of opposite doping types and the drain region has a doping type same as that of
substrate with high concentration. According to structural configuration, TFET is a
combination of several devices, the reversed P-I-N diode at the off state, Esaki tunnel diode at
the on state and the MOS diode to form the inversion or accumulation layer when gate
voltage is applied.

Gate

Insulator
Insulator

Source Si Drain

Insulator
Gate

Figure 1: Double Gate Tunnel FET

Open Visual TCAD, go to file select new and then device drawing. Draw the boundary for
the device with dimension 0.08µm × 0.01 µm. Draw the rectangular box on top of the
substrate and as well as at the bottom of the substrate with dimensions 0.086µm × 0.004 µm.
Now inside the both insulating layer boxes we can draw the gate terminal with dimensions
0.03µm × 0.002µm. Draw the source and drain terminals with dimensions 0.003µm × 0.01
µm (as shown in below fig 2).

Department of Electronics & Communication Engineering, NIT Goa

After drawing the device boundaries label the regions as for substrate choose Si material, for
insulating layer as SiO2, for gate N-poly, and for drain and source as Al material.

Figure 2 DG TFET

Device Dimensions and Parameters

Region Type Concentration (cm-3)
Substrate p-type 1×1016
Source p-type 2×1018
Drain n-type 2×1019

Set box mesh size constrain with mesh size 0.003nm. set mesh size constrain of line size 30
nm and line division of 60. Similarly set mesh size constrain of line size 10 nm and line
division of 20.
Do the meshing and save the file. Go to device drawing, open device simulation. In the
simulation window open the tif file of DG-TFET and the simulation has to be done with the
below given biasing values.

Figure 3: Simulation File of DG TFET

Department of Electronics & Communication Engineering, NIT Goa

Simulation Results
The transfer characteristics (Id-Vg) are performed at constant drain voltage (Vd = 1V) and
threshold Voltage (VT) is noted for the DG MOSFET. It is observed that the drain current
starts rising at lower voltage for the DG TFET as shown in figure 4 whereas the drain current
in conventional MOSFET starts rising at a threshold voltage of higher voltage. It is noticed
that as the threshold voltage required for our device is less than the threshold voltage of
conventional MOSFET, it has the ability to operate with low supply voltage which in turn
reduces the power consumption.

Figure 4 Characteristics of DG-TFET

Figure 5 (a) Transfer Characteristics for MOSFET in Log Scale Figure 5 (b) Transfer Characteristics for DG-TFET in Log Scale

Department of Electronics & Communication Engineering, NIT Goa

Conclusion
The comparison of sub threshold swing of TFET and MOSFET was done. Based on the
results obtained we have concluded that our device has the ability to decrease the sub
threshold swing below the sub threshold swing of conventional MOSFET and it can improve
the switching speed, power consumption as we have operated the device at low supply
voltage. Besides that, TFET can offers improvement on current drive, faster switching times,
lower power consumption and lower voltage operation.

References
[1] Streetman, B. G., & Banerjee, S. (2006). Solid state electronic devices (6th ed.).
Pearson/Prentice Hall.
[2] K. K. Bhuwalka, J. Schulze, and I. Eisele, “A simulation approach to optimize the
electrical parameters of a vertical tunnel FET,” IEEE Trans. Electron Devices, vol. 52, no. 7,
pp. 1541–1547, Jul. 2005.
[3] Christian Philipp Sandow, “Modelling, Fabrication and Characterization of silicon tunnel
field effect transistor”, PhD Thesis Report, RWTH Aachen, Germany, (available online at
http://darwin.bth.rwth-aachen.de/ opus3/volltexte/2011/3453/pdf/3453.pdf)

Department of Electronics & Communication Engineering, NIT Goa