Vol. 34, No.

11 Journal of Semiconductors November 2013

A new approach to extracting the RF parameters of asymmetric DG MOSFETs

with the NQS effect
Sudhansu Kumar Pati1; Ž , Kalyan Koley1 , Arka Dutta1 , N Mohankumar2 ,
and Chandan Kumar Sarkar1
1 Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University,
Kolkata-700032, India
2 SKP College of Engineering, Tiruvannamalai, Tamilnadu-606611, India

Abstract: In analog circuit design an important parameter, from the perspective of superior device performance,
is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi-
tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing
independent bias control for the front and the back gates. Here a non-quasi-static (NQS) small signal model for
DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim-
ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgd1
and Cgd2 , the intrinsic front and back distributed channel resistance, Rgd1 and Rgd2 respectively, the transport de-
lay, m , and the inductance, Lsd . The parameter extraction model for an asymmetric DG MOSFET is validated with
pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The
device simulation is performed with respect to frequency up to 100 GHz.

Key words: asymmetric DGMOSFET; RF modeling; small signal analysis; parameter extraction
DOI: 10.1088/1674-4926/34/11/114002 EEACC: 2570

In this paper, an effective small signal model is developed

1. Introduction
The continuous down scaling of CMOS process technol-
ogy makes it a probable solution for system-on-chip applica-
tions, where the analog and the digital circuits are realized in
the same ICŒ1; 2 . The scope for analog amplifiers and RF cir-
cuits using MOSFETs has increased immensely with scaling.
One of the important breakthroughs in this regard is the estab-
lishment of the DG MOSFET as a device with better RF perfor-
mance, in comparison to the conventional MOSFETŒ3 . How-
ever, the circuit implementation process is faced with many
performance and dependability related issues. The primary is-
sue, related to analog amplifiers and RF circuit application, is
the linearity of the MOSFETŒ4 . The linearity impacts RF cir-
cuits predominantly with respect to harmonic generation, gain
compression and inter-modulation distortion.
It has been established that a DG MOSFET operating in
asymmetric mode, with independent bias control for the front
and the back gate, presents better linearity than its symmetric
mode counterpartŒ4; 5 . This improvement in the linearity is as-
sociated with better control over the channel inversion, drain
current and the threshold voltageŒ6 . Also, asymmetrical DG
MOSFETs are more popular as compared to symmetrical DG
MOSFETs for analog circuit applications because the front gate
functionality can be tuned through the bottom gate bias. It has
a number of significant effects for circuit designŒ7; 8 : such as
reduction of parasitic and layout area, additional circuit func-
tionalitiesŒ9 , improved channel control, reduced process varia-
tion sensitivityŒ10 , higher operation speed, and low power con-
sumption with respect to equivalent conventional circuits.
for an asymmetrical mode DG MOSFET, considering non-
quasi-static effects, for circuit implementation suitable for high
frequency operation. The basic principle behind this model lies
in the use of superposition theory for estimation of the influ-
ence of the front and back gate over the channel. Subsequently,
the RF parameters are extracted from the model, validated and
analyzed. The following sections are organized as device struc-
ture and simulation, small-signal equivalent circuit, extraction
of intrinsic parameters, results and discussion, and finally the
conclusion.
2. Device structure and simulation
The structure of the double gate MOSFET analyzed here
is shown in Fig. 1. The device is specified by gate length (Lg /
of 45 nm, gate height, tg of 10 nm, gate overlap length tov of
3 nm and intrinsic ultra-thin silicon body, with 16 nm thick-
ness (tsi /. The source and drain length (Xsd / are fixed at 50 nm,
analogous with that the upper and the lower gate SiO2 dielec-
tric thickness, tox is fixed at 1.9 nm. The doping of the highly
doped source/drain regions of the device is 1020 cm 3 consid-
ering lateral straggle as results of diffusion of S/D dopants into
the extension and the channel region. In this work, Gaussian
type lateral straggle is considered. The channel has a lightly
doped p-type silicon body with doping concentration of 1016
cm 3 . The device is simulated using the Sentaurus TCADŒ12
with the standard density gradient model. Before simulation
the mobility is calibrated with the standard experimental data
from Ref. [13]. The Aurora mobility model is used to find the
carrier mobility in the device, which depends on ionized im-

† Corresponding author. Email: sudhansupt@gmail.com

Received 3 December 2012, revised manuscript received 7 January 2013 © 2013 Chinese Institute of Electronics

114002-1
J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.

Fig. 1. The cross sectional view of double gate MOSFET. tsi , tox and
tov are the body, oxide and overlap of the gate thickness respectively. Fig. 3. Extrinsic parasitic source and drain resistances (Rs and Rd /
Lg is gate length. Ns , Nd and Nb are doping concentration of source, extracted using the channel resistance method.
drain and body respectively. In this work we consider Lg D 45 nm,
tox D 1.9 nm, tov D 3 nm, tg D 10 nm, xsd D 50 nm, tsi D 16 nm, Ns
D 1020 cm 3 D Nd and Nb D 1016 cm 3 .

Fig. 2. The equivalent circuit of the device shows that the extrinsic
components can be evaluated at off condition of the device. Cgdo and
Cgso are the gate to drain and the gate to source overlap capacitances
respectively. Cinnerfringe is the inner fringing capacitance of the de-
vice. Rs and Rd are the source and drain extrinsic parasitic resistance
respectively.

purity scattering and temperature. For accurate estimation of

active carrier lifetime and carrier density, the Shockley–Read–
Hall (SRH) recombination and incomplete ionization models
are assimilated.
3. Small-signal equivalent circuit
In this section the small-signal equivalent model for asym-
metric operation of a double gate nMOSFET is designed. For
this purpose initially the intrinsic parameters of the device are
evaluated from y-parameter analysisŒ14 .
Figure 2 represents an equivalent circuit model of the de-
vice depicting the intrinsic and the extrinsic components. For
an accurate extraction of intrinsic components, the extrinsic
parasitic resistances (i.e. Rs and Rd / and capacitances (i.e. Cgso
and Cgdo / must be de-embedded. The source and drain resis-
tances are extracted by using the channel resistance method as
shown in Fig. 3 and are obtained as Rs D Rd D 8.31 . To
de-embed parasitic capacitances, the device is simulated at the
zero gate bias and drain voltage. The gate overlap capacitances
including inner fringe capacitance as shown in Fig. 2. Cinnerfringe
Fig. 4. The intrinsic small signal equivalent circuit of asymmetric DG-
MOSFET. These components can be evaluated after de-embedding
the extrinsic components Cgdo , Cgso , Rs and Rd .
C Cgdo and Cinnerfringe C Cgso are extracted from y-parameters
Y11 and Y12 . Since the device is operated in the strong inver-
sion, the inner fringe capacitance is negligible and thus the ex-
trinsic capacitances are obtained as Cgso D 0.3396 fF and Cgdo
D 0.3067 fF.
Figure 4 shows the small signal equivalent circuit of in-
trinsic components after de-embedding the parasitic capaci-
tances and resistances. Rgs1 , Rgs2 , Rgd1 and Rgd2 are the dis-
tributed channel resistances, Cgs1 , Cgs2 , Cgd1 and Cgd2 are the
distributed channel capacitances. The small signal drain con-
ductance (gds / and mutual conductance (gmy / are represented
by gm1 and gm2 respectively. Lsd is the inductance taking into

114002-2
J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.

ˇ
int ˇ j!Cgdy
Y12 Gz D0
D ; (2)
1 C j!Rgdy Cgdy

ˇ
int ˇ gmy j!Cgdy
Y21 Gz D0
D ; (3)
1 C j!m 1 C j!Rgdy Cgdy

ˇ
int ˇ j!Cgdy j!Cgdz
Y22 Gz D0
D C
1 C j!Rgdy Cgdy 1 C j!Rgdz Cgdz
gds
C : (4)
1 C j!Lsd gds
Fig. 5. Small signal equivalent circuit of an asymmetric DGMOSFET The Y int -parameter expressions can be simplified by as-
for two port analysis. Asymmetric analysis contains two conditions 2 2
suming ! 2 Rgsy 2 2
Cgsy  1, ! 2 Rgdy Cgdy  1, ! 2 m2  1,
for evaluation of intrinsic components. Condition1: Gate 2 and source
grounded, i.e. GyD1 ¤ 0, D ¤ 0, GzD2 D 0 and S D 0. Condition 2: ! 2 Rgsz2 2
Cgsz  1, and ! 2 L2sd gds 2
 1. This is because the small
Gate 1 and source grounded, i.e. GyD2 ¤ 0, D ¤ 0, GzD1 D 0 and signal parameters are extracted for low frequency. The simpli-
S D 0. fied expressions can be written as
ˇ  

int ˇ 2 2 2
Y11 Gz D0
 ! Cgsy R gsy C C gdy R gdy C j! Cgsy C Cgdy ;
account the effect of the time constant m as a result of the non ˇ (5)
int ˇ 2 2
quasi static (NQS) effect. Here, the NQS effect is the delay in Y12 Gz D0
 ! Cgdy R gdy j!C gdy ; (6)
charging of the terminal capacitances because of the high fre- ˇ
int ˇ 2 2


Y21 Gz D0  gmy ! Cgdy Rgdy j! m gmy C Cgdy ; (7)
quency operationŒ15 . This delay is incorporated in the small  
ˇ
signal model considering Lsd . In a DGMOSFET electrostatic int ˇ
Y22  g ds C ! 2
C 2
R gdz C C 2
R gdy
Gz D0 gdz gdy
control over the channel is better and drain-induced barrier
loweringŒ16 21 is highly subsidized and hence not considered 2


C j! Cgdz C Cgdy Lsd gds : (8)
here.
The small signal parameters such as Cgsy , Cgdy , Cgdz , Rgsy ,
The small signal equivalent circuit of the device here is
Rgdy , gmy , gds ; m and Lsd of the equivalent circuit are extracted
represented as a four terminal device, which is difficult to ana-
from real and imaginary parts of Y int -parameters and are given
lyze in mixed mode analysis. Thus, for the analysis of the four
by
terminal devices, the circuit is converted to two port networks
considering two separate bias conditions. Figure 5 represents int


Im Y12
the two port representation of the small signal equivalent cir- Cgdy D ; (9)
cuit of Fig. 4 considering the bias conditions where the suffixes !


y and z in Fig. 5 signify two conditions. The two conditions Im Y11 int
considered to convert the network in Fig. 4 into a two port net- Cgsy D Cgdy ; (10)
!
work are stated as follows:

int
First condition: Gate 2 and source grounded i.e. GyD1 ¤ Re Y12
Rgdy D 2
; (11)
0, D ¤ 0, GzD2 D 0 and S D 0. ! 2 Cgdy
Second condition: Gate 1 and source grounded i.e. GyD2 "
#
int
¤ 0, D ¤ 0, GzD1 D 0 and S D 0. 1 Re Y11 2
Rgsy D 2 Cgdy Rgdy ; (12)
However, the analysis of the two cases is similar, since the Cgsy !2
structure of the device is symmetrical about the gates.
ˇ
int ˇ
gmy D Re Y21 ! 2 D0
; (13)

ˇ
4. Extraction of intrinsic parameters int ˇ
gds D Re Y22 ; (14)
! 2 D0

The intrinsic parameters of the asymmetric DG MOSFET "
#

int
described in earlier section were extracted by Y -parameter ana- 1 Im Y21
m D Cgdy ; (15)
lysis. The evaluated Y -parameters comprise of both extrinsic gmy !
and intrinsic components. The intrinsic Y -parameters (Y int / m
were extracted using the approach reported in Ref. [14] by de- Lsd D ; (16)
gds
embedding the extrinsic parasitic resistances and capacitances.

int
The Y int equations thus derived for the asymmetric DG MOS- Im Y22 2
FET for intrinsic parameter extraction are represented as be- Cgdz D Cgdy C Lsd gds ; (17)
!
low:
"
#
int
ˇ j!Cgsy j!Cgdy 1 Re Y22 gds 2
Y int ˇ
11 Gz D0 D C ; (1) Rgdz D 2
!2
Cgdy Rgdy : (18)
1 C j!Rgsy Cgsy 1 C j!Rgdy Cgdy Cgdz

114002-3
J. Semicond. 2013, 34(11) Sudhansu Kumar Pati et al.

Fig. 6. The equivalent capacitance Cgd and resistance Rgd are ex- Fig. 7. The intrinsic capacitance (Cgd / and intrinsic resistance (Rgd /
tracted from both symmetric and asymmetric analysis. By using the with frequency are found to be constant. The capacitance and resis-
superposition principle, the equivalent capacitance and resistance are tance are extracted at Vds D 0.5 V.
evaluated from the asymmetric analysis and compared to symmetric
analysis. These parameters are extracted are found to be constant with
frequency.

5. Results and discussion

In this section the results obtained for the asymmetric oper-
ation of the DGMOSFET are extracted and analyzed. For eval-
uating the equivalent capacitance (Cgd / and resistance (Rgd /
of the asymmetric DGMOSFET, first the intrinsic capacitance
and resistance are extracted analytically. This is performed as
described in an earlier section and is represented by Cgd1 , Rgd1 ,
Cgd2 and Rgd2 for condition 1 (C1) and Cgd2 , Rgd2 , Cgd1 and
Rgd1 for condition 2 (C2). Subsequently, by using the superpo-
sition principle, Cgd and Rgd of an asymmetric DGMOSFET at
conditions Vgs1 D 0.6 V, Vgs2 D 0 V, Vds D 0.55 V and Vgs1 D
0 V, Vgs2 D 0.6 V, Vds D 0.55 V respectively are extracted. The
extracted capacitances Cgd1 and Cgd2 (C1) and resistances Rgd1
and Rgd2 (C1) are considered as a series combination for calcu-
lating effective capacitance and resistance for gate 1. Similarly,
the effective capacitance and resistance are extracted for gate
2. Finally the Cgd and Rgd for an asymmetric DGMOSFET are
evaluated by considering the parallel combination of the effec-
tive capacitance and resistance for gate 1 and gate 2.
The evaluated equivalent Cgd and Rgd are compared with
the symmetric DGMOSFET at Vgs1 D Vgs2 D 0.6 V, Vds D
0.55 V and presented in Fig. 6 and a good match is obtained.
It is established earlier that these parameters remain constant
with frequency variation up to 100 GHzŒ14 .
Figure 7 shows the intrinsic parameters, gate to drain ca-
pacitance, and resistance variation with frequency at different
gate 1 and gate 2 bias, while keeping drain potential constant
at Vds D 0.55 V. It represents that with an increase in the gate
biases, the capacitances also increase and lower the resistances
attributed to increased volume inversion.
Figure 8 shows the variation of Cgd and Rgd with the vari-
ation of gate 1 bias, while keeping Vds D 0.55 V and frequency
constant. The variation was studied for three different gate 2
biases. An increase in capacitance is observed in addition to a
decrease in resistance with increasing gate 1 bias. With an in-
crease in gate bias inversion, charge in the channel is enhanced;
resulting in an improvement in capacitance values and a corre-
Fig. 8. Comparison of resistances (Rgd / and capacitances (Cgd / as
function of gate 1 bias for different gate 2 potential, keeping the drain
potential Vds constant i.e. 0.55 V.
sponding decrease in the resistance values. Thus, the channel
current improves with gate1 bias with an additional advantage
of better control provided by the gate 2 bias.
Figure 9 shows a comparison of Cgd and Rgd with vari-
ations of drain bias extracted for different gate 2 bias keeping
gate 1 bias constant. As the drain voltage is increased the width
of the channel at the drain side is decreased, i.e. the pinch off
region. Due to which the capacitance Cgd reduces with drain
bias, resulting in an increase in resistance Rgd .
Figure 10 shows the time constant (m / and the inductance
(Lsd / with respect to frequency at potential Vgs1 D 0.6 V, Vgs2
D 0 V D Vs and Vds D0.55 V. Lsd and m are evaluated analyt-
ically as in the previous section, and found to be constant up to
100 GHz.
6. Conclusion
An accurate small signal model for an ADG MOSFET
is developed by considering non-quasi-static effects. The de-
vice parameters were extracted for a strong inversion regime
through Y -parameter analysis using the Sentaurus TCAD. The

114002-4
J. Semicond. 2013, 34(11)
Fig. 9. Comparison of the capacitances (Cgd / and the resistances (Rgd /
as a function of drain bias for different gate potentials.
Fig. 10. The time constant (m / and inductance (Lsd / verses frequency
are extracted at Vgs1 D 0.6 V, Vgs2 D 0 V D Vs and Vds D 0.55 V are
found to be constant.
intrinsic parameter extractions are performed after removing
the extrinsic gate-to-drain/source capacitance, inner fringing
capacitance and source/drain resistance from the device para-
meters. Understanding the channel coupling in various bias and
frequency regimes is imperative for circuit design conceptual-
ization and optimization. The bias and frequency regions that
enhance channel coupling are identified. The extracted para-
meters with frequency remain constant up to 100 GHz, which
verifies the validity of our model. Also for validation purposes,
the gate to drain parasitic resistance and the capacitance were
extracted for both DG and ADG MOSFETs at the same biasing
condition and compared. A good match is established between
Cgd and Rgd . It is found that the extraction technique is precise,
consistent and applicable to high frequency ranges.
Acknowledgments
The authors would like to thank the Silicon Institute of
Technology, Bhubaneswar, Odisha and RPS scheme AICTE,
Government of India, for their valuable support in carrying out
this research work.
114002-5
Sudhansu Kumar Pati et al.
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