Microelectronics

Journal

Microelectronics Journal 31 (2000) 701709

www.elsevier.com/locate/mejo

Electrical modeling of the chip scale ball grid array package at radio
frequencies
M.F. Caggiano*, E. Barkley, M. Sun, J.T. Kleban
Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08855-0909USA
Received 3 December 1999; accepted 1 March 2000

Abstract
The CSBGA package is targeted for the next generation of wireless systems, since this packaging technology occupies signicantly less
real estate than conventional packaging. The smaller packages not only accommodate the shrinking size of cellular phones but also contain
lower parasitics, which reduces signal integrity losses. This innovative new software is targeted for the engineer who, at his desktop PC or
workstation, can rapidly generate an accurate radio frequency (RF) electrical model of an entire Chip Scale BGA package. Program operation
consists of entering the available data, and in just minutes, retrieving output that can be used in a SPICE circuit simulation. The focus of this
work is on the frequency dependent parasitics in which the skin depth effects are modeled as additional circuit elements. Routines were
developed to model the frequency dependant variable resistance and inductance with as few components as possible in order to reduce the
complexity of the SPICE topology but still maintain accuracy. The program was designed to be fast and portable contrasting other methods of
modeling in which such attributes were sacriced for greater accuracy. Models of an entire 144 I/O package can be generated in less than
1 min on a SUN Ultra1 workstation. The models generated are targeted for RF systems having a wide range of use across military and
commercial electronics applications. q 2000 Elsevier Science Ltd. All rights reserved.
Keywords: Chip scale BGA; Micro BGA; Electrical packaging modeling; Skin effects; Radio frequency; SPICE modeling

1. Introduction involved with 3D solvers, while still maintaining reasonable

The demand for faster and smaller IC's is increasing.
More transistors are being fabricated on smaller chips
which, to complete the size reduction, demand smaller
packages. The design of the CSBGA looks to provide the
demanding market such a package. The wide spread accep-
tance of the CSBGA package will facilitate the need for fast,
accurate models of new package designs.
CSBGA packages present a new challenge for inductance
and capacitance calculations. Traces, which previously
fanned out in a near parallel fashion from the chip, now
can be found in a variety of new congurations as shown
in Fig. 1. Existing methods, such as 3D solvers, generate
very accurate results but require long set up and run times.
Time is not the only drawback to using a 3D solver. These
expensive programs are complicated and require a good deal
of prociency in order to use them properly. The primary
goal of the CSBGA parasitics program is to speed up the
modeling process by eliminating much of the complexity
* Corresponding author. Tel.: 1 1-732-445-0678; fax: 1 1-732-445-
2820.
E-mail address: cagg@ece.rutgers.edu (M.F. Caggiano).
0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved.
PII: S 0026-269 2(00)00047-1
accuracy [13]. The program, written in C, can be operated
by anyone with basic computer experience, on a wide range
of systems. Along with the usability of the program comes
speed. The generation of the data takes only a minute or two
depending on the system, and is suitable for most applica-
tions where great accuracy may not be needed.
1.1. The model
The circuit model Fig. 2, starts with the wires, which
connect the chip outputs, or wedges, to the bond pads on
the package. The program generates values for self-induc-
tance and resistance of these wires. Also calculated is the
mutual inductance between other wires for the ten nearest
neighbors, (ve on each side of a wire). The capacitance to
ground is calculated along with only two of the nearest
neighbors, since capacitive coupling is small past the third
wire (do to screening effects) and therefore can be
neglected.
After the wire bond, the trace begins. The trace self-
inductance and resistance is calculated in the same manner
as the wires. The traces are much longer than the wires
causing their effects to be more signicant. The capacitance
702 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709

Fig. 1. Example of a CSBGA depicting worst case trace layout. Not all traces and ball locations are displayed in order to improve visibility.

between traces is also computed up to two neighbors away.
However, the mutual inductance is calculated between
every trace in the package, since the size of these packages
forces designers to route traces in many unusual ways (e.g.
traces that fan in could interact with each other even though
they are not near neighbors).
The last elements of the circuit model are via, bottom
trace (if one exists), and solder ball, which are all modeled
as a single element to reduce complexity, however, the
bottom traces will also contribute mutual terms to the top
traces. An additional resistor, modeling a contact resistance,
concludes the chain.
In order to describe accurately the package capaci-
tance, a distributive model is assumed. The rst capa-
citor is the wire capacitance combined with half the
trace capacitance. The second capacitor is the rest of
the trace capacitance combined with the bottom trace
capacitance. This provides a more accurate picture by

Fig. 2. Electrical model of package.

 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709 703

which to model the package and thus completes the

circuit model.

1.2. Radio frequency skin effects

At radio frequency (RF), the penetration of currents and

magnetic elds is governed by the skin effect. The result of
this depth of penetration (skin depth) is frequency depen-
dent resistance and self-inductance. These changes were
studied for round bond wires and for package traces with
rectangular cross sections. A new circuit models the high
frequency self-inductance and resistance by shunting the
elements with simple ladder networks. For a small sacrice
in accuracy, this simple model provides a signicant order
reduction for previously developed ladder networks of
frequency dependent resistance [47]. These circuit models
were added to the previous program [1,2] to extend the
frequency range of accurate simulation.
Fig. 3. High frequency conductors: (a) circular cross-section of conductor
1.3. Data input and output with radius, r, and skin depth, d; (b) rectangular cross-section of conductor
with skin depth, d.
The program requires a geometry le containing the wire
bond locations in Cartesian coordinates along with the
corresponding ball location, and for each trace any relevant linear elements, while the traces are modeled as rectangular
via locations. The output of the program is a SPICE deck or linear elements. The width and thickness of the elements are
circuit le. The circuit le holds all the necessary informa- user entered in the input le and the lengths are computed
tion to simulate the package with the rest of the circuit. A from the data provided by the input geometry le. Since the
sub-circuit style was used in order for easy integration with traces tend to be of greater length than other conductor types
other circuit les. The designer has every ball and bond pad are, their values of inductance are more signicant. Package
node at their disposal to connect to the chip model and the conductors use the following equation [8] for self-induc-
circuit board. The le consists of the sub-circuit node list- tance at low frequencies:
ing, and then each ball followed by the various inductors,
L 2lln2l=reff 2 0:75nH 1
resistors, and capacitors. The mutual inductance terms are
converted to coefcients of coupling, and are printed only if where l is the length of the conductor and reff the effective
they are greater than the cutoff point set by the user. radius (both in cm). Rectangular conductors such as the
package traces use the perimeter of the conductor to obtain
2. Inductance reff.

The CSBGA package contains a variety of conductors 2.2. RF self-inductance

that have values for self and mutual inductance. Self and
mutual inductance are related phenomena based on the
induction of voltage by a varying current. As current
increases or decreases, the magnetic eld surrounding the
conductor expands or contracts. This induces a correspond-
ing voltage that acts as noise to the high-speed switching
signals that run through the package. These inductance
values are calculated using a variety of formulas [810]
which depend on conductor layout and geometry. The accu-
racy of these formulas is acceptable in the RF range (from
DC up to 3 GHz).
2.1. Self-inductance
Self-inductance is phenomena inherent to any current-
carrying conductor and does not depend on its conguration
compared to other elements. The wire bonds, vias, and
solder balls in the package are estimated to be cylindrical
The skin depth, d , is a measure of the higher distribution
of current being carried along the outside skin of the
conductor as compared to the center (see Fig. 3). d
decreases with frequency indicating that more current is
being conducted along narrower depths with increasing
frequencies. The skin depth, d , represents the depth at
which the current density has been attenuated by 1/e as its
value decays exponentially into the conductor. The effects
of varying skin depth on self-inductance can be understood
by approximating a cylindrical wire as a thin hollow tube for
frequencies at which the skin depth is less than the radius of
the wire. The outer radius of the tube is the same as the outer
radius of the cylinder. The inner radius of the tube is just the
radius minus the skin depth. Self-inductance for a straight
wire of any cross section is found by rst dividing the wire
into an innite number of laments with length equal to the
length of the wire and with a circular cross section of
704 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709

LS1 is the value of the self-inductance of the wire at dc,

found from Eq. (1). The parallel combination of the two
inductors equals L1 the self-inductance solved at innite
frequency, from this the value for the shunting inductor
LS2 can be found from
L1 LS1
L S2 nH 4
LS1 2 L1
The value for the resistor is chosen to place the impe-
dance pole at the frequency where the inductance reduces to
Lavg, the average of LDC and L1. The inductance changes
between the dc and innite frequency values in about one
decade. The R can be obtained from
Fig. 4. Enhanced circuit schematic including resistance and inductance skin
effects equivalent models. R vp LS1 1 LS2 V 5
v p can be found from the solution of Eq. (3) and is equal to
innitesimally small area. The self-inductance of the wire is
equal to the sum of the mutual inductances of all the pairs of x2
vp 2
rad=s 6
laments. Or, the self-inductance is equal to the mutual 4pmsr eff
inductance of two parallel straight laments, spaced at the
where
geometric mean distance of all the points of the section from
 
each other [8]. Mutual inductance is inversely proportional 2:617 1:025
to the distance of separation between the two laments, and x 7
T
the geometric mean distance of a tube as described above is
larger than the geometric mean distance of a wire with the and
   
cross section described above. Consequently, as frequency Lavg 2l
is increased, the self-inductance of a solid wire decreases. T4 2 ln 11 8
2l reff
This is due to the smaller skin depth making the conductor's
effective geometric mean distance larger.
A formula for inductance as a function of frequency can 2.4. RF self-inductance results
be found from the following formula: Fig. 5 shows a comparison between the theoretical self-
   
2l mT inductance vs. frequency generated from Table 52 [8] and
L 2l ln 211 nH 2 Eqs. (2) and (3) along with model of inductance generated
reff 4
from Eqs. (4)(8). Fig. 5a is the comparison for a 25.4 mm
where m is the relative permeability and T the frequency (1 mil) diameter gold wire and 3b is a copper conductor with
dependent term and can be found empirically from Table 52 an effective radius of 50.8 mm (2 mils). In Fig. 5a the induc-
given in Ref. [8]. At low frequencies T is equal to one and tance of the gold bond wire changed by about 7% and the
Eq. (2) reduces to Eq. (1). At innite frequency T is equal to error of the model was less than 2% over the range of
zero. Using a computer program that takes data points and frequency. In Fig. 5b the inductance of the copper rectan-
determines a matching function, a series of equations were gular trace changed by about 10% and the error of the model
developed to obtain T as a function of x. Where was less than 2% over the range of frequency.
p
x 2preff 2mf s 3
2.5. Mutual inductance
and s is the conductivity. This means that an equation had
been developed for self-inductance as a function of Mutual inductance is an electromagnetic phenomenon
frequency. where a conductor will, because of its varying magnetic
eld, induce voltages in a nearby conductor. Mutual induc-
2.3. RF self-inductance model tance depends on the element's length and conguration
compared to the proximity of other elements, and will
By studying various plots of inductance versus frequency exist between each conductor in the package. However, it
for various radii and lengths, it was determined that the is important to note that this value approaches zero as the
curves could be well matched with a circuit with a zero at elements become perpendicular to one another. This prop-
the origin, followed by a second zero and a pole. The second erty eliminates mutual inductance of the Z-plane elements,
zero and the pole are typically within one decade of each vias and solder balls, with the XY-plane elements of the
other. The circuit, shown in Fig. 4, acts like an inductor that wires and traces. Additionally, since the value of the mutual
decreases uniformly over the decade in frequency. inductance rapidly decreases with increasing separation
 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709 705

Fig. 6. Sample trace geometry for computing mutual inductance.

another. No inductance will exist between the perpendicular

elements. For the parallel case, the elements are separated
from each other by distance that increases by an integer
multiplier. Therefore, mutual inductance need only be
calculated once for each possible value of separation,
saved in an array, and assigned to the elements as needed.
The equation for mutual inductance between parallel or near
parallel elements is
" v
!2!!
u
l u l
M 2l ln 1 t1 1
d d
v
!2 !#
u
u d d
2 t1 1 1 nH 10
l l

where d is the separation between conductors in cm.

2.6. Mutual inductance between traces

The traces in the package present a more interesting

Fig. 5. (a) Comparison of inductor model with theoretical inductance curve
problem, as they are mapped out in routes with a wide
(thick line) for gold conductor with circular cross-section and radius of range of angles to one another as shown in Fig. 1. The
12.7 mm. (0.5 mil). (b) Comparison of inductor model with theoretical CSBGA packages call for a robust formula capable of
inductance curve (thick line) for rectangular copper conductor with effec- computing mutual inductance between traces of any length
tive radius of 50.8 mm (2 mils). and arranged in any conguration. The mutual inductance
formula, Eq. (10) would not be able to handle all of the
between conductors, only signicant values are reported to possible congurations. An alternate routine [1,2] was
the SPICE sub-circuit. Mutual inductance is reported to the developed, employing Eq. (11), which was much more
output SPICE deck in the form of the coupling coefcient versatile. Starting with the beginning and ending points of
based on the two traces' value of self-inductance shown in the two traces that are displayed in Fig. 6, the routine calcu-
Eq. (9). lates four distances: r1 from ball1 to ball2, r2 from end2 to
p ball1, r3 from end1 to ball2, and r4 from end1 to end2. Next,
K M= L1 L2 9 using the two trace lengths and the four distances, the algo-
rithm calculates, e , the angle between the two traces and the
The cylindrical elements in the package exist in arrays or two extensions, u and v, the distances to the point where the
rows of equal length, and lie parallel or perpendicular to one two traces would meet on a plane. Finally, with all of
706 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709

the above computations, the value of mutual inductance 3.2. RF resistance model
between the two traces can be formulated. This method
provides the mutual inductance between non-meeting In an effort to simplify the circuit models for high
elements lying anywhere on the same plane, at any angle frequency resistance [4], a circuit model ladder was exam-
to each other. The mutual inductance is given as [8]: ined for both two inductors and three resistors (2nd order
model) and for one inductor and two resistors (1st order
M 2 cose model). The resistance modeled is at until the frequency
2 3 where the skin depth is less than the radius for circular cross
21 m 21 l
u 1 l tanh 1 v 1 m tanh section or until the frequency where the skin depth is less
6 r1 1 r2 r2 1 r4 7
6 7 than one half of the smallest dimension for a rectangular
6 7
4 21 m 21 l 5 cross section. After the at section, the resistance increases
2u tanh 2 v tanh
r3 1 r4 r2 1 r3 as the square root of frequency (slope of one half on log
11 plot). The impedance of an inductor also increases with
frequency but linearly. Employing a ladder network with
This equation will yield negative inductance for traces resistors and inductors (see Fig. 4) adds successive pole/
with current owing in opposite directions, and zero induc- zero corrections to generate an impedance with an average
tance for perpendicular traces. However, this method has its slope equal to one half. This allows for the determination of
limitations, since u and v (lengths to point where traces the poles and zeros of the ladder. The poles and zeros must
meet) will come out to be innite for traces that are parallel. fall between the frequency at which the curve starts to rise
An algorithm, parallel, detects and slightly skews the paral- and the maximum frequency of desired accuracy. The rst
lel traces, allowing accurate utilization of this formula. The zero is placed near the corner frequency, which is where the
software nds the mutual inductance between each and resistance curve leaves the at portion of the curve, and the
every trace in the package, and reports these values to the last pole must be in the vicinity of the maximum frequency
SPICE deck routine if within a user-denable limit. of desired accuracy. The other pole and zero are determined
in a way that generates an average slope equal to one half.
The corner frequency, fk is found from setting the skin
3. RF resistance
depth equal to the radius for round wires
3.1. Theoretical representation 1
fk Hz 15
pm0 sr 2
To verify the accuracy of our model, a series of equations
are solved to obtain a theoretical representation of resistance or equal to one half of the length of the smallest cross
as a function of, d , the skin depth. A function of frequency, sectional dimension (usually the thickness for traces)
skin depth is given as 1
fk   2 Hz 16
1 t
d p 12 pm0 s
pf m0 s 2

By considering the conductor to consist of only the portion where m 0 is the permeability of free space, and t the thick-
covered by the skin depth, the increase in resistance can be ness of the trace.
calculated. Since resistance is inversely proportional to area, The other boundary frequency is given by the user of the
all other factors being equal, it will increase over frequency program as the maximum frequency of needed accuracy.
by the ratio of total area at DC to area based on skin depth, The location for the poles and zeros was determined by
d . Fig. 3 shows the skin depth for both circular and rectan- optimizing the spacing to produce the square root of f
gular conductors. Resistance will begin to increase with increase. In the rst trials, the poles and zeros were spaced
frequency approximately when the skin depth (Eq. (12)) evenly on a log plot throughout the range from corner to
decreases to equal the radius of the circular conductor or maximum frequency. The arrangement was simulated and
1/2 the shortest dimension in rectangular conductors. the spacing was modied until the percent error of the
For a circular conductor the resistance ratio can be shown ladder from the theoretical curve was minimized. A series
to be of constants, ci, was obtained from the simulations (see
Table 1) that could be applied to any wire or trace dimen-
Rv r2 sion. The resulting equations for placement was developed
for d , r 13
R DC d2r 2 d from the following expressions and the series of constants:
  ci
The following equation represents the resistance ratio for f
f P;Z fk max Hz 17
rectangular conductors with t thickness less than w width: fk
Rv tw The process of determining the constants was repeated for
for 2d , t 14
RDC 2dt 1 w 2 2d all of the poles and zeros for both the rst order (1 pole, 1
 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709 707
 
Table 1 R 3 1 sL2 R2
Table of constants used in calculating the values of the poles and zeros 1 sL1 R1
R3 1 sL2 1 R2
Zladder V 26
Pole/Zero cI (1st order) cI (2nd order) R3 1 sL2 R2
1 sL1 1 R1
R3 1 sL2 1 R2
Zero 1 0.255 0.167
Pole 1 0.707 0.378 Eq. (26) yields two poles and two zeros, where each is one
Zero 2 0.671 of the solutions of two quadratic equations (one for the
Pole 2 0.934
numerator, one for the denominator. In the second order
case, there are ve unknowns (R1, R2, R3, L1, L2) and there
zero) and the second order (2 poles, 2 zeros). Once the poles are ve equations. One equation for RDC, two for the poles as
and zeros were determined for the rst or second order solutions of the quadratic equation in the denominator of Eq.
sections from Eq. (17), the values of the inductors and resis- (26), and two equations for zeros as solutions of the quad-
tors could be found. From Fig. 4 the rst order DC resistance ratic equation in the numerator of Eq. (26).
and the ladder impedance can be found. They are given as For the second order case solving the ve simultaneous
0 1 equations yielded:
P1 P2
B 1 C R 1 RDC V 27
RDC B
@ 1
CV 18 Z1 Z2
1 A
1
R1 R2 P1 P 2 a
R 2 RDC V 28
Z1 Z2 c 2
R 2 1 sL1 R1
Zladder V 19 P1 P2 a
R2 1 sL1 1 R1 R 3 RDC V 29
b
Factoring the DC resistance out of Eq. (19) gives the rst
P1 P2
order pole, P1, and the zero, Z1, of the impedance as L 1 RDC H 30
Z1 Z2 c
R1 1 R2
P1 rad=s 20
L1 P1 P 2 a 2
L2 RDC H 31
Z1 Z2 bc
R2 where
Z1 rad=s 21
L1
a P1 1 P2 Z1 1 Z2 2 Z1 1 Z2 2 2 P1 P2
The geometry of the conductor gives the DC resistance and
the solution of Eq. (17) with the values in Table 1 will yeild 1 Z1 Z2 rad=s2
P1 and Z1. Solving the three simultaneous Eqs. (18), (20) and
(21) with the values of RDC, P1 and Z1 produce the equations b P1 2 Z1 P2 2 Z2 P2 2 Z1 Z2 2 P1 rad=s4
for R1, R2, and L1.
c P1 1 P2 2 Z1 2 Z2 rad=s
 
P
R1 RDC 1 V 22
Z1 3.3. RF resistance results

The circuit models were developed to match these theo-

R 1 Z1
R2 V 23 retical values over frequency for circular wire bonds and
P1 2 Z1 rectangular trace elements in the CSBGA package. In addi-
tion, the software contains an algorithm written to approx-
R2 imate accuracy based on the percent error up to a specied
L1 H 24 frequency between Eqs. (13) and (14) and the value of the
Z1
resistance ratio using the rst and second order circuit
The second order values of resistors and inductors can be equivalents. This algorithm allows the user to state a desired
found from the same procedure as the rst order. From Fig. accuracy and the program will select the necessary circuit
4 the DC resistance and the ladder impedance are given as: order, rst or second, to meet this specication.
0 1 Figs. 7 and 8 are comparisons of theoretical resistance
ratios with the models of resistance for gold wires and
B 1 C
B C copper conductors. Figs. 7a and 8a are 2 GHz plots for a
RDC B CV 25
@ 1 1 1 A 25.4 mm diameter gold wire and 25.4 mm by 127 mm copper
1 1
R1 R2 R3 conductor respectively. In Fig. 7a a 15% error is observed
708 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709
Fig. 7. (a) Comparison of rst order (dashed line) and second order (thick
solid line) with the theoretical resistance ratio curve (thin solid line) for a
gold conductor with circular cross-section, and radius 12.7 mm (0.5 mil.).
Models taken out to 2 GHz. (b) Comparison of rst order (dashed line) and
second order (thick solid line) with the theoretical resistance ratio curve
(thin solid line) for a gold conductor with circular cross-section, and radius
12.7 mm (0.5 mil.). Models taken out to 10 GHz.
for the rst order model and less than 5% for the second.
The plot of Fig. 8a (wider copper conductor) shows a
slightly larger error since the frequency where the skin
effects start (10 MHz compared to 50 MHz for the gold
wire) is lower resulting in a larger frequency range to
2 GHz. Figs. 7b and 8b are similar plots extended to
10 GHz. The rst order model in each of the gures
shows about a 20% error, while the second order model is
still less than 5%.
Fig. 8. (a) Comparison of rst order (dashed line) and second order (thick
solid line) with the theoretical resistance ratio curve (thin solid line) for a
copper conductor with rectangular cross-section, thickness 25.4 mm
(1 mil.) and width 127 mm (5 mils). Models taken out to 2 GHz. (b)
Comparison of rst order (dashed line) and second order (thick solid
line) with the theoretical resistance ratio curve (thin solid line) for a copper
conductor with rectangular cross-section, thickness 25.4 mm (1 mil.) and
width 127 mm (5 mils). Models taken out to 10 GHz.
4. Capacitance
4.1. Mutual capacitance
The program needed to solve for the mutual capacitance
between traces that are oriented in the various ways as
mentioned in the inductance routines above. Equations
 M.F. Caggiano et al. / Microelectronics Journal 31 (2000) 701709
that solved for the capacitance between parallel and equal
length traces [9] were enhanced [1,2] to t the non-ideal
cases. The method begins with a routine that projects the
traces onto a center reference line that bisects the traces
being evaluated. The angle between this line and the traces
can be found as well as the effective length and the effective
width of the traces. Traces that route around each other or
come in close contact are handled by this reference line
routine. The length appears in the linear portion of the equa-
tion for mutual capacitance and hence is the most important
parameter. The equation the program uses to nd the mutual
capacitance is given as [9]
2pe0 eeff l
C F 32
lnp2 d2 1=w1 1 t1=w2 1 t 1 1 program with versatility meeting the needs of current
where t is the package thickness, d the distance between traces,
w1 and w2 are the trace widths of the two mutual traces. e eff is
the effective dielectric of the package substrate material and
air and is a function of the dielectric thickness [1].
The distance, d, between traces on a standard BGA with
near parallel traces would simply be the average distance
between the balls of the traces and the pads of the traces.
The Chip Scale BGA's adjacent traces could travel in very
different directions. Therefore the method used to compute
d was the distance between the trace midpoints. A centerline
was then formed from the average separation of the two
traces. This centerline was used to compute the effective
length and effective width of each trace with its mutual
partner. The effective width, w1, is the width of the rst
trace divided by cos u , where u is the angle between this
trace and the centerline.
The effective length and effective width are related to
each other by the trace area. This area remains constant.
Therefore, the effective length became the area divided by
the effective width with the area being the original trace
length multiplied by the original trace width. The effective
lengths and widths were entered into Eq. (32) to obtain
capacitance.
4.2. Capacitance to ground
A small capacitance from each trace is calculated to the
die using Eq. (32) with the die paddle dimensions as one of
the conductors.
4.3. Capacitance results
To verify the above routine a 3-D solver was employed to
generate sample calculations of mutual capacitance for
different trace pair orientations. Each of the simulations
consisted of two traces which had the chip pad of each
trace xed at certain points while one of the traces was
rotated using the pad point as its pivot (see Fig. 6). The
trace was rotated so that the angle between the traces
would range from 0 to 3008. The program was exercised
for each situation that was simulated by the 3-D solver.
The two value sets were put into a le that was loaded
709
into matlab to produce a capacitance curve. The results
of the comparisons show agreement to within 20% and
are discussed in Refs. [1,2].
5. Conclusions
The main feature of the CSBGA Package Parasitic Model
Program is the rapid calculation and report of self and
mutual inductance and mutual capacitance for user dened
packages. The program accounts for many situations: fan-in
and fan-out traces, parallel traces, crossing traces, more than
one metal layer, and the effects of a die paddle. Algorithms
handling the different package congurations equip the
CSBGA layouts. For typical conductors found in CSBGA's,
the rst order skin effects model of resistance, containing
one pole and one zero (an additional resistor and inductor),
yielded a maximum percent error of 20%. The second order
case approximates the RF resistance with twice the number
of poles and zeros that the rst order case uses and yielded a
maximum error of 5%. Verication of the mutual induc-
tance and capacitance has been performed in previous
works [13].
These inductance and capacitance algorithms can also be
applied to other chip-scale packaging. Chip packages and
their effects can not be ignored, especially as applications
demand smaller, faster, and more accurate microchips for
their designs. As the packaging industry grows, programs
such as these will prove useful tools for engineers who must
design tomorrow's newest applications.
References
[1] M.F. Caggiano, R.M. Brush, J.T. Kleban, P.J. Chuaypradit, Electrical
modeling of the chip scale BGA, Proceedings IEEE 48th IEEE Elec-
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