IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.

3, MARCH 2011

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Reliability Analysis and Optimization of Power-Gated ICs

Aida Todri, Student Member, IEEE, and Malgorzata Marek-Sadowska, Fellow, IEEE
AbstractPower gating is an efcient technique for reducing the leakage power of electronic devices by disconnecting the power supply from blocks idle for long periods of time. Disconnecting gated blocks causes changes in the current densities of the grid branches and vias. For some gating congurations, dc current densities may increase in some grid locations to the extent that they violate electromigration (EM) constraints. In this paper, we analyze the EM and infrared (IR) voltage drop effects in gated global power grids. Based on our analyses, we develop a global grid sizing algorithm to satisfy the reliability constraints on grid branches and vias for all feasible gating congurations. Our experimental results indicate that a grid initially sized for all blocks connected to it may be modied to fulll EM and IR constraints for multiple gating schedules with only a small area increase. Index TermsElectromigration (EM), power gating, power grid optimization, power noise, vias.
Fig. 1. Power network with power gating.

I. INTRODUCTION

OWER distribution networks in high performance digital ICs are commonly structured as multilayer grids, as depicted in Fig. 1. The global power grid network is typically designed in the early stages of the design process, when little is known about the power demands at specic chip locations. Correcting or redesigning the power grid in the later stages in order to improve its electrical characteristics can be prohibitively expensive. On the other hand, over designing the power grid may lead to increased power consumption. With technology scaling, more transistors are packed on a chip and, at the same time, subthreshold and gate leakage currents are increasing. These major factors increase the criticality of power management and affect the grid design such that: 1) over designing the grid is not an option due to tight power budgets and 2) idle portions of the chip could be temporarily disconnected from the grid. Power gating is a technique that allows idle blocks to be disconnected from the power grid in order to reduce leakage current. Sleep transistors placed between the global and block level power grids enable the blocks to be turned on and off as process needed. Such an implementation requires a multiwith lowtransistors used by the circuits and highsleep transistors. Power gating saves power when idle blocks with
Manuscript received April 16, 2009; revised July 20, 2009. First published December 18, 2009; current version published February 24, 2011. This work was supported by SRC Grant 1421, a gift from Apache Design Automation, and an Intel Corporation equipment grant. A. Todri is with the Computing Division, Fermi National Accelerator Laboratory, Batavia, IL 60510 USA (e-mail: atodri@fnal.gov). M. Marek-Sadowska is with the Electrical and Computer Engineering Department, University of California, Santa Barbara, CA 93106 USA (e-mail: mms@ece.ucsb.edu). Digital Object Identier 10.1109/TVLSI.2009.2036267

substantial leakage currents are disconnected from the global grid for sufciently long periods of time. Disconnecting gated blocks causes large changes in currents owing through the global grids branches and vias. A power-gated device may have several power gating congurations (PGCs). For example, the chip shown in Fig. 1 has is gated and 2) both two gating congurations: 1) only block and are gated. blocks In this work, we focus on the power and signal integrity of the global power grid in dc conditions. We model circuit blocks as current sources and the global grid as a resistive network. Inductive effects are ignored because we are performing dc analysis. We only consider the working and/or sleep mode of gateable blocks rather than their transition modes. Thus, we ignore the power up/down currents when power gating is activated/deactivated. This is because our goal is to capture the static average current ows that last for considerable amounts of time and can lead to potential electromigration (EM) problems during the chips operational lifetime. We analyze currents owing in the global grid branches and vias and show that a global grid optimized for all blocks connected to it may be violating EM constraints for certain PGCs. This observation is counterintuitive, as turning off a block reduces the amount of current owing on the global grid; but, locally, current may be crowded in some branches or vias, which can lead to EM violations. As vias have cross-sections smaller than the grid branches, they can fail sooner than the grid branches [1], [2] due to EM caused by large current densities. The existing literature on grid sizing for dc conditions describes techniques to optimize the grid area under voltage drop [infrared (IR)] and EM constraints for one conguration of all circuit blocks connected to the grid [3][7]. These methods cannot be directly applied to optimize the power-gated grids

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because there is no easy way to determine a worst case conguration of those blocks connected to the grid that would subsume all power gating congurations. A different approach is presented in [8], where the authors model the block currents as random variables. Grid currents obtained from random sources can be thought of as current vectors from various PGCs, however, the optimization scheme presented in [8] is based on the assumption that current densities in all branches are equal. This condition is not fullled in our case. We performed experiments on an industrial power grid designed for a consumer electronics chip. The grid was designed in 90-nm technology, the chip area was 6.35 mm and it contained 260 K gates. The global power grid was constructed from metal 6 and 7 wires with uniform track widths. We applied various power gating congurations and measured the current densities on the power grid branches. We observed an increase of up to 40% in the current densities versus the allowed current density constraints. We rst show that a global grid satisfying the EM and IR constraints for all blocks connected to it may have EM violations for some PGCs. We perform both EM and IR analyses on the global power-gated grids in order to understand the nature of these EM violations. We derive conditions for and dependencies between the branch and via violations. Based on the distribution of the branch violations, we investigate various sizing techniques to optimize the grid area while satisfying the reliability constraints for all PGCs. We observe that when EM branch violations occur only on parallel tracks, greedy resizing works well. However, when EM violations occur simultaneously on neighboring horizontal and vertical tracks, greedy resizing of those tracks may lead to new violations elsewhere in the grid. This is because current ow changes direction after greedy resizing is applied on perpendicular violations. The unpredictable change in current direction and of its magnitude causes new violations on some branches. We apply a multigrid-based technique to reduce the original large-scale network to a much coarser one. The reduced network can be optimized very efciently due to its smaller dimensions. We perform grid optimization to eliminate branch and via violations with a minimal increase in the grid area. We start by investigating the occurrences of branch and via violations and determine those situations in which these violations are interrelated. We determine those constraints that the optimized grid must fulll and show that a power-gated grid can be sized such that it meets both EM and IR constraints. To control the grid area increase, we propose a combination of greedy resizing and an iterative, linear program (LP)-based grid track size correction technique. The proposed method produces a feasible grid that satises all the reliability constraints for all PGCs. The rest of this paper is organized as follows. In Section II, we describe the global power grid model used in this work. In Section III, we analyze the problem. The IR drop on gated power grids is discussed in Section IV. In Section V, we describe the multigrid method. In Section VI, we describe the method of computing EM violations. Our power-gating aware optimization techniques are presented in Section VII, followed by the results in Section VIII. Section IX concludes the paper.

Fig. 2. Via array. (a) 3-D. (b) 2-D representation. (c) Its model.

II. GLOBAL POWER GRID NETWORK In a multilayer grid, power tracks on each metallization layer span the entire die and are orthogonal to the tracks in adjacent layers. Via arrays at the track intersections connect the tracks in adjacent layers. Fig. 2 shows a geometrical representation and model of the vias. Vias are represented as resistances whose values depend on their dimensions. The global power grid network is designed to provide supply voltage to all its blocks within an allowed amount of IR drop and with current densities that satisfy the EM constraints on the grid branches and vias. In this paper, we focus only on the global power grid analysis (the top two layers of the power grid). The lower metal layers of the power grid are encapsulated in the block level model. For our dc analysis, we represent the global grid as a resistive network with resistances extracted from the wires and vias exact geometries. The grid topology is a mesh with uniform track widths. Gated and nongated blocks are represented as current sources that can be connected or disconnected from the power grid. We simplify the problem by omitting the resistances of the sleep transistors. We model the circuit blocks connected to the global grid as current sources with values equal to their average current consumption. When a block is operational, the current source modeling it is connected to the global grid. When power gating is applied, only a subset of the current sources are connected to the global grid. Different power gating congurations are applied by enabling/disabling blocks and their current consumption. It is important to note that, even with such a simplied grid model, EM constraint violation can be an acute reliability issue. III. EM ANALYSIS FOR POWER GATING In this section, we analyze the causes of EM violations in the global grids branches and vias. We utilize the superposition principle in computing the current ow when power gating is applied. A. EM Analysis on Global Grid Branches To understand the nature of EM violations, we start by investigating current ows in the branches. We will refer to those currents contributed by individual current sources and a xed conguration of voltage sources as base currents. For each conguration of gated (disconnected) current sources, a branch current can be determined as a superposition of the base currents from the active current sources. Superposition is applied as a property of linear networks [9]. We analyze the sample circuit shown in Fig. 3. Fig. 3(a) from source . shows the base branch currents , , and from Fig. 3(b) shows the branch base currents , , and

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Fig. 4. Via array geometry with a units of technology parameter .

The maximum density tained as

in the grid branches can be ob-

(3) from (2) is branch s maximum current density where is the number of branches. A branch is a violation and branch if , where is the maximum allowed current density constraint. In general, EM violations may occur only on those branches in which some base currents ow in opposite directions. In an ungated chip, those currents partially cancel each other, but for some gating congurations, the cancellation effect may vanish. B. EM Analysis on Global Grid Vias When power gating is applied, EM violations on both vias and grid branches are caused by the same mechanism. The excess current in grid branches has to ow through neighboring vias in order to reach the current sources. In Fig. 3(a), for example, there are vias between branches and . The currents owing through these vias before and after power gating , this is an indicator that these vias are and . Because might experience EM constraint violations when power gating is applied. The vias robustness is dependent on the via array size and the amount of current owing through it. Depending upon the current owing through the via and the two branches adjacent to it on the same metal layer, we identify two types of vias. In via type I, the current in one branch splits into the current owing into the via and into the other branch. In via type II, the branch currents merge and ow through the via. In Fig. 4, we show a typical via array structure where the dimensions are shown in units of a technology parameter [2]. For a via array of a size nxm, the track widths are exand . pressed in terms of as for a The current ow through a single via is for a type II via. Current densities type I and for vias are expressed as and for types I and II. In a track, the current densities are and for branches adjacent to a via, such as branches 1 and 2, shown in Fig. 2(c). Via density is expressed in terms of its neighboring branchs densities as (4)

Fig. 3. Sample circuit. (a) Base currents of source A. (b) Base currents of source B. (c) Branch currents before power gating. (d) Branch currents after power gating source A.

source . In Fig. 3(c), both sources and are connected to the grid and the branch currents are derived by the superposition of the base branch currents from the individual sources:

When source is gated, its base currents vanish. The new currents owing through the gated grid are shown in Fig. 3(d). , , and . Branch can have a potential EM violation, as the current owing when the circuit is power gated can be greater than the current in the ungated . This is so because in branch , base currents case; ow in opposite directions. Assuming that is the width and is the height of the wire segment , the new current density can be greater than the current density constraint . This analysis can be extended to more than two current sources and multiple gating congurations. be its base current from the curFor each branch , let is dened by the rent source . Each gating conguration of those active current sources that uniquely determine set branch ks base currents and their directions. The branch cur, for the gating conguration , can be computed rent . The as a summation of the active base currents , maximum current in a branch is (1) where is the number of gating congurations. Given that cur, the maximum rent density is expressed as current density in a branch is (2)

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TABLE I VIA RELIABILITY FOR (A) TYPE I AND (B) TYPE II VIAS WHEN THERE ARE CURRENT FLOW CHANGES ON THE GRID BRANCHES DUE TO POWER GATING

and amounts of currents owing through the branches and vias [8], [10], [11]. Corollary: The uniform scaling of via and branch resistances does not change the currents on a grid, so we can always upsize the tracks and vias to meet the EM and IR constraints [12]. Based on these theorems, we derive a scaling factor to uniformly upsize the entire grid without changing currents where (5) This factor guarantees that upsizing the grid by will always satisfy the EM constraints on all grid branches for all power gating congurations. It is important to note that upsizing the entire power grid by corrects the EM problems in grid branches, but it may result in a large area increase in the power grid and it may not remove all the via violations. We further investigate an optimization technique to resize the power grid without creating large grid area overhead and such that EM constraints are also satised by all via currents. V. MULTIGRID METHOD To perform grid optimization, we need to compute base currents and track width sensitivities for grids with millions of nodes. Applying modied nodal analysis (MNA) [9] to a large grid is quite expensive, and computing a matrix inversion could be a bottleneck, limiting the sizes of grids we can analyze. For this reason, we use a multigrid technique to reduce the grid granularity [13]. The multigrid technique provides very accurate simulation results for dc analysis [14], [15]. This technique consists of three steps: 1) reducing the original large grid into much a smaller grid; 2) solving the reduced grid; and 3) computing the solution for the original grid by applying a back-mapping process. The multigrid method performs grid reduction by skipping every other row (or column) track and doubling the widths of each remaining row (column) track. For each level of grid reduction, we perform row (column) track skipping and generate the relationships between the widths of the tracks in the original and in the reduced mesh. These relationships are expressed as linear combinations of the original track widths. The total grid area is unchanged. When removing a track between two tracks and , the incremental widths of and can be expressed as

for a type I via. Suppose that after power gating has been apto due to plied, the branch current density changes from current change. Let us assume that both branches 1 and 2 of Fig. 2(c) have no current density violations after power gating and . We check the via curis applied, rent density and its conditions for a possible EM violation. The via current density for a type I via can be expressed as . Given that both branches do not violate current density constraints, the via current density can be a violaif the condition tion, holds. Similarly, we derive all possible type I and II via violations based on the adjacent branch current densities after power gating has been applied. We state them in Table I. The possible scenarios are: 1) a violation occurs only on a via; 2) a violation occurs only on a branch; and 3) simultaneous violations are present both on a via and a branch adjacent to it. For type I vias, the . second condition listed on the table cannot occur as It is important to note that a via type is dened for a given power gating conguration. IV. IR DROP ON POWER-GATED GRIDS In this section, we discuss the role of IR drop in power-gated grids. The assumptions are that a power grid is resistive and operational blocks are modeled by current sources. The resistances are obtained from the track and via widths. Tracks are of uniform widths throughout their lengths. When power gating is applied, the grid node voltages may change. We have the following theorems. Theorem 1: The grid node voltages can only increase when a current source is turned off [8], [10], [11]. Theorem 2: In a resistive grid, the uniform scaling of the via and branch widths (resistances) does not change the directions

(6) In the original power grid, the widths for column tracks and are , , and . and are the distances from to and to . After removing track in the reduced power grid, and . To keep the the widths of tracks and become total area unchanged, the increment of the track widths should satisfy (6). Track folding is accomplished by interchangeably folding a track in vertical and horizontal directions. The reduced grid can be solved exactly using a direct solver. The solution of the reduced grid is mapped back to the original grid. Grid unfolding

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Fig. 5. Track widths and vias: (a) before and (b) after the track folding step.

is performed using the same coefcients as those used for grid folding. This allows the original grids granularity and properties to be kept. Vias must be considered during each of the multigrid transformation steps. The side length of a via is , as shown in Fig. 4. During the track folding step, all distance coefcients, , and track widths, , are expressed in terms of a via with a length of . This allows the vias to be partitioned to each track based on (6). Fig. 5 illustrates the track folding step, where three vertical tracks are folded into two tracks. Current sources are handled similarly. A current source connected to a node is split into two current sources connected to the neighboring nodes. The current values are assigned proportionally to the impedance of the branches or to the distances between the two nodes. The total value of the current sources remains unchanged. Current source splitting is also completed in two steps, rst in a vertical and then in a horizontal direction. We utilize similar expressions for grid unfolding, but in the reverse order. VI. COMPUTING EM VIOLATIONS In this section, we analyze the grid to identify those branches where EM violations can occur. This process requires three steps: 1) base current computation; 2) maximum branch current computation; and 3) identication of branch and via violations. A. Base Currents For each block that may be gated, we compute base currents using the appropriately reduced grid. We fold the tracks of the original grid around the block. The tracks covered by the block and their three immediate neighbors are left unfolded. The unfolded tracks allow us to maintain computational accuracy for current values in the branches around the block. From our experiments, we have found that leaving three immediate neighboring tracks unfolded maintains the current ow properties of the block while providing grid reduction. Leaving more tracks unfolded does not improve the accuracy and limits the granularity for grid reduction. We illustrate the grid folding for block A in Fig. 6. Having computed the base currents of the reduced grid, we map them back onto the original grid by unfolding the tracks. B. Maximum Branch Currents There may be many blocks supplied by the grid and, if any of them may be gated, we may have a huge number of possible gating congurations. It is impractical to enumerate the branch currents for very many gating congurations. For this reason we

Fig. 6. (a) Block A and its three neighboring tracks. (b) The reduced grid for computing the base current for block A.

consider two cases. The rst is when all PGCs are possible, and the second is when only a few PGCs are possible. Optimizing a grid in the rst case may lead to over design if only a few gating congurations exist. In the rst case, for each grid segment, we need to compute the sum of those base currents owing in positive and negative directions. For each branch, we maintain these two values, which are initially set to 0. As we compute the base currents of the original grid, we update these sums by adding the base current values to the appropriate partial sums. Thus, as we compute the base currents for each block, we also compute the sums of those currents owing in each direction for each branch. At the end of this process, some of these currents may be large enough to indicate a violation. In the second case, for each branch on the grid, we maintain the matrix of the base currents from each block. We compute branch currents for each PGC by applying the superposition of the appropriate base currents and, for each branch, we note the current with a maximum value. C. Identifying Violations We utilize the information gathered from the previous two steps to identify branch EM violations. From the computed worst case maximum branch currents, we obtain the current densities that identify branch violations and their magnitudes; we refer to their spatial conguration as a violation distribution map (VDM). Via violations are obtained similarly. The current owing through the branches must ow through the vias in order to reach the blocks current sources. As discussed in Section IV-B, via violations can occur in two ways: 1) a branch and its neighboring vias are violations (a violation on both via and branch) or 2) there is a only a via violation. These are obtained by analyzing the violation conditions for via types I and II, as shown in Table I. VII. POWER-GATING AWARE OPTIMIZATION Our goal is to optimize the original grid with a minimal area increase while satisfying the reliability constraints for all feasible PGCs. We utilize a violation distribution map as it captures branch violations from all power gating congurations. We initially optimize the grid to x all branch violations and, in the end, consider the remaining via violations. By doing so, we are

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Fig. 7. (a) Rened VDM. (b) Tracks to remain unfolded around a violation. (c) The reduced grid.

left only with possible via violations that satisfy the rst condition for type I or II vias, as shown in Table I. A track can have multiple, various magnitudes of violations on branches. We rene VDM by considering only the worst case branch violations that occur on each track. The rened map is referred to as rVDM. We optimize the grid to satisfy EM violations considering only the rVDM. We further reduce the complexity of the optimization problem by applying the multigrid reduction technique. Thus, our optimization scheme has three main steps: 1) reduce the grid size by folding tracks; 2) optimize the reduced grid; and 3) unfold the grid to its original granularity. A. Grid Folding Before folding, we identify a few neighboring tracks around a violation that will remain unfolded to maintain the conditions in which the violation exists. Unfolded tracks are chosen based on the violations locations. The smallest rectangular area covering the perpendicular violations and the rst and second immediately neighboring tracks around the violations create the region of effectiveness. The region of effectiveness ensures that the grid characteristics are maintained for the violations while grid folding is performed. We observed that including rst and second immediate tracks accurately captures the violation magnitude. Including more tracks does not increase the accuracy and it also limits the granularity for performing grid folding. Fig. 7(a) shows an example of the rened violation map. Fig. 7(b) shows the tracks that remain unfolded around one of the violations and Fig. 7(c) shows the reduced grid and the region of effectiveness around the violations. B. Reduced Grid Optimization The reduced grid is much coarser than the original grid and can be efciently optimized to satisfy the EM constraints for all PGCs. We present our grid sizing algorithm in the context of the reduced grid, but it can be used for the original grid as well. One way to x all EM branch violations is to upsize the reduced grid by , as discussed in Section III-B. However, could lead to an over-designed grid area. upsizing by

Instead, we apply a sequence of ne scale upsizing steps , where is the number of steps, to obtain a feasible grid that meets both EM and IR constraints for all power gating congurations. The ne scale upsizing steps are chosen empirically and applied to the whole grid. Additionally, after each upsizing step, we perform the downsizing of necessary tracks while not worsening the current density and voltage drop constraints on the power grid. Tracks to be downsized are chosen based on an optimization method. We propose a three-step iterative process of: 1) deriving current and voltage sensitivities for grid sizing; 2) uniformly up-sizing the grid by ne scale steps; and 3) shrinking the selected tracks. This process is repeated until there are no violations on the reduced grid. The proposed method is based on the ndings from theorems 1 and 2. Utilizing uniform up-sizing means there is no change in the current ow, which gives us the ability to control the current density. The gradual shrinking of selected tracks enables us to downsize the grid area while reducing the current density after each step in those branches that violate constraints. Repeating this method iteratively, we are able to minimize the total grid area while satisfying current density and voltage drop constraints. On the other hand, applying only the greedy upsizing steps changes the current ow in an unpredictable way, which makes it challenging to control the current and consequently leads to an overdesigned grid area. In the following sections, we discuss each steps of proposed method in detail. 1) Sensitivities: The base current sensitivity is dened as the amount by which the base current on a branch changes when a track is resized. We calculate the base current sensitivities for each branch in the reduced grids region of effectiveness. Branch current sensitivity is computed as a sum of the base current sensitivities for those current sources active in a given gating conguration. For each branch in the region of effectiveness, we compute its current sensitivity when each track is resized. These sensitivities are obtained for each power gating conguration in order to monitor their effects on current density. We also calculate voltage sensitivities for each node in the region of effectiveness of the reduced grid. Voltage sensitivity is the amount of change in the initial node voltage when a track is resized. We obtain voltage sensitivities for all the nodes on the reduced grid when each track is resized. Similar to current sensitivities, voltage sensitivities are obtained for each power gating conguration. Both current and voltage sensitivities have positive or negative values that correspond to increases or decreases in either current or voltage. By utilizing current sensitivities and by applying superposition, we can estimate the new current ow in a branch when several tracks are simultaneously resized. For superposition to give accurate results, we choose small track resizing coefcients , where is the number of simultaneously resized tracks. Similarly, we apply superposition to estimate the new node voltages when several tracks are resized. 2) Grid Upsizing: The ne upsizing steps are less than , which is derived from (5), and are chosen empirare between 1% to 5% ically. The ne upsizing coefcients

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of . We compute the new maximum EM violation sizing the grid as

after up-

(7) is the previous EM violation and is the upsizing where was derived from (3). step. The initial The ne upsizing steps are applied to the whole grid. 3) Grid Downsizing: After uniformly upsizing by , we shrink the total grid such that the new violations, if they occur, are not worse than . Downsizing the tracks constrains the grid area increase in the process of eliminating the EM violations. We select the tracks for resizing by solving a linear optimization problem. We minimize the total grid resizing by maximizing the tracks to be downsized as (8) are the track resizing coefcients subject to branch where current density, via current density, voltage drop, and resizing coefcient constraints. We note that grid downsizing is applied only to some tracks identied by . They are discussed in more detail in the following. 4) Branch Current Density: The branch current density constraint ensures that, after uniformly upsizing and shrinking the grid, branch current densities are not becoming worse than the . The new current for a existing branch current density branch can be expressed in terms of both the previous current and the current sensitivities after each track is resized by using the resizing coefcient as (9) of branch can be expressed as a function The new width , and the of the upsizing coefcient , the previous width resizing coefcient as (10) Equation (10) states that the new wire widths are derived by upsizing the previous widths and subtracting the amounts that these were resized (downsized). From the previous equations, we can derive the current density constraint for a branch as (11) Equation (11) states that the new current ows on a resized branch would not worsen the current density conditions. Thus, after each resizing step, the current density is decreased by until it satises the constraints. This equation serves as a basis of convergence for our optimization method. We rearrange (11) and write it as

Equation (12) is derived for all branches on the grid, for each power gating conguration. As pointed out in Section VI-B, we monitor the maximum current on all branches over all possible power gating congurations. Utilizing (12), we derive the new current densities after each resizing step to account for all power gating congurations. The optimization method converges to a solution that satises all possible PGCs. 5) Via Current Density: The via current density constraint ensures that, after uniformly upsizing and shrinking the grid, via current densities are not becoming worse than the existing . The new current for a via via current density can be expressed in terms of both the previous current and current sensitivities after each track is resized using the resizing coefcient as (13) We derive the current density constraint for a via as (14) and are the modiwhere ed dimensions of the via array due to track width resizing. is the current via density and it ensures that, after resizing, via current densities are not becoming any worse. Given that we utilize small track resizing coefcients , we apply linear approximation on the expression and rearrange (14) as

(15) Equation (15) is derived for all vias on the grid for each PGC. 6) Voltage Drop: The voltage drop constraint ensures that, after resizing some tracks, the IR drop does not become worse than the allowed amount. The new node voltage is expressed and voltage sensitivities in terms of previous node voltages when a track is resized (16) The new IR drop violation is expressed in terms of the new node voltage as (17) where is the coefcient that determines the allowed voltage drop on the grid. 7) Resizing Coefcients: We specify the range of track reof their original widths, as sizing coefcients to be within in (18). Some tracks can be upsized and some can be locally downsized, however, the global grid area is reduced (18)

(12)

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In our optimization problem, (10), (12), (15), (17), and (18) are utilized to select the tracks for grid resizing. 8) Sensitivities: For each upsizing step , after performing uniform grid upsizing and selective downsizing, we reanalyze the modied reduced grid to compute the new sensitivities. The algorithm iterates the sensitivity calculation-upsizing-downsizing steps until there are no more violations for all PGCs on the reduced grid. This algorithm is referred to as the three-step LP algorithm. 9) Analysis of Violations: We utilize the information about the distribution of violations and their peak magnitudes from rVDM to guide the resizing algorithm. A violation requires special resizing steps based on its location, the width of a track, and the widths of the neighboring tracks. To remove a violation on one track, several tracks may need to be resized. Which tracks these are and how much to resize them depends on the violations distributions on the grid. 10) Case I: Greedy Resizing: Greedy resizing is applied by simply upsizing the violation track by the magnitude of the violation [19]. For certain distributions of violations, resizing the tracks where violations occur solves the problem. For violations located in parallel tracks, applying greedy resizing could be effective. Greedy resizing is safe as long as no new violations are created on perpendicular neighboring tracks. To measure the safety of performing greedy resizing, we introduce the following. Denition 1: The size margin of a track is , where is the maximum current density on the track branches. Denition 2: The violation of a track is measured as . Denition 3: The capacity of a track is . is used as a size quality metric to determine whether and how much more current ow a track can accommodate . No new violations are created after rewithout violating sizing a track if the tracks perpendicular to it satisfy the following rule. 11) Rule 1: Greedy resizing of a track is applied only if the can accommodate perpendicular tracks minimum capacity the amount of violation reduced on by its resizing. This . can be stated as Rule 1 ensures that, after resizing to x a violation, the amount of current change on the perpendicular neighboring tracks does not create new violations. The branches affected most by resizing are the resized tracks neighbors. This is because currents from resized tracks have to satisfy Kirchoffs laws. In practice, it is sufcient to investigate only the rst and the second perpendicular track segments in the neighborhood of the resized track. These segments are referred to as rst and second immediate neighboring branches. This further renes Rule 1 as follows. 12) Rule 2: Greedy resizing is applied only if the minimum capacity of the 1st and 2nd immediate perpendicular neighboring branches can accommodate the amount of violation removed by resizing. as The resizing coefcient is determined by the violation . As a result, greedy resizing can be applied safely to parallel violations as long as Rule 2 is satised.

Fig. 8. Circuit sample for three-step LP currents (a) before and (b) after resizing.

13) Case IIThree-Step LP Resizing: Violations may also be located on both horizontal and vertical tracks. Fig. 8(a) shows a simple circuit with violations on perpendicular tracks T2 and T4. We apply greedy resizing to these tracks with the up-sizing coefcient set to 50% and observe the current ow change on other branches. Fig. 8(a) and (b) show current ows before and after resizing. We notice that the currents of the resized tracks increase, but their densities decrease. In the meantime, the currents on track T1 and their densities also decrease. However, track T3 experiences both a current increase and a change of direction in the current ow. This could create a new violation. The change in current direction makes greedy resizing ineffective for violations on perpendicular tracks. For such situations, we apply our three-step LP algorithm. The algorithm is applied on both horizontal and vertical tracks in the regions of effectiveness. The following rule is used for perpendicular violations. 14) Rule 3: Apply three-step LP resizing to the region of effectiveness and the neighboring perpendicular tracks of boundary violations. The resizing steps and coefcients for the three-Step LP are chosen as discussed in Section VII-B3 The rened violation distribution map is analyzed to identify case 1 or 2 type violations. This is accomplished by scanning the whole grid with a 3-by-3 sliding window. Only those violations that are covered by the same window are considered jointly. If a violation appears in two windows, then those windows are combined. Based on the violation patterns, we decide which resizing algorithm to apply. For those multiple violations on parallel tracks that are close to each other, we apply greedy resizing to the worst case violation, which often removes several parallel violations, as long as Rule 2 is satised. For multiple violations on perpendicular tracks, we apply our three-step LP algorithm on a combined region, which satises Rule 3. Based on this analysis, we developed an algorithm, , which applies either the greedy or three-step LP algorithm depending on the violation distribution. Fig. 9 algorithm. summarizes our C. Grid Unfolding Once the folded grid has been optimized, we unfold it into the original grids granularity and current source placement. Unfolding is completed in the same manner as folding by using the same coefcients in (6) where are the original distances between the tracks. Current sources remain unchanged.

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Fig. 10. Overall

MG + 3STLP optimization ow.

Fig. 9. Overall ow for

G + 3STLP algorithm.

After the optimization process, some of the reduced grids tracks experience an increase in their widths. When unfolding to the original granularity, the increase in width is distributed between all the unfolded tracks. Because we only consider the worst case violations on a track, there could be scenarios in which, after optimization and unfolding, the grid would exhibit minor violations. From our experimental results we have found that the branch violations are on the order of 1% of the current density value. These miniscule violations can be removed by applying greedy upsizing. Our overall ow for power-gating-aware optimization includes grid analysis for EM violations and grid optimization using our three-step LP algorithm. EM violations removal and grid optimization are performed on a reduced grid that is obtained by applying the multigrid method. Thus, our overall ow is a combination of the multigrid method and three-step LP algorithm, referred to as an algorithm, and it is summarized in Fig. 10. D. Via Consideration The optimization method described in the previous section produces a grid with no EM branch violations. According to the discussion in Section III-B, it is possible that such a grid may still suffer from via violations. This is due to the minor violations observed in branches that can propagate into vias based on those conditions discussed in Table I. From experimental results we have found that via violations are even less than 1% of the current density value. Based on our experience, these violations are less severe in the branch-optimized grid and can be easily removed by greedy upsizing those tracks with via violations. VIII. RESULTS We have implemented the grid resizing algorithm and tested it on several circuits. The circuit parameter values, sheet resis-

, and minimum wire tivity , wire width , current density pitches were taken from [16]. We considered power delivery in 1.0 V. The voltage drop con90-nm technology with and the sizing coefcients straints were set to 10% of the were bounded by 5% of the original track width. In our experiments, we tested various algorithms such as the uniform upsizing by , greedy resizing, three-step LP, , and . There are no prior works that developed tools for power grid optimization for various power gating congurations, which is why we utilize the greedy re, and algosizing, three-step LP, rithms for comparison. We conducted experiments on power grids that were initially optimized for a minimum area, while satisfying EM and IR constraints for all current sources present. In all our experiments, we used three types of current density blocks: high, medium, and low. Their values were kept constant for all experiments. For each block placement and grid setup, we applied three power gating congurations, which are referred to as some PGCs, and we also performed experiments when all PGCs were possible. We studied the effects of power gating for different distributions of current sources and grid congurations. 1) Impact of Block Placement and Track Width Distribution: We used two block placements and two grid congurations. and have the same types of grids with Benchmarks narrow tracks in their centers. has high density blocks has low density blocks placed placed in the center, whereas in the center of the grid, as illustrated in Fig. 11(a) and (b). and have the same types of grids with Benchmarks wide tracks in their centers. has high density blocks in the has low density blocks in the center center of the grid, and of the grid, as shown in Fig. 11(c) and (d). 2) Impact of Grid Granularity: Several 20 20, 30 30, 50 50, and 100 100 grids were tested for the same block placements to study the effects of grid granularity in gated ICs. 3) Impact of Initial Optimized Grid: We tested examples and , both of which have the same placements of

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TABLE II AREA SAVINGS AND RUN TIMES APPLYING THE GREEDY, THREE-STEPLP,

G + 3STLP, AND MG + 3STLP ALGORITHMS

Fig. 11. Various grid congurations.

current sources and the same grid areas; however, they have has wider different track width distributions. Benchmark tracks in the regions with high current density blocks, whereas has more evenly distributed widths throughout the grid. We studied the effect that the initial grid setup has on the amount of area increase. 4) Impact of Via Resistivity: We tested grids with vias manufactured from various materials. Vias introduce constraints to our grid optimization method. We studied the effect that

via structures with different resistivities, such as aluminium, copper, and tungsten [17], [18] have on the grid area savings. The results of applying the various algorithms are shown in Table II. Circuit names and their initial grid sizes are given in the rst and second columns. In columns 3 and 4 are the original grid area and the uniformly resized grid area. The term uniform refers to upsizing the area by the factor . Uniform upsizing is considered the standard increase in an area that is required to fulll all constraints for all gating congurations. The difference in area between uniform upsizing and the original area is the standard amount of additional area required to build a feasible grid. Columns 59 show the percentages of area savings for each algorithm with respect to uniform resizing. Run times are shown in columns 1013. We observe that the greedy algorithm has negative percentages in area savings, meaning that it has a greater area increase than that achieved by uniform upsizing. This is due to greedy resizing, which changes the current ow in an unpredictable way. It is challenging to control and can also introduce new violations, which can lead to needing many iterative steps and a larger grid area to x all violations. Also, we note that and have less area savings than benchmarks and . Benchmarks and are those grids that have high current density blocks located in the center region; thus, when gated, they cause more current ow imbalance. The

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TABLE III AREA SAVINGS AND RUN TIMES USING DIFFERENT VIA RESISTIVITY MATERIALS

Fig. 12. Graphical comparison of algorithms.

number and magnitudes of these violations are greater than those in and . To x the EM violations, a greater area and . Also, as the grid granincrease is required for ularity changes, less grid upsizing is needed to eliminate EM violations. Finer grids have more freedom for locally resizing tracks and for controlling the overall grid area, especially when the multigrid method is applied. For some grids and gating congurations, our algorithm achieves huge savingsup to 47% in area savings compared and to uniform upsizing. We note that benchmarks have grids with the same area, but they also have different track width distributions that lead to different area increases. This suggests that the wire width distribution of the initial grid affects the quality of the nal result. We also note that considering all PGCs versus some PGCs requires greater area increases as more violations are being considered. Considering all PGCs subsumes some PGCs and is a safe approach if a huge number of gating congurations are possible. Comparisons between algorithms are also shown in Fig. 12. Applying the multigrid technique in our optimization ow not only reduces the complexity of the problem, but it also leads to greater area savings. Before grid folding, each track has its capacity metric that determines the creation of new violations after resizing, however, grid folding introduces a new capacity metric for a folded track, which is the accumulation of capacities of the

original tracks. Thus, the new capacities are more relaxed than the original ones. This reduces the likelihood that new violations will be created and overall less area increase is required. Addialgorithm does not perform greedy tionally, the algorithm, which is also anresizing as does the other factor contributing to the greater area savings. Folding and unfolding the grid serves as track width redistribution for efcient grid resizing. methods are We note that greedy, 3STLP, and not able to perform optimization on power grid granularities of 50 50 and 100 100 due to the large number of circuit nodes and the system complexity. We also observed that ap, plying ne upsizing stepssuch as in the 3STLP, algorithmsis benecial in obtaining a minand imum area increase with respect to uniform resizing. There is only a marginal runtime increase, as shown in Table II, columns 1013. In Table III, we show the percentage in area savings when various via resistivity materials are used. Copper has the lowest resistivity and tungsten has the highest. From the previous experiments in [12], we notice that the percentages in area savings are not as great when vias are considered. Additionally, an increase in via resistivity imposes more limitations on the area savings. IX. CONCLUSION In this paper, we demonstrate that disconnecting gated blocks from a power grid causes signicant changes in grid current ow. A grid that satises the reliability constraints when the whole circuit is powered may violate branch and via EM constraints when a portion of the circuit is shut off. Correcting this problem by the greedy resizing of EM violating tracks is not a viable option because new EM violations are introduced elsewhere. We perform analyses of the grid currents and study the effects of grid sizing on IR drop and EM. Our grid sizing method starts by optimizing grid tracks for EM branch and via violation. The grid-sizing theorems constitute the foundations of the

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three-step iterative grid-sizing algorithm. We also observe that vias introduce additional constraints on power grid optimization. Experimental results suggest that our algorithm is very efcient and achieves much better results than those obtained by simple uniform grid upsizing. REFERENCES [1] N. Raghavan and C. M. Tan, Statistical modeling of via redundancy effects on interconnect reliability, in Proc. Int. Symp. Phys. Failure Anal. ICs, 2008, pp. 15. [2] J. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996. [3] S. Chowdhury, Optimum design of reliable IC power networks having general graph topologies, in Proc. IEEE/ACM Des. Autom. Conf., 1989, pp. 787790. [4] X. D. Tan, C. J. R Shi, D. Lungeanu, J. C. Lee, and L. P. Yuan, Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings, in Proc. IEEE/ACM Des. Autom. Conf., Jun. 1999, pp. 7883. [5] X. D. Tan and C. J. R. Shi, Fast power/ground network optimization based on equivalent circuit modeling, in Proc. Des. Autom. Conf., 2001, pp. 550554. [6] T.-Y Wang and C. C.-P Chen, Optimization of the power/ground network wire-sizing and spacing based on sequential network simplex algorithm, in Proc. Int. Symp. Quality Electron. Des., 2002, pp. 157162. [7] H. Su, K. Gala, and S. Sapatnekar, Fast analysis and optimization of power/ground networks, in Proc. Int. Conf. Comput.-Aided Des., 2000, pp. 477482. [8] S. Boyd, L. Vandenberghe, A. E. Gamal, and S. Yun, Design of robust global power and ground networks, in Proc. Int. Symp. Phys. Des., 2001, pp. 6065. [9] R. L. Boylestad, Introduction to Circuit Analysis. Englewood Cliffs, NJ: Prentice-Hall, 2000. [10] S. Chowdhury and M. A. Breuer, Optimum design of IC power/ground nets subject to reliability constraints, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 7 , no. 7 , pp. 787796, Jul. 1988. [11] S. Chowdhury and M. A. Breuer, Minimal area design of power/ground nets having graph topologies, IEEE Trans. Circuits Syst., vol. CAS-34, no. 12, pp. 14411451, Dec. 1987. [12] A. Todri, M. Marek-Sadowska, and S. C. Chang, Analysis and optimization of power-gated ICs with multiple power gating congurations, in Proc. Int. Conf. Comput.-Aided Des., 2007, pp. 783790. [13] P. Wesseling, An Introduction to Multigrid Methods. Flourtown, PA: R. T. Edwards, 2004.

[14] J. Kozhaya, S. R. Nassif, and F. N. Najm, A multigrid like technique for power grid analysis, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 10, pp. 11481160, Oct. 2002. [15] K. Wang and M. Marek-Sadowska, On-chip power supply network optimization using multigrid-based technique, in Proc. ACM Des. Autom. Conf., 2003, pp. 113118. [16] J. Cong, An interconnect-centric design ow for nanometer technologies, Proc. IEEE, vol. 89, no. 4, pp. 505528, Apr. 2001. [17] J. Tao, K. K. Young, N. W. Cheung, and C. Hu, Electromigration reliability of tungsten and aluminum vias and improvements under AC current stress, IEEE Trans. Electron Devices, vol. 40, no. 8 , pp. 13981405, Aug. 1993. [18] ITRS, International technology roadmap for semiconductors, 2007. [Online]. Available: http://www.itrs.net/reports [19] T. H. Cormen, E. Charles, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. Cambridge, MA: MIT Press and McGraw-Hill, 2001. [20] H. Jiang, M. Marek-Sadowska, and S. Nassif, Benets and costs of power-gating technique, in Proc. Int. Conf. Comput. Des., 2005, pp. 559566. Aida Todri (S03) received the B.S. degree in electrical engineering from Bradley University, Peoria, IL, in 2001, the M.S. degree in electrical engineering from Long Beach State University, Long Beach, CA, in 2003, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 2009. She has been with the Computing Division, Fermi National Accelerator Laboratory, Batavia, IL, since 2009. Her research interests include low power design, clock and power network design, signal and power integrity analysis.

Malgorzata Marek-Sadowska (M87SM95F97) received the M.S. degree in applied mathematics and the Ph.D. degree in electrical engineering from Technical University of Warsaw, Warsaw, Poland. From 1976 to 1982, she was an Assistant Professor with the Institute of Electron Technology, Technical University of Warsaw. She was a Research Engineer with the University of California (UC) Berkeley Electronics Research Laboratory from 1982 to 1990. Since then, she has been with the Department of Electrical and Computer Engineering, UC Santa Barbara, as a Professor. Dr. Marek-Sadowska was an Associate Editor from 1991 to 1993, and from 1993 to 1995, she was Editor-In-Chief of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUIT AND SYSTEMS.