Proc.

XXVIII International Scientific Conference Electronics - ET2019, September 12 - 14, 2019, Sozopol, Bulgaria

Low Power Ramp Generator

with MOSFET and CNTFET Transistors
Mariya Spasova, Tihomir Brusev, George Angelov, Rossen Radonov and Marin Hristov
Department of Microelectronics, Faculty of Electronic Engineering and Technologies
Department of Technology and Management of Communication Systems, Faculty of Telecommunications
Technical University of Sofia, 8 Kliment Ohridski blvd., 1000 Sofia, Bulgaria
{m.spasova, brusev, angelov, rossen.radonov, mhristov}@ecad.tu-sofia.bg

Abstract – In this paper we compare low power ramp
generator schematics realized with conventional MOSFET
transistors and CNTFET transistors. The current consumption
and power losses of the both circuits are evaluated and
analyzed. The generator circuit is part of an overall buck dc-dc
converter system, which uses a PWM control technique. The
investigation is performed in Cadence Spectre circuit simulator
using the 0.35 μm CMOS technology design kit.
Keywords – CNTFET transistor; ramp generator; buck dc-
dc converter; power losses, efficiency, Cadence Spectre.
I. INTRODUCTION
Nowadays, plenty of battery-powered smart electronic
devices, especially in the context of Internet of Things (IoT)
systems, require efficient energy consumption techniques
[1], [2]. For the implementation of efficient energy
solutions, dc-dc converters are needed to efficiently convert
high voltages to low voltages (buck dc-dc converters) and
low voltages to high voltages (boost dc-dc converters).
In this paper we consider an integrated buck dc-dc
converter that uses a Pulse-Width Modulation technique. A
highly efficient integrated buck dc-dc converter has to
occupy small silicon area, in order to increase battery life
[3]. Pulse-Width Modulation (PWM) is a method of creating
modulated electronic pulses with a desired width. In
particular, it is used to control the states of the output power
switches. The circuit blocks of a PWM-controlled buck dc-
dc converter are shown in Fig. 1.
Fig. 1. Circuit blocks of PWM-controlled buck dc-dc converter.
The overall dc-dc converter system consists of bandgap
voltage reference, error amplifier, ramp generator, buffer,
and power stage. The power stage includes output p-MOS
and n-MOS transistors and a low-pass filter formed by filter
inductor and filter capacitor. An error signal is received,
978-1-7281-2574-9/19/$31.00 ©2019 IEEE
when the difference between the output voltage of the
system (Vout) and the output voltage level of bandgap
reference (Vbg) is amplified.
The frequency of the ramp generator defines the switching
frequency fs of the buck converter. For the PWM control
technique this frequency is constant. The control signal,
which regulates the power p-MOS and n-MOS transistors, is
generated by comparing the output voltage of the ramp
generator (Vramp) and the error control voltage. The output
signal of the comparator controls the states of the power
buck converter’s switches M1 and M2.
This buck dc-dc converter is part of a power management
integrated circuit (PMIC) for IoT electronic devices. The
PMIC block diagram is shown in Fig. 2 [4].
Fig. 2. Block diagram of power management integrated circuit
(PMIC) in IoT electronic device [4].
In Section II of this paper, we investigate the ramp
generator of Fig. 1. It is designed with conventional
MOSFET transistors in Cadence Spectre using the 0.35 μm
CMOS technology design kit of Austria Microsystems
(AMS). In Section III, a low power ramp generator designed
with CNTFET transistors (carbon nanotube transistors) is
described. The current consumption and power losses of
both circuits are then evaluated and compared.
II. RAMP GENERATOR CIRCUIT WITH MOSFET
TRANSISTORS
As mentioned above, first we design the ramp generator
with conventional MOSFET transistors in c35b4
technology – that is a 0.35 μm CMOS technology of AMS.
The simulated circuit block is shown in Fig. 3. The
schematic of the ramp generator is illustrated in Fig. 4.
Fig. 3. Simulated block circuit of ramp generator.
Fig. 4. Circuit schematic of the ramp generator designed in AMS
0.35 μm CMOS technology.
Two current mirrors form the output stage of the ramp
generator. They are composed of two p-MOS transistors
(M2 and M3) and two n-MOS transistors (M13 and M14)
respectively. Both current mirrors define the charging and
discharging currents of the ramp’s output capacitor C1. The
NMOS and PMOS transistors are implemented in Spectre by
using nmosnrf and pmosnrf elements from
PRIMLIBRF library.
The output signal frequency of the generator defines the
switching frequency fs of the buck dc-dc converter. The
simulated waveform of the output voltage Vramp of the
MOSFET ramp generator is presented in Fig. 5.
Fig. 5. The waveform of the output signal Vramp of the ramp
generator designed in AMS 0.35μm CMOS technology.
The power supply voltage VDD is equal to 1.5 V. The
output signal’s frequency of the designed ramp generator is
equal to 77 MHz. This frequency depends on i) the current,
which flows through ramp capacitor C1 and on ii) the
capacitor’s value. The current consumption of the generator
is equal to 216 μA, while the power losses are equal to
323 μW.
III. RAMP GENERATOR CIRCUIT WITH CNTFET
TRANSISTORS
Secondly, we realize the ramp generator of Fig. 1 in
Spectre simulator using CNTFET transistors. The circuit
schematic is given in Fig. 6. The CNTFET circuit model
used is based on the Stanford CNTFET model [5]. It is
implemented in Spectre as an external Verilog-A code that
we have used for the n- and p-CNTFETs in our previous
papers [6], [7]. Carbon nanotube (CNT) transistors may
feature one or more CNTs and can meet the requirements for
a decreased layout area as they are accurately modeled down
to 20 nm [5]. However, we would like to emphasize that in
this paper, the investigation is based on circuit level analysis
only as we do not have any layout representations of
CNTFETs in our design kits.
Fig. 6. The schematic of ramp generator investigated with CNFET
transistors.
In our analysis with the CNTFET circuit, we have set
model parameters’ values that correspond to the parameters
used for the conventional MOS transistors accounting for the
scaling coefficient – conventional MOSFETs feature
channel lengths of 350 nanometers while CNTFETs feature
channel lengths that are 10 times shorter. It should also be
noted that CNTFETs have parameters – such as number of
CNTs, chirality of the tubes, etc. – that do not have matching
counterparts in MOSFETs.
After analyzing multiple simulations with parameters that
meet the above consideration for scaling, it occurred that the
CNTFET ramp generator circuit require a very careful
parameter setup in order to ensure the obtaining of
simulations results; otherwise the simulator would return
“divide-by-zero” errors. Successful simulation results are
produced by setting parameter values that are equal to the
default model values – physical channel length (Lch) =
32 nm, thickness of high-k top gate dielectric material
(planar gate) = 4 nm, chirality of tube (n1, n2) = (19, 0),
number of tubes in the device = 1.
The simulated triangular waveform of the output voltage
Vramp of the CNTFET ramp generator is plotted in Fig. 7.
The power supply voltage VDD is equal to 0.8 V. The
frequency of the output signal is equal to 77 MHz. The
current consumption of the generator when CNFET
transistor’s models are used is equal to 20.9 μA. The power
losses in the circuit are equal to 16.7 μW.
 transistors. Current consumption and power losses of both
circuits are calculated and compared. The results obtained
prove that power losses in the CNTFET ramp generator are
significantly smaller than the MOSFET circuit designed
with conventional transistors from the 0.35 μm CMOS
technology design kit of AMS. Hence, the efficiency of a
buck dc-dc converter could be increased if it is designed with
CNTFETs. In turn, an improved battery life of electronic
devices incorporated in the power management integrated
circuit will be realized.

Fig. 7. The waveform of the output signal Vramp of the ramp

generator with CNTFET transistors. ACKNOWLEDGMENT
This work was supported by the European Regional
The results obtained are presented in Table 1. It can be
Development Fund within the Operational Programme
seen that power losses in the ramp generator with CNTFETs
“Science and Education for Smart Growth 2014 - 2020”
are around 19 times smaller compared to the circuit with
under the Project CoE “National center of mechatronics and
MOSFETs from the 0.35 μm CMOS technology AMS
clean technologies“ BG05M2OP001-1.001-0008", L10S7
design kit. The current consumption of the circuit with
SynChaLab.
CNTFETs is about 10 times smaller compared to the
consumption of the generator with MOSFET transistors.
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