IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO.
8, AUGUST 2020
Effects of Scaling on Analog FoMs of
UTBB FD-SOI MOS Transistors:
A Detailed Analysis
Mandar S. Bhoir , Graduate Student Member, IEEE, and Nihar R. Mohapatra , Senior Member, IEEE
Abstract — In this article, the combined effect of BOX
thickness (TBOX ) and ground-plane (GP) doping (NGP ) on
channel carrier mobility and analog figures of merit (FoMs)
is investigated. It is reported that the thin BOX along with
higher NGP will limit the electron/hole mobility of ultrathin
body and BOX fully depleted silicon-on-insulator (UTBB
FD-SOI) MOS transistors. The physics responsible for this
observation is discussed in detail. The contrasting behavior
of different GPs, the effect of TBOX scaling, and gate-length
scaling on device behavior is also analyzed. It is also shown
that in advanced UTBB FD-SOI MOS transistors, a tradeoff
exists between transistor intrinsic gain, cutoff frequency,
and non-linearity. In nMOS transistors, the best intrinsic
gain and cut-off frequency can be achieved with ultrathin
BOX and n-type GP (or with no GP), whereas the best
linearity can be achieved with ultrathin BOX and p-type GP
implant.
Index Terms — Ground plane, mobility, non-linearity, tech-
nology scaling, transconductance, ultrathin body and BOX
fully depleted silicon-on-insulator (UTBB FD-SOI).
I. I NTRODUCTION
T HE 5G communication technology and Internet-of-
Things (IoT) applications require on-chip low-power
mixed-signal systems. The ultrathin body and BOX fully
depleted silicon-on-insulator (UTBB FD-SOI) MOS transistor,
a planar device architecture, has emerged as a promising
solution for these applications because of its better dc, analog,
and RF figures of merit (FoMs) [1], [2]. With thinner body
and BOX thicknesses (TSi and TBOX ), the UTBB FD-SOI
MOS transistors provide better gate electrostatic control
[i.e., reduced short-channel effects (SCEs)] and lower device
parasitics. The high doped ground plane (GP) underneath the
BOX improves the gate electrostatics, provides cost-effective
multithreshold transistor options, and helps in effective real-
ization of back-gate biasing schemes [3]. However, with
Manuscript received May 26, 2020; revised June 11, 2020; accepted
June 13, 2020. Date of publication June 24, 2020; date of current version
July 23, 2020. This work was supported in part by the Visvesvaraya
Ph.D. Scheme, MeitY, Government of India, and in part by the Horizon
2020 ASCENT EU Project (Access to European Nanoelectronics Net-
work) under Project 654384. The review of this article was arranged by
Editor G. Ghione. (Corresponding author: Mandar S. Bhoir.)
The authors are with the Department of Electrical Engineering,
IIT Gandhinagar, Gandhinagar 382355, India (e-mail: mandar.bhoir@
iitgn.ac.in; nihar@iitgn.ac.in).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2020.3002878
0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
3035
saturation of the TSi scaling, the future CMOS nodes fully
rely on the scaling of TBOX and optimization of GP doping.
From the last 50 years, technology scaling has been mostly
logic application driven. Although the electrostatics of such
UTBB FD-SOI devices were extensively studied and carefully
modeled [4], [5], there are limited reports on the effect
of device dimensions on carrier mobility [6]. In particular,
the effect of TBOX and GP doping (NGP ) on mobility is still
unexplored. Arshad et al. [7] had reported degradation of
transconductance (gm ) for devices with thin BOX and GP.
However, physics behind this observation was not discussed.
Note that the mobility is an important parameter for digital
and analog/RF circuits. Therefore, a detailed understanding of
mobility degradation with UTBB FD-SOI device scaling is
necessary for better device design.
Furthermore, the transistor intrinsic gain and non-linearity
are essential FoM of analog circuits. The communication
systems use different linearization techniques to suppress
the unwanted harmonics. However, these circuits are gener-
ally complex and expensive, thereby emphasizing the need
for linear transistors. Till date, a few references only have
reported the effect of scaling on the analog performance and
non-linearity of UTBB FD-SOI MOS transistors [7]–[12]. The
articles [9], [10] had compared the analog performance para-
meters for transistors with and without GP, but the study was
limited to a single technology node (constant TSi and TBOX )
and/or for devices with thicker gate dielectrics. The studies
[11], [12] had compared the linearity performance of UTBB
FD-SOI and bulk MOS transistors and the impact of back-gate
bias on non-linearity, but the impact of technology scaling
on linearity was missing. Our research group had recently
reported the effect of TBOX and GP doping on transistor’s non-
linearity [13]. However, the report was brief and was done
for transistor’s with thicker TSi . To summarize, there are no
systematic studies on the effect of TBOX scaling and GP doping
(NGP ) on the analog FoMs.
In this article, we have shown that the UTBB FD-SOI MOS
transistor scaling (ultrathin BOX and high NGP ) results in
degradation of electron/hole mobility and gm . For the first
time, the exact physics behind this behavior is discussed
in detail with the help of TCAD simulations and device
measurements. The contrasting behavior of n- and p-type GP,
the effect of TBOX scaling, and gate-length (L g ) scaling on
this mobility degradation is explored in detail. The impact of
3036 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 8, AUGUST 2020

TBOX scaling and NGP on analog FoMs, viz., gm , output con-

ductance (gds ), and intrinsic gain (gm /gds ), is also investigated.
The second- and third-order harmonic distortions are extracted
from the dc simulations to investigate the linearity behavior.
Finally, an optimized design space for better analog FoMs is
proposed.
This article is organized as follows. Section II describes
the device details and simulation setup. The mobility-limiting
factors are investigated in Section III. The impact of technol-
ogy scaling on the analog FoMs is discussed in Section IV
followed by conclusion in Section V.

II. D EVICE D ETAILS AND S IMULATION S ETUP

The UTBB FD-SOI MOS transistors used in this article
have effective oxide (top-gate) thickness (EOT) of ∼1 nm
and TSi of 6 nm. The measured devices have TBOX of 25 nm,
whereas the devices used for simulations have TBOX varying
from 100 down to 10 nm. The transistor’s measured/simulated
in this article have L g varying from 20 to 300 nm. However,
we have mainly focused on L g of 100 nm (∼4 × L g,min ) for
analysis of the analog FoMs. The undoped body and substrate Fig. 1. Experimental (symbols) versus simulated (solid lines) transfer
with a GP (of constant doping profile) underneath the BOX characteristics of UTBB FD-SOI nMOS transistor (schematically shown
is used. The study is carried out for both p- and n-type GP above) with Lg = 20 and 300 nm, plotted for different back-gate
bias. Sentuarus TCAD simulator is accurately calibrated by matching
(p-GP and n-GP) implants. simulations with the experimental data.
The Sentaurus TCAD tool suite [14] is accurately cali-
brated with the measurement data from a 20-nm CMOS node
(provided by CEA-LETI). The thickness-dependent mobility
model for thin layer (TL) [6] along with the inversion and
accumulation layer (IAL) unified mobility model is used to
precisely capture the mobility behavior in UTBB devices. The
models to account for quantum mechanical correction, high-
field mobility saturation, and generation–recombination are
also included. Fig. 1 shows the measured and simulated trans-
fer characteristics. As shown, the good agreement between the
measured and simulated data for different values of L g and
back-gate bias (Vbg−s ) confirms the accuracy and scalability
of models used in the TCAD tool. This well-calibrated deck is
then used for the detailed analysis of transistor performances.

III. A DDITIONAL M OBILITY D EGRADATION
A. Limiting Factors
The impact of TL and surface-roughness scattering (SRS)
on electron mobility of UTBB FD-SOI nMOS transistors is
checked by disabling the TL and SRS models. Fig. 2(a) shows
the simulated transfer characteristics with and without TL
and SRS models. A significant increase in Id (mobility) is
observed when these models are not used, thus emphasizing
the dominant role of TL and SRS in UTBB devices. For
thin-body devices with TSi < Tinv (Tinv is the inversion layer
thickness in bulk MOS transistors), the inversion charges
(electron) are confined to a smaller thickness. This confine-
ment increases the electron–phonon wave function overlap
(increased electron–phonon interactions) resulting in reduced
mobility at lower transverse electric fields [15]. In addition,
these devices experience significant SRS at higher transverse
electric field because of increased proximity of electrons to
the Si–SiO2 /HfO2 interface [16]. Both the effects are captured
Fig. 2. (a) Simulated transfer characteristics with (solid lines) and without
(dashed lines) TL and SRS mobility models for Vds of 50 mV and 0.8 V.
Variation of Id with respect to Vov for different values of NGP of (b) p-type
and (c) n-type. In UTBB MOS transistors, Id degrades for higher p-type
GP doping, while it is constant for n-type GP case.
well by the TL and SRS models as verified earlier through
excellent matching with the experimental data (see Fig. 1).
To analyze the impact of NGP , TBOX , L g , Vds on effective
electron mobility (μeff ), and Id , the simulations are performed
by varying one parameter at a time. The results are discussed
in detail below.
B. Effect of Different GPs on μeff
For nMOS transistor with TBOX of 10 nm, the simula-
tions are performed by varying NGP from 1015 (no GP) to
1019 cm−3 . The threshold voltage (Vth ) increases with increase
in NGP for p-type GP, while it decreases for n-type GP.
Fig. 2(b) and (c) shows Id as a function of overdrive voltage

Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
BHOIR AND MOHAPATRA: EFFECTS OF SCALING ON ANALOG FoMs OF UTBB FD-SOI MOS TRANSISTORS 3037

Fig. 3. (a) Illustration of source–channel barrier (φSC ) extracted near
the Si–SiO2 interface. (b) φSC as a function of NGP plotted at the top
gate and back interface. The barrier at body–BOX interface is higher for
p-type GP compared with n-type GP transistors.
Fig. 4. Transverse electric field (ETran ) within the Si body for different
GP transistors biased at different values of Vov . In p-type GP transistors,
the higher ETran at body–BOX interface causes electron confinement near
the top-gate interface.

(Vov = Vgs − Vth ) at Vds of 0.6 V for different GP transistors.

In comparison with no GP transistors, Id reduces with increase
in NGP for p-type, while it is constant (slightly increases) for
n-type GP transistors. This Id degradation for p-type GP can be
attributed to either the increase in source/drain series resistance
(RSD due to depletion in LDD [17]) or to the reduction in
electron mobility. To investigate the exact reason, the same
simulations are performed by disabling TL and SRS models
and the resultant transfer characteristics is shown in Fig. 2(b).
As shown, without these models, there is no change in Id with
NGP variations. This confirms that the TL- and SRS-dependent
mobility degradation (and not the RSD effect) is responsible
Fig. 5. Variation of electron concentration within the Si body extracted
for Id reduction with p-type GP doping. for different values of (a) p-type GP doping, (b) n-type GP doping,
To understand physics behind the contrasting behavior of and (c) Vbg−s . For higher p-type NGP as well as for negative Vbg−s ,
p- and n-type GPs, the source–channel barrier [φSC , as shown electrons are confined near the top-gate interface. Note that the profiles
are extracted along the vertical cut line near the source end for constant
in Fig. 3(a)] at top-gate interface and back (Body-BOX) Id of 150 μA/μm.
interface is extracted for different values of NGP . The data are
plotted in Fig. 3(b). In comparison with no GP transistors, φSC
the Si body [see Fig. 5(b)] and results in negligible variation
increases at back interface and reduces at top-gate interface
of μeff and Id in case of n-type GP transistors [see Fig. 2(c)].
with increase in p-type NGP . On the other hand, φSC is almost
To further augment our understanding, the UTBB FD-SOI
constant at both the interfaces for n-type GP transistors. Note
transistors are simulated and measured for different back-
that this behavior is observed for transistors biased at constant
gate biases (Vbg−s ). As shown in Fig. 5(c), similar electron
Vov or constant Id . To understand the extracted φSC data,
confinement occurs with more negative Vbg−s . Therefore,
the transverse electric field (E Tran ) within Si body (from top
as shown in Fig. 6, μeff reduces for negative Vbg−s (for a
to back interface) is extracted for transistors with different
particular Id ). This experimentally confirms the role of TL
GPs and plotted in Fig. 4. As shown, the p-type GP transistor
and SRS components on mobility degradation. For reader’s
has higher E Tran , whereas n-type/no GP transistor has lower
information, μeff is extracted using the Split-CV technique [18]
(weak) E Tran at the back interface for all Vov values. This is
from the current and capacitance measurements carried out on
because of different work functions of the substrate (φsub ).
long and wide-channel (300 nm × 60 μm) UTBB FD-SOI
This higher E Tran (Si body to substrate) in p-type GP depletes
nMOS transistors.
the silicon close to the back interface resulting in higher
φSC [see Fig. 3(b)]. This results in electron confinement at
the top interface [see Fig. 5(a)]. The higher confinement C. Effects of TBOX Scaling on μeff
and proximity of carriers to the interface increase TL- and To study the impact of TBOX scaling on μeff , simulations
SRS-dependent mobility degradation in p-type GP transistors, are performed with TBOX varying from 100 down to 10 nm for
thus resulting in lower μeff and Id [see Fig. 2(b)]. On the other devices with and without GP. Fig. 7 shows the transfer charac-
hand, the weaker E Tran at the back interface for n-type/no GP teristics at Vds of 0.6 V. As shown, Id reduces with decrease in
transistors results in lower φSC at back interface [see Fig. 3(b)]. TBOX and the reduction is higher for devices with p-type GP.
This facilitates (almost) uniform electron distribution within To investigate further, the electron concentration profiles inside

Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
3038
Fig. 6. Experimentally extracted μeff as a function of Id plotted for
different values of Vbg−s . Electron mobility degrades as Vbg−s is swept
from 0 to −2 V due to their confinement near the top-gate interface
[see Fig. 5(c)].
Fig. 7. Variation of Id -Vov as a function of TBOX for devices without GP,
with p-type GP and n-type GP doping. With TBOX scaling, Id reduces and
it is significant for devices with p-type GP implant.
the Si body is extracted and plotted in Fig. 8. With decrease
in TBOX , the electron concentration remains unperturbed for
the devices without GP and with n-type GP, while the devices
with p-type GP show considerable electron confinement (near
the top-gate interface). Note that E Tran at the back interface
increases with reduction in TBOX . This causes more depletion
at the back interface and more confinement of electrons at the
top interface. The confinement of electrons at the top interface
increases TL- and SRS-dependent mobility degradation and
this explains higher degradation in Id for the devices with
p-type GP compared to n-type or without GP (see Fig. 7).
To summarize, the advanced UTBB FD-SOI nMOS transis-
tors with ultrathin BOX and p-type GP experience additional
mobility degradation because of electron confinement near
the top-gate interface and subsequent TL- and SRS-induced
mobility degradation. Therefore, these devices exhibit lower
Id and gm (at the same bias) compared to the devices with
thick BOX and/or n-type (or no) GP.
D. Effects of Lg and Vds on μeff
We have also studied the effect of L g and Vds on the
mobility limiting factors. Fig. 9(a) shows the gm degradation
[gm,max = (gm,max NoGP -gm,max GP )/gm,max NoGP ] with p-type
GP as a function of L g for Vds of 50 mV and 0.8 V. As shown,
gm,max (i.e., TL- and SRS-induced mobility degradation)
Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 8, AUGUST 2020
Fig. 8. Variation of electron concentration within the Si body with TBOX
scaling for devices without GP, with p-type GP and n-type GP implant.
Higher electron confinement near the top-gate interface is observed in
the devices with thin BOX and p-type GP.
Fig. 9. gm,max degradation with p-GP doping (Δgm,max ) as a function of
Lg plotted for different values of (a) Vds and (b) S/D contact resistance
(Rcontact ). The TL- and SRS-induced mobility degradation get masked in
shorter Lg due to increased effect of velocity saturation and RSD .
reduces for transistors with shorter L g and higher Vds . This
is because the current in shorter transistors and higher Vds
is mainly limited by velocity saturation and RSD . Therefore,
the effect of p-type GP on mobility (current) is less in
shorter transistors and at higher Vds . This argument is further
verified from gm,max versus L g plot for different values
of RSD [see Fig. 9(b)].
E. Effects of Scaling on Hole Mobility in
pMOS Transistors
Fig. 10 shows gm,max as a function of GP doping (n- and
p-type GP) for a pMOS transistor with thin BOX. Similar to
nMOS transistors, the holes in pMOS transistors also undergo
TL- and SRS-dependent mobility degradation with thinner
BOX and higher n-type GP doping. Note that the effect of
p and n-type GP in pMOS transistors is exactly opposite
to that of nMOS transistors because of the opposite role of
p-/n-type GP in electron and hole confinement.
IV. A NALOG P ERFORMANCE C OMPARISON
To investigate the impact of TBOX and NGP on analog perfor-
mance, gm and gds are extracted from the transfer and output
characteristics, respectively. For this analysis, the nMOS tran-
sistors are biased in the saturation regime (Vds ≥ Vov ).
BHOIR AND MOHAPATRA: EFFECTS OF SCALING ON ANALOG FoMs OF UTBB FD-SOI MOS TRANSISTORS 3039

Fig. 12. Variation of gm with TBOX for the devices without GP, with
Fig. 10. gm,max degradation (Δgm,max ) as a function of NGP plotted for p-type GP and n-type GP doping. With TBOX scaling, gm reduces and
pMOS transistors with different GPs. Δgm,max increases with NGP for this reduction is significant for devices with p-type GP doping.
transistors with n-GP because of hole confinement.

Fig. 11. gm as a function of (a) Id (plotted for different values of NGP )
and (b) NGP (plotted for different values of Vds ). For higher (p-type) NGP ,
gm reduces and flatness of gm –Id curves improves because of higher
TL- and SRS-dependent mobility degradation.
Fig. 13. Variation of gds as a function of (a) NGP and (b) TBOX plotted
for different values of Id . With TBOX scaling, gds reduces and lowest gds
is observed for devices with thin BOX and n-type/no-GP doping.

A. gm
Fig. 11(a) shows gm as a function of Id for different GPs
at Vds = 0.6 V for a nMOS transistor with TBOX of 10 nm.
As shown, gm is lower for transistors with p-type GP doping
due to enhanced TL- and SRS-dependent mobility degradation,
while it is almost constant (slightly higher) for n-type GP
doping compared with no GP. At Id = 200 μA/μm, gm
degrades by ∼14% in case of p-type GP compared with
n-type GP. The gm reduction with increase in p-type NGP is
the same for different values of Vds , as shown in Fig. 11(b).
Fig. 12 shows gm as a function of TBOX for nMOS transistors
with and without GP. Comparatively higher gm reduction in
transistors with p-type GP is observed, which is consistent with Fig. 14. DIBL as a function of (a) NGP and (b) TBOX for 100-nm-long
transistors. DIBL reduces with TBOX scaling, and for ultrathin BOX devices
the higher Id degradation as discussed earlier (see Fig. 7). the substrate charge condition (at BOX-substrate interface) influences
Note that this gm reduction for transistors with thin BOX the DIBL behavior.
and p-type GP also results in cutoff frequency degradation,
thereby affecting the RF performance.
devices with ultrathin BOX and n-type/no GP implant. This
observation is the same for all the bias currents. Note that
B. gds in shorter transistors, gds is mainly due to drain-induced
Fig. 13(a) shows gds as a function of NGP for TBOX of 10 nm. barrier lowering (DIBL). Fig. 14 shows the DIBL of a 100-
Fig. 13(b) shows gds as a function of TBOX for transistors nm-long nMOS transistor as a function of NGP and TBOX .
with and without GP. As shown, lower gds is observed for In FD-SOI MOS transistors, the DIBL mainly depends on

Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
3040 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 8, AUGUST 2020

Fig. 16. (a) | gm2 | (i.e., | d 2 Id /dVg2 |) and (b) | gm3 | (i.e., | d3 Id /dV3g |) as a
Fig. 15. Intrinsic gain, gm /gds as a combined function of TBOX and
function of Id extracted for different values of NGP (p-type). gm2 and gm3
NGP for 100-nm-long nMOS transistor. The gain is highest for devices
reduce for higher NGP , especially in lower current regime.
with ultrathin BOX and n-type GP, while the devices with high p-type GP
doping will have optimized gain performance for TBOX ∼ 20 nm.

three factors: 1) drain-to-channel coupling through Si body

(proportional to TSi ); 2) drain-to-channel coupling through the
BOX (proportional to TBOX ); and 3) drain-to-channel cou-
pling through the substrate (depends on charge condition near
the BOX–substrate interface [19]). As shown in Fig. 14(b),
the DIBL reduces with TBOX scaling (100 to ∼20 nm) for
devices with and without GP due to the reduction in fac-
tor 2, but for TBOX < 20 nm (with increased proximity of
substrate to drain), factor 3 dominates [Fig. 14(a)], thereby
increasing DIBL for the ultrathin BOX and p-type GP case
(BOX–substrate interface in the depletion regime). However,
in devices without GP (or n-type GP), the substrate is in
inversion (or near flat band), i.e., lower impact of factor 3.
Hence, the DIBL reduces with TBOX scaling as expected.
To summarize, the gds variations in UTBB FD-SOI transistors
are mainly due to modulation of DIBL with TBOX and NGP .

C. gm /gds
Fig. 15 shows gm /gds as a function of TBOX and NGP . gm and
gds are extracted for Vds = 0.6 V and Id = 150 μA/μm.
The higher gm and lower gds for devices with ultrathin BOX
and no GP implant result in higher gm /gds . The devices with
intermediate p-type NGP (1017 cm−3 ) shows no considerable
improvement with TBOX scaling. The devices with highly
doped p-type GP (≥1018 cm−3 ) shows higher intrinsic gain
around TBOX ∼ 20 nm but exhibits a gm /gds reduction for
further TBOX scaling because of sharp gm and gds degradation
as discussed earlier. On the contrary, a slight improvement in
gm /gds is observed with n-type GP compared to no GP because
of small improvement in gm as well as gds .
D. Transistor’s Intrinsic Linearity
To study transistor’s non-linearity, the second- and
third-order derivatives of Id (gm2 and gm3 ) with respect to Vgs
are extracted and shown in Fig. 16. For a memory-less circuit
excited with a sinusoidal signal of amplitude Va , second- and
Fig. 17. Behavior of HD2 and HD3 with respect to Id for different values
of NGP (p-type). For higher NGP , lower HD2 and HD3, i.e., better linearity
is observed for low-current levels (shown in inset).
third-order harmonic distortions can be written as shown in
(1) and (2) [20]. Here, Va of 50 mV is used.
 
1  gm2 
HD2 = Va  (1)
4 gm 
 
1 2  gm3 
HD3 = V . (2)
24 a  g  m
Fig. 17 shows the extracted HD2 and HD3 as a function of
Id for different values of NGP (p-type). The HD2 and HD3 for
n-type GP are not shown as they are the same as no GP case.
At lower Id , HD2 and HD3 reduction (i.e., better linearity)
is achieved with increase in NGP (shown in the inset for
Id = 150 and 200 μA/μm). This improvement even with
degraded gm is because of improved flatness of gm –Id curves,
i.e., lower gm2 and gm3 , as shown in Fig. 16. In other words,
it is the increased impact of TL in low transverse electric field

Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
BHOIR AND MOHAPATRA: EFFECTS OF SCALING ON ANALOG FoMs OF UTBB FD-SOI MOS TRANSISTORS
Fig. 18. Variation of (a) HD2 and (b) HD3 as a function of TBOX extracted
at different current levels for devices with and without p-GP. At low current
levels, better linearity is achieved with thin BOX and p-GP implant.
regime, which linearizes the general nonlinear nature of Id –Vg
characteristics. At higher Id , HD2 increases for higher NGP
(p-type). This behavior is because of early fall in gm –Id curves
(i.e., higher | gm2 | for Id ≥ 230 μA/μm) due to the early onset
of SRS on top of TL in high electric-field regime (high Vgs ).
Similarly, the harmonic distortions with TBOX scaling are
shown in Fig. 18. Better linearity is achieved with reduction
in TBOX , especially at lower Id , and this is due to mobility
limiting factor as discussed in NGP case. Note that the linearity
improvement is higher for nMOS transistors with p-type GP
compared to without (or n-type) GP. This observation is
consistent with the different Id degradation for the two cases,
as shown in Fig. 7.
V. C ONCLUSION
The effect of TBOX , L g scaling, and GP doping on dc and
analog/RF performance of UTBB FD-SOI MOS transistors
was investigated in detail. It was observed that the electron
mobility degrades with a reduction in TBOX for transistors
with p-type GP. No mobility degradation was observed with
TBOX scaling for transistors with n-type GP or no GP. The
confinement of electrons at the top interface and subsequent
TL/SRS was shown to be responsible for this behavior. It was
also shown that a tradeoff exists between transistor intrinsic
gain, cutoff frequency, and non-linearity. For FD-SOI nMOS
transistors, the best intrinsic gain and cutoff frequency can
be achieved with ultrathin BOX and n-type GP (or no GP),
whereas the best linearity can be achieved with ultrathin BOX
and p-type GP.
Qualitatively, the UTBB FD-SOI nMOS transistors with
“TBOX ∼ 10 nm + n-GP” or “TBOX ∼ 20 nm + p-GP implant”
was shown to be few optimal design spaces from analog/RF
performance perspective.
ACKNOWLEDGMENT
The authors would like to thank Dr. Reimbold Gilles,
CEA-LETI, France, for the characterization-related support
and discussion in the framework of the ASCENT project.
Authorized licensed use limited to: Tsinghua University. Downloaded on December 03,2022 at 10:20:01 UTC from IEEE Xplore. Restrictions apply.
3041
R EFERENCES
[1] W. Schwarzenbach et al., “Advanced FD-SOI and beyond low tem-
perature SmartCut enables high density 3-D SoC applications,” IEEE
J. Electron Devices Soc., vol. 7, pp. 863–868, May 2019, doi:
10.1109/jeds.2019.2916460.
[2] R. Carter et al., “22nm FDSOI technology for emerging mobile, Internet-
of-Things, and RF applications,” in IEDM Tech. Dig., Dec. 2016,
pp. 2.2.1–2.2.4, doi: 10.1109/iedm.2016.7838029.
[3] J.-P. Noel et al., “Multi-VT UTBB FDSOI device architectures for low-
power CMOS circuit,” IEEE Trans. Electron Devices, vol. 58, no. 8,
pp. 2473–2482, Aug. 2011, doi: 10.1109/TED.2011.2155658.
[4] T. Poiroux et al., “Leti-UTSOI2.1: A compact model for UTBB-FDSOI
technologies—Part I: Interface potentials analytical model,” IEEE Trans.
Electron Devices, vol. 62, no. 9, pp. 2751–2759, Sep. 2015, doi:
10.1109/TED.2015.2458339.
[5] S. Khandelwal et al., “BSIM-IMG: A compact model for ultrathin-
body SOI MOSFETs with back-gate control,” IEEE Trans. Elec-
tron Devices, vol. 59, no. 8, pp. 2019–2026, Aug. 2012, doi:
10.1109/TED.2012.2198065.
[6] S. Reggiani, E. Gnani, A. Gnudi, M. Rudan, and G. Baccarani, “Low-
field electron mobility model for ultrathin-body SOI and double-gate
MOSFETs with extremely small silicon thicknesses,” IEEE Trans.
Electron Devices, vol. 54, no. 9, pp. 2204–2212, Sep. 2007, doi:
10.1109/ted.2007.902899.
[7] M. K. Md Arshad et al., “UTBB SOI MOSFETs analog figures of merit:
Effects of ground plane and asymmetric double-gate regime,” Solid-State
Electron., vol. 90, pp. 56–64, Dec. 2013, doi: 10.1016/j.sse.2013.02.051.
[8] V. T. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, and J. A. Martino,
“Influence of different UTBB SOI technologies on analog parame-
ters,” in Proc. 31st Symp. Microelectron. Technol. Devices (SBMicro),
Aug. 2016, pp. 1–4, doi: 10.1109/sbmicro.2016.7731356.
[9] V. T. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, and J. A. Martino,
“Ground plane influence on UTBB SOI nMOSFET analog parame-
ters,” in Proc. 30th Symp. Microelectron. Technol. Devices (SBMicro),
Aug. 2015, pp. 1–4, doi: 10.1109/sbmicro.2015.7298114.
[10] V. Kilchytska et al., “Ultra-thin body and thin-BOX SOI CMOS technol-
ogy analog figures of merit,” Solid-State Electron., vol. 70, pp. 50–58,
Apr. 2012, doi: 10.1016/j.sse.2011.11.020.
[11] V. Kilchytska et al., “Comparative study of non-linearities in 28 nm
node FDSOI and bulk MOSFETs,” in Proc. Joint Int. EUROSOI Work-
shop Int. Conf. Ultimate Integr. Silicon (EUROSOI-ULIS), Apr. 2017,
pp. 128–131, doi: 10.1109/ulis.2017.7962581.
[12] B. K. Esfeh et al., “Back-gate bias effect on UTBB-FDSOI non-
linearity performance,” in Proc. 47th Eur. Solid-State Device Res.
Conf. (ESSDERC), Sep. 2017, pp. 148–151, doi: 10.1109/essderc.2017.
8066613.
[13] M. S. Bhoir and N. R. Mohapatra, “Impact of BOX thickness and
ground-plane on non-linearity of UTBB FD-SOI MOS transistors,” in
Proc. Joint Int. EUROSOI Workshop Int. Conf. Ultimate Integr. Silicon
(EUROSOI-ULIS), Mar. 2018, pp. 1–4.
[14] Sentaurus TCAD User Manual Version F-2016.09, Synopsys Inc.,
Mountain View, CA, USA, 2016.
[15] K. Uchida, J. Koga, R. Ohba, T. Numata, and S. I. Takagi, “Experi-
mental evidences of quantum-mechanical effects on low-field mobility,
gate-channel capacitance, and threshold voltage of ultrathin body SOI
MOSFETs,” in IEDM Tech. Dig., Dec. 2001, pp. 29.4.1–29.4.4, doi:
10.1109/iedm.2001.979588.
[16] D. Lizzit, D. Esseni, P. Palestri, and L. Selmi, “Surface roughness
limited mobility modeling in ultra-thin SOI and quantum well III-
V MOSFETs,” in IEDM Tech. Dig., Dec. 2013, pp. 5.2.1–5.2.4, doi:
10.1109/iedm.2013.6724565.
[17] R. Yan et al., “LDD and back-gate engineering for fully depleted
planar SOI transistors with thin buried oxide,” IEEE Trans. Elec-
tron Devices, vol. 57, no. 6, pp. 1319–1326, Jun. 2010, doi:
10.1109/ted.2010.2046097.
[18] P. Kushwaha et al., “Predictive effective mobility model for
FDSOI transistors using technology parameters,” in Proc. IEEE Int.
Conf. Electron Devices Solid-State Circuits (EDSSC), Aug. 2016,
pp. 448–451, doi: 10.1109/edssc.2016.7785304.
[19] M. K. M. Arshad et al., “Extended MASTAR modeling of DIBL in UTB
and UTBB SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 59,
no. 1, pp. 247–251, Jan. 2012, doi: 10.1109/TED.2011.2172993.
[20] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated
Circuits, vol. 451. Cham, Switzerland: Springer, 2013.