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William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
 Control Control

Select Data in Select Sense

Cell Cell

(a) Write (b) Read

Figure 5.1 Memory Cell Operation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Memory Type Category Erasure Write Volatility
Mechanism
Random-access Read-write Electrically,
Electrically Volatile
memory (RAM) memory byte-level
Read-only Masks
memory (ROM) Read-only
Not possible
Programmable memory
ROM (PROM)
Erasable PROM UV light, chip-
(EPROM) level Nonvolatile
Electrically Electrically
Read-mostly Electrically,
Erasable PROM memory byte-level
(EEPROM)
Electrically,
Flash memory
block-level

Table 5.1
Semiconductor Memory Types

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

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Dynamic RAM (DRAM)

◼ RAM technology is divided into two technologies:

◼ Dynamic RAM (DRAM)
◼ Static RAM (SRAM)

◼ DRAM

◼ Made with cells that store data as charge on capacitors

◼ Presence or absence of charge in a capacitor is interpreted as

a binary 1 or 0

◼ Requires periodic charge refreshing to maintain data storage

◼ The term dynamic refers to tendency of the stored charge to

leak away, even with power continuously applied

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 dc voltage

Address line T3 T4

T5 C1 C2 T6
Transistor

Storage
capacitor
T1 T2

Bit line Ground

Ground
B

Bit line Address Bit line

B line B

(a) Dynamic RAM (DRAM) cell (b) Static RAM (SRAM) cell

Figure 5.2 Typical Memory Cell Structures

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

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Static RAM
(SRAM)
▪ Digital device that uses the same
logic elements used in the
processor

▪ Binary values are stored using

traditional flip-flop logic gate
configurations

▪ Will hold its data as long as power

is supplied to it

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.