Line Memory

Number Tag Block address

0 0
1 1
2 2 Block 0
3 (K words)

C–1
Block Length
(K Words)

(a) Cache

Block M – 1

2n – 1
Word
Length
(b) Main memory

Figure 4.4 Cache/Main-Memory Structure

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 Address

Address
buffer

System Bus
Control Control
Processor Cache

Data
buffer

Data

Figure 4.6 Typical Cache Organization

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 Cache Addresses Write Policy
Logical Write through
Physical Write back
Cache Size Line Size
Mapping Function Number of caches
Direct Single or two level
Associative Unified or split
Set Associative
Replacement Algorithm
Least recently used (LRU)
First in first out (FIFO)
Least frequently used (LFU)
Random

Table 4.2
Elements of Cache Design
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 Logical address Physical address
MMU

Processor Main
Cache memory

Data

(a) Logical Cache

Logical address Physical address

MMU

Processor Main
Cache memory

Data

(b) Physical Cache

Figure 4.7 Logical and Physical Caches

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Mapping Function
◼ Because there are fewer cache lines than main memory
blocks, an algorithm is needed for mapping main memory
blocks into cache lines

◼ Three techniques can be used:

Direct Associative Set Associative

• The simplest technique • Permits each main • A compromise that
• Maps each block of main memory block to be exhibits the strengths of
memory into only one loaded into any line of the both the direct and
possible cache line cache associative approaches
while reducing their
• The cache control logic disadvantages
interprets a memory
address simply as a Tag
and a Word field
• To determine whether a
block is in the cache, the
cache control logic must
simultaneously examine
every line’s Tag for a
match

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 b t b
B0 L0

m lines
Bm–1 Lm–1
First m blocks of
cache memory
main memory
(equal to size of cache) b = length of block in bits
t = length of tag in bits
(a) Direct mapping

t b
L0

one block of
main memory

Lm–1
cache memory
(b) Associative mapping

Figure 4.8 Mapping From Main Memory to Cache:

Direct and Associative

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 s+w

Cache Main Memory

Memory Address Tag Data WO
Tag Line Word W1 B0
L0 W2
s–r r w W3

s–r

s
W4j
w Li
W(4j+1) Bj
Compare w
W(4j+2)
W(4j+3)
(hit in cache)
1 if match
0 if no match

Lm–1
0 if match
1 if no match
(miss in cache)

Figure 4.9 Direct-Mapping Cache Organization

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 Main memory address (binary)
Tag
(hex) Tag Line + Word Data
00 000000000000000000000000 13579246
00 000000000000000000000100

00 000000001111111111111000
00 000000001111111111111100
Line
Tag Data Number
16 000101100000000000000000 77777777 00 13579246 0000
16 000101100000000000000100 11235813 16 11235813 0001

16 000101100011001110011100 FEDCBA98 16 FEDCBA98 0CE7

FF 11223344 3FFE
16 000101101111111111111100 12345678 16 12345678 3FFF

8 bits 32 bits
FF 111111110000000000000000 16-Kline cache
FF 111111110000000000000100

FF 111111111111111111111000 11223344
FF 111111111111111111111100 24682468
Note: Memory address values are
in binary representation;
32 bits other values are in hexadecimal
16-MByte main memory

Tag Line Word

Main memory address =

8 bits 14 bits 2 bits

Figure 4.10 Direct Mapping Example

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+
Direct Mapping Summary

◼ Address length = (s + w) bits

◼ Number of addressable units = 2s+w words or bytes

◼ Block size = line size = 2w words or bytes

◼ Number of blocks in main memory = 2s+ w/2w = 2s

◼ Number of lines in cache = m = 2r

◼ Size of tag = (s – r) bits

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 s+w

Cache Main Memory

Memory Address Tag Data W0
Tag Word W1
W2
B0
L0
s W3

w Lj
s
W4j
W(4j+1)
Compare w Bj
W(4j+2)
W(4j+3)
(hit in cache)
1 if match
0 if no match
s
Lm–1

0 if match
1 if no match
(miss in cache)

Figure 4.11 Fully Associative Cache Organization

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 Main memory address (binary)

Tag (hex) Tag Word Data

000000 000000000000000000000000 13579246
000001 000000000000000000000100

Line
Tag Data Number
3FFFFE 11223344 0000
058CE7 FEDCBA98 0001
058CE6 000101100011001110011000
058CE7 000101100011001110011100 FEDCBA98 FEDCBA98
058CE8 000101100011001110100000
3FFFFD 33333333 3FFD
000000 13579246 3FFE
3FFFFF 24682468 3FFF

22 bits 32 bits
16 Kline Cache

3FFFFD 111111111111111111110100 33333333

3FFFFE 111111111111111111111000 11223344
3FFFFF 111111111111111111111100 24682468 Note: Memory address values are
in binary representation;
32 bits other values are in hexadecimal

16 MByte Main Memory

Tag Word
Main Memory Address =

22 bits 2 bits

Figure 4.12 Associative Mapping Example

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+
Associative Mapping Summary

◼ Address length = (s + w) bits

◼ Number of addressable units = 2s+w words or bytes

◼ Block size = line size = 2w words or bytes

◼ Number of blocks in main memory = 2s+ w/2w = 2s

◼ Number of lines in cache = undetermined

◼ Size of tag = s bits

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