SRAM versus DRAM

SRAM
◼ Both volatile
◼ Power must be continuously supplied to the
memory to preserve the bit values

◼ Dynamic cell
◼ Simpler to build, smaller
◼ More dense (smaller cells = more cells per unit
area)
DRAM
◼ Less expensive
◼ Requires the supporting refresh circuitry
◼ Tend to be favored for large memory
+ requirements
◼ Used for main memory

◼ Static
◼ Faster
◼ Used for cache memory (both on and off chip)
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+
Read Only Memory (ROM)
◼ Contains a permanent pattern of data that cannot be
changed or added to

◼ No power source is required to maintain the bit values in

memory

◼ Data or program is permanently in main memory and never

needs to be loaded from a secondary storage device

◼ Data is actually wired into the chip as part of the fabrication

process
◼ Disadvantages of this:
◼ No room for error, if one bit is wrong the whole batch of ROMs
must be thrown out
◼ Data insertion step includes a relatively large fixed cost

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+
Programmable ROM (PROM)

◼ Less expensive alternative

◼ Nonvolatile and may be written into only once

◼ Writing process is performed electrically and may be

performed by supplier or customer at a time later than the
original chip fabrication

◼ Special equipment is required for the writing process

◼ Provides flexibility and convenience

◼ Attractive for high volume production runs

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 Read-Mostly Memory

Flash
EPROM EEPROM
Memory
Electrically erasable
programmable read-only Intermediate between
Erasable programmable
memory EPROM and EEPROM in
read-only memory
both cost and functionality

Can be written into at any

time without erasing prior
contents
Uses an electrical erasing
Erasure process can be
technology, does not
performed repeatedly
Combines the advantage of provide byte-level erasure
non-volatility with the
flexibility of being
updatable in place
More expensive than Microchip is organized so
PROM but it has the that a section of memory
advantage of the multiple More expensive than cells are erased in a single
update capability EPROM action or “flash”

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 RAS CAS WE OE

Timing and Control

Refresh
Counter MUX

Row Row Memory array

Address De- (2048 2048 4)
A0 coder
A1 Buffer

Data Input
A10 Column Buffer D1
Address D2
Refresh circuitry D3
Buffer Data Output D4
Buffer
Column Decoder

Figure 5.3 Typical 16 Megabit DRAM (4M 4)

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 A19 1 32 Vcc Vcc 1 24 Vss
1M 8 4M 4
A16 2 31 A18 D0 2 23 D3
A15 3 30 A17 D1 3 22 D2
A12 4 29 A14 WE 4 21 CAS
A7 5 28 A13 RAS 5 20 OE
A6 6 27 A8 NC 6 19 A9
A5 7 26 A9 A10 7 24 Pin Dip 18 A8
A4 8 25 A11 A0 8 17 A7
0.6"
A3 9 32 Pin Dip 24 Vpp A1 9 16 A6
A2 10 23 A10 A2 10 15 A5
0.6"
A1 11 22 CE A3 11 14 A4
A0 12 21 D7 Vcc 12 13 Vss
Top View
D0 13 20 D6
D1 14 19 D5
D2 15 18 D4
Vss 16 17 D3
Top View

(a) 8 Mbit EPROM (b) 16 Mbit DRAM

Figure 5.4 Typical Memory Package Pins and Signals

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