1

+
Chapter 5
Internal Memory
+ 2

Memory Cell Operation

 3

Semiconductor Memory Types

Table 5.1 Semiconductor Memory Types

+ 4

Dynamic RAM (DRAM)

 RAM technology is divided into two technologies:
 Dynamic RAM (DRAM)
 Static RAM (SRAM)

 DRAM

 Made with cells that store data as charge on capacitors

 Presence or absence of charge in a capacitor is interpreted

as a binary 1 or 0

 Requires periodic charge refreshing to maintain data

storage

 The term dynamic refers to tendency of the stored charge

to leak away, even with power continuously applied
 5
+
Dynamic
RAM
Structure

Figure 5.2a
Typical Memory Cell Structures
 6
+
Static RAM
(SRAM)
 Digital device that uses the same
logic elements used in the
processor

 Binary values are stored using

traditional flip-flop logic gate
configurations

 Will hold its data as long as power

is supplied to it
 7
+
Static
RAM
Structure

Figure 5.2b
Typical Memory Cell Structures
 8

SRAM versus DRAM

SRAM
 Both volatile
 Power must be continuously supplied to the
memory to preserve the bit values

 Dynamic cell
 Simpler to build, smaller
 More dense (smaller cells = more cells per unit
area)
DRAM
 Less expensive
 Requires the supporting refresh circuitry
 Tend to be favored for large memory
+ requirements
 Used for main memory

 Static
 Faster
 Used for cache memory (both on and off chip)
+ 9

Read Only Memory (ROM)

 Contains a permanent pattern of data that cannot be
changed or added to

 No power source is required to maintain the bit values in

memory

 Data or program is permanent in the memory and never

needs to be loaded from a secondary storage device

 Data is actually wired into the chip as part of the fabrication

process
 Disadvantages of this:
 No room for error, if one bit is wrong the whole batch of ROMs
must be thrown out
 Data insertion step includes a relatively large fixed cost
+ 10

Programmable ROM (PROM)

 Less expensive alternative

 Nonvolatile and may be written into only once

 Writing process is performed electrically and may be

performed by supplier or customer at a time later than the
original chip fabrication

 Special equipment is required for the writing process

 Provides flexibility and convenience

 Attractive for high volume production runs

 11

Read-Mostly Memory

Flash
EPROM EEPROM
Memory
Electrically erasable
programmable read-only Intermediate between
Erasable programmable
memory EPROM and EEPROM in
read-only memory
both cost and functionality

Can be written into at any

time without erasing prior
contents
Uses an electrical erasing
Erasure process can be
technology, does not
performed repeatedly
Combines the advantage of provide byte-level erasure
non-volatility with the
flexibility of being
updatable in place
More expensive than Microchip is organized so
PROM but it has the that a section of memory
advantage of the multiple More expensive than cells are erased in a single
update capability EPROM action or “flash”
Typical 16 Mb DRAM (4M x 4)
12
Chip Packaging 13
 14

256-KByte
Memory
Organization

+
1MByte Module Organization
15
Interleaved Memory
16
Composed of a collection of
DRAM chips

Grouped together to form a

memory bank

Each bank is independently

able to service a memory read
or write request

K banks can service K requests

simultaneously, increasing
memory read or write rates by
a factor of K

If consecutive words of
memory are stored in different
banks, the transfer of a block of
memory is speeded up
+ 17

Error Correction
 Hard Failure
 Permanent physical defect
 Memory cell or cells affected cannot reliably store data but become
stuck at 0 or 1 or switch erratically between 0 and 1
 Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
 Wear

 Soft Error
 Random, non-destructive event that alters the contents of one or more
memory cells
 No permanent damage to memory
 Can be caused by:
 Power supply problems
 Alpha particles
Error Correcting Code Function 18
 19

+
Hamming
Error
Correcting
Code
 20

Table 5.3
Performance
Comparison
DRAM Alternatives

Table 5.3 Performance Comparison of Some DRAM Alternatives

+ 21

Layout of Data Bits and Check Bits

 22

Check Bit Calculation

+ 23

Hamming SEC-DED Code

 24
Advanced DRAM Organization SDRAM

 One of the most critical system bottlenecks when using

high-performance processors is the interface to main
internal memory DDR-DRAM
 The traditional DRAM chip is constrained both by its
internal architecture and by its interface to the
processor’s memory bus

 A number of enhancements to the basic DRAM

architecture have been explored: RDRAM

Table 5.3 Performance Comparison of Some DRAM Alternatives

Synchronous DRAM (SDRAM)
25

One of the most widely used forms of DRAM

Exchanges data with the processor synchronized

to an external clock signal and running at the full
speed of the processor/memory bus without
imposing wait states

With synchronous access the DRAM moves data in

and out under control of the system clock
• The processor or other master issues the instruction
and address information which is latched by the DRAM
• The DRAM then responds after a set number of clock
cycles
• Meanwhile the master can safely do other tasks while
the SDRAM is processing
26

S
D
R
A
M
+ 27

SDRAM Pin Assignments

Table 5.4 SDRAM Pin Assignments

+ 28

SDRAM Read Timing

 RDRAM Developed by Rambus
29

Bus delivers address and

control information using an
asynchronous block-oriented Adopted by Intel for its
protocol Pentium and Itanium
•Gets a memory request over the high- processors
speed bus
•Request contains the desired
address, the type of operation, and
the number of bytes in the operation

Bus can address up to 320

Has become the main
RDRAM chips and is rated at
competitor to SDRAM
1.6 GBps

Chips are vertical packages

with all pins on one side
•Exchanges data with the processor over
28 wires no more than 12 centimeters
long
+ 30

RDRAM Structure
+ 31

Double Data Rate SDRAM

(DDR SDRAM)

 SDRAM can only send data once per bus clock cycle

 Double-data-rate SDRAM can send data twice per clock

cycle, once on the rising edge of the clock pulse and once on
the falling edge

 Developed by the JEDEC Solid State Technology Association

(Electronic Industries Alliance’s semiconductor-engineering-
standardization body)
+
DDR SDRAM
Read
Timing

32
+ 33

Cache DRAM (CDRAM)

 Developed by Mitsubishi

 Integrates a small SRAM cache onto a generic DRAM chip

 SRAM on the CDRAM can be used in two ways:

 It can be used as a true cache consisting of a number of 64-bit
lines
 Cache mode of the CDRAM is effective for ordinary random
access to memory
 Can also be used as a buffer to support the serial access of a
block of data
+ Summary
34

Internal
Memory
Chapter 5

 Semiconductor main memory

 Hamming code
 Organization
 DRAM and SRAM  Advanced DRAM organization
 Types of ROM  Synchronous DRAM
 Chip logic  Rambus DRAM
 Chip packaging  DDR SDRAM
 Module organization  Cache DRAM
 Interleaved memory
 Error correction
 Hard failure
 Soft error