Embedded Systems.

Lecture 7: Memory Technologies and Hierarchy

1
Sensitivity: Public
 Introduction
An embedded system is a special-purpose
computer system designed to perform one
or a few dedicated functions, sometimes
with real-time computing constraints.
An embedded system is part of a larger
system.
 Embedded systems often have small memory
and are required to run a long time, so memory
management is a major concern when
developing real-time applications.

2
Sensitivity: Public
 Context
8 bit data bus

Flash
Memory
Register
File

Registers
SRAM
Registers
Memory
Registers
EEPROM

Atmel ATmega168 Datapath 3

Sensitivity: Public
 Memory
• Looks like a very long list.
• Each row is called a memory
location and has a unique
address
• Each location stores the same
number of bits, usually multiples
of 8 bit (bytes)
• Number of addresses 2^N (where
N is an integer).

4
Sensitivity: Public
 Memory from Programmer’s
Perspective

Store

Memory
Load

5
Sensitivity: Public
 Common Memory Types

Sensitivity: Public
 Random Access Memory
• Contents lost without power (volatile
memory).
• Used to store temporary data. In embedded
system, very little RAM is required. Some
systems don’t even have RAM at all!
• No limit to number of writes the device can
handle.
• Fast writes (unlike EPROM/EEPROM)
• Two major types are SRAM and DRAM

7
Sensitivity: Public
 RAM-DRAM Memory Technology

• Dynamic random-access memory

• Volatile memory.
• Capacitor charge state indicates stored value
• Whether the capacitor is charged or discharged indicates
storage of 1 or 0 DRAM
• 1 capacitor & 1 access transistor
• Slower => used for main memory.
• Cheaper / bit => lower cost.
• Capacitor leaks
• DRAM cell loses charge over time
• DRAM cell needs to be refreshed
• Requires periodical refreshing every 10-100 ms => dynamic.
8
Sensitivity: Public
 RAM:SRAM Memory Technology
• Static random-access memory
• Two cross coupled inverters store a single bit
• Feedback path enables the stored value to persist in the “cell”
• Six transistors / bit => lower capacity.
bitline bitline
• 4 transistors for storage wordline
• 2 transistors for access
• More expensive / bit => higher cost
• Faster => used in caches
SRAM

• No refreshing required => faster & lower power consumption.

9
Sensitivity: Public
 ROM: Read Only Memory
• Non-volatile memory: content is retained even without power.
• In embedded systems, used to store application programs and
test routines.
• Contents can be set by fixing it during manufacturing or
“burning” it using a programming device
• Common types include MROM, PROM, EPROM and flash
memory
• Erasable types can only be rewritten a fixed number of times
• Can be read from but not written to, by a processor in an
embedded system.
• Traditionally written to, “programmed”, before inserting to
embedded system.
• Stores constant data needed by system.
• Some embedded systems work without RAM, exclusively on
ROM, because their programs and data are rarely changed.
Sensitivity: Public
 ROM:MROM/EPROM/EEPROM
• Mask ROM (MROM)
• Non-reprogrammable read only memory
• Its cheap (dense)
• EPROM
• Erasable programmable read-only memory
• Erase by using UV light
• EEPROM
• Electrically erasable programmable read-only memory
• Can be reprogrammed many times
• Can be erased at byte granularity
• All are often used to store small read-only code
• E.g., Boot loader
11
Sensitivity: Public
 Some Memory Types-Flash Memory

• Non-volatile memory.
• Can be electrically erased & reprogrammed.
• Used in memory cards, and USB flash drives.
• It is erased and programmed in large blocks at
once, rather than one word at a time.
• Examples of applications include PDAs and
laptop computers, digital audio players,
digital cameras and cell phones.

12
Sensitivity: Public
 Some Memory Types-Flash Memory

Two types
• NOR Flash (e.g., S70GL02GT Cypress device)
• Reads at byte granularity
• Fast random reads (~120ns)
• slow writes (~520ms to erase 120KB)
• Lesser density
• Primarily used as code storage
• NAND Flash (e.g., S34ML04G2 Cypress device)
• Page addressable (e.g., 512 Bytes )
• Slow random reads (~30us)
• fast writes (~3.5ms to erase 120KB)
• Higher density
• Primarily used as data storage 13
Sensitivity: Public
 Types of Memories
SSD: $0.75 /GB, HDD: $0.1-0.2/GB
DRAM: $20-25/GB
Type Size Latency Cost/bit

Register < 1KB < 1ns $$$$

On-chip SRAM 8KB-6MB < 2ns $$$

Off-chip SRAM 1Mb – 16Mb < 10ns $$

DRAM 64MB – 1TB < 100ns $

Disk (SSD, HDD) 40GB – 1PB < 20ms < $1/GB

Sensitivity: Public
 Memory Hierarchy
Memory hierarchy is about arranging different kinds of storage
devices in a computer based on their size, cost and access speed,
and the roles they play in application processing. The main
purpose is to achieve efficient operations by organizing the
memory to reduce access time while speeding up operations.
• Is an approach for organizing memory and storage
systems.
• A memory hierarchy is organized into several levels –
each smaller, faster, & more expensive / byte than the
next lower level.
• Device at level k serves as a cache for the larger, slower
device at level k+1.
• Programs tend to access the data at level k more often
than they access the data at level k+1.
Sensitivity: Public
 Memory Hierarchy

Registers
On-Chip Cache

SPEED and COST

SRAM
CAPACITY

Off-Chip Cache
SRAM
Main Memory-DRAM

Local secondary storage-Flash/Disk

16
Sensitivity: Public
 Why to Implement the Memory Subsystem as
a Hierarchy?

Locality of reference: tendency of the

computer program to access instructions
whose addresses are near one another.

17
Sensitivity: Public
 Types of Locality of reference
• Temporal Locality: means current data or instruction
that is being fetched may be needed soon. So, we
should store that data or instruction in the cache
memory so that we can avoid again searching in main
memory for the same data.
• Spatial locality: means instruction or data near to the
current memory location that is being fetched, may be
needed by the processor soon. This is different from
the temporal locality in that we are making a guess that
the data/instructions will be needed soon. With
temporal locality we were talking about the actual
memory location that was being fetched. 18
Sensitivity: Public
 Memory Hierarchy
Temporal locality Spatial locality
•Keep recently •Bring neighbors of
referenced items at recently referenced
higher levels CPU to higher levels
•Future references •Future references
satisfied quickly satisfied quickly
Cache (SRAM)

Main Memory (DRAM)

NAND Flash
19
Sensitivity: Public
 Word size and data bus size
• The Width of data bus determines the amount of data
transferable in one step.
• Original m68000 has a 16-bit data bus
– Can transfer 1 word or 2 bytes at once
– A longword requires two transfers
• Current 68HC000 has a selectable bus width of 8 or 16 bits
– Selecting 8-bit data bus results in cheaper system but lower
performance
• The maximum amount of memory for any 68000 system is 16
Mega locations x 1 byte/location = 16 Megabytes
– Can also be thought of as 8 Mega words
- a word is 16 bits or 8 Bytes.

20
Sensitivity: Public
 Memory Space and Address Bus
• Smallest transferable amount of data from memory to CPU
(and vice versa) is one byte (8 bits).
• Each byte has a unique location or address.
• The address of each byte is written in hexadecimal (hex).–
For 68000, the prefix ‘$’ means a hex value.
• The range of addresses accessible by the processor is the
memory space.– Limited by the size of the address bus.
• From the programmer’s point of view, the m68000 with an
address bus of 24 bits wide. Has;
– Memory space is 0 to 2^24 -1 (1 6777216 or 16 Megabyte)
– Written in hex as $000000 to $FFFFFF.

21
Sensitivity: Public
 Array Organization of Memories
Components
N bits
• A memory array Address Data
Array
• Address decoder
• I/O circuitry
M bits

M-bit data can be stored/loaded in/from at Data

each unique N-bit address
• Addressability: M bits
• Address space: unique addresses
22
Sensitivity: Public
 Memory Array Example
Address data
0x00 0x00
8 bits 0x01 0xF1
Address 0x02 0x11
… …
0xFE 0x20
0xFF 0x34

8 bits

Data 23
Sensitivity: Public
 Memory Array Organization
• Storage nodes in one column connected to one bitline
• Address decoder activates only ONE wordline
• Content of one line of storage available at output
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11

Address 2 Active wordline stored stored stored

bit = 0 bit = 1 bit = 0
wordline2
10 10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1

Data2 Data1 Data0 24

Sensitivity: Public 1 0 0
 How the Accesses Are Controlled?
• Access transistors configured as switches connect
the bit storage to the bit line.
• Access controlled by the worldline.
bitline
wordline
stored
bit

bitline bitline
wordline

Sensitivity: Public
DRAM SRAM 25
 Memory Bank Organization and
Operation
Read access sequence
1. Decode row address &
drive word-lines
2. Selected bits drive bit-
lines (entire row read)
3. Amplify row data
4. Decode column address
& select subset of row
• Send to output

26
Sensitivity: Public
 Memory Bank Organization and
Operation
Write access sequence
1. Decode row address &
drive word-lines
2. Selected bits drive bit-
lines (entire row read)
3. Amplify row data
4. Decode column address
& update selected subset
of row with “Data In”
• Write data

Data In

27
Sensitivity: Public
 Memory Read Example
8 X 16 bits Memory Array
1 0 1 1 0 1
0 Read access sequence
1 0 1 1 1101011101010101
1101011101010101 1. Decode row address &
2 drive word-lines
4 bits 3 bits 1001001101100101
3
1001011111110111 2. Selected bits drive bit-
4 lines (entire row read)
1101111101110101
5
1100011111011101 3. Amplify row data
6
1111011101011101 4. Decode column address
1 7
1101010101010000 & select subset of row
1 bits • Send to output

8 bits

Data In/Out
11011101
28
Sensitivity: Public
 Worked examples-1
Write down the differences between SRAM and DRAM . Show
the memory hierarchy and point out where are DRAM and
SRAM employed respectively.

SRSRAM DRAM
SRAM has lower access time, which is DRAM has a higher access time. It is
faster compared to DRAM. slower than SRAM.
SRAM is costlier than DRAM. DRAM cost is lesser compared to SRAM

SRAM needs a constant power supply,
but it consumes less power.
SRAM is of a smaller size.
Sensitivity: Public
DRAM requires more power consumption
as the information is stored in the
capacitor
DRAM is available in larger storage
capacity
29
 Worked examples-2
A 64-bit microcontroller has 256KB of internal EEPROM Memory. we wish to save a text file
that contains 38250 characters on the EEPROM. The program to implement this will occupy 4020
registers in the same memory. Determine whether the internal EEPROM memory will suffice.
Solution
We need to calculate the total memory required to store both the text file and the program. The
number of bits required to store one character in ASCII encoding is 8 bits. Therefore, the number
of bits required to store 38250 characters is:
=38250 characters * 8 bits/character = 306000 bits
Since the EEPROM memory is measured in bytes, we need to convert the number of bits to
bytes=306000 bits / 8 bits/byte = 38250 bytes.So, we need 38250 bytes of memory to store the
text file.
4020 registers * 8 bytes/register = 32160 bytes
• Therefore, the total memory required to store both the text file and the program is:
• 38250 bytes + 32160 bytes = 70,410 bytes
• Since the internal EEPROM memory of the microcontroller is 256KB (=256*1024 =262,144
bytes), it is sufficient to store both the text file and the program.
30
Sensitivity: Public