BME 3101:Microprocessors

EUGENE BIZIMANA.
Department of Biomedical Science
Engineering

@MUST 1
 Memory and I/O Design
Outline
• Memory and I/O Design;
• Digital I/O
• D/A and A/D signal conversions and converters

@MUST 2
 Microprocessor Memory Design
• The main purpose of a memory unit is to hold
instructions and data.
• The major design goal of a memory unit is to
allow it to operate at a speed close to that of a
microprocessor.
• High speed memory is extremely expensive and it
is Practically not feasible to design a large
memory unit.

@MUST 3
 Classification of Memory
• A microcomputer memory system can be broadly
divided into three groups:

1. Microprocessor memory
2. Primary or main memory
3. Secondary memory

@MUST 4
 Memory Hierarchy

Registers By Using a hierarchy of

memory each with different
Cache
access speeds and storage
capabilities a computer
system can exhibit
Memory
performance above what
would be possible without a
Disk
combination of the various
types.
Tape

Fig. 1: Memory Hierarchy

@MUST 5
• The memory closest to the processor is relatively
small but its very fast and expensive.

• The memory most distant from the processor is

disk memory which is very slow but least
expensive.

@MUST 6
 Main Memory
• The main memory is divided into:
i. Random Access Memory (RAM)
ii. Read Only Memory (ROM)

@MUST 7
 Random Access Memory (RAM)
• This type of memory is temporary or volatile in nature as
its data is erased when the system is shut down.

• RAM is a read/write memory as information can be

written into and read from a RAM.

• All active programs are stored in the RAM.

• There are 2 types of RAM

i. Dynamic RAM
ii. Static RAM
@MUST 8
 Dynamic RAM(DRAM)
• It consists of a transistor and capacitor. The capacitor has the ability to
store an electric charge.

• The amount of time taken to produce data required from memory,

from the start of access until the availability of data is called memory
access time.

• However, a capacitor loses charge over a period of time, and can

retain data for barely a thousandth of a second.

• Therefore, the memory controller needs to refresh the memory

contents frequently.

• DRAM is characterized by high density and low power

@MUST 9
 Dynamic Random Access Memories

Word Line

DRAM, is designed using a

capacitor and FET. As the capacitor
is charged, it stores a “1”while it
Bit Line
stores a “0” when it is discharged.
There is need for Refresh Cycles
as storage decay in ms
Fig. 4: DRAM

@MUST 10
 Static RAM (SRAM)
• It consists of internal flip-flops that store the binary
information.

• It takes up more space for a given storage capacity than do

dynamic RAMs.

• Static RAMs are used in specialized applications while

dynamic RAMs are used in the primary storage sections of
most computers.

• The static RAM is easier to use and has shorter read and write
cycles compared to dynamic RAM.
@MUST 11
 Static Random Access Memories
SRAM cell is a type of flip-flop circuit, usually
implemented using FETs.

Data Data j
j
Word Enable
i

Words = Rows Static RAM Cell

Static RAM Cell Static RAM Cell

Fig. 5: SRAM

Columns =@MUST
Bits (Double Rail Encoded) 12
 RAM Timing
WE

CS

Fig. 2: Simplified Read Timing

Address Valid Address
Access Time

Data Out Data Out

WE

CS
Fig: 3:Simplified Write Timing
Memory Cycle Time
Address Valid Address

Data In Input Data

@MUST 13
 Static RAM Organization
1024 x 4 SRAM
CS
Chip Select Line (active lo) WE
A9
Write Enable Line (active lo) A8
A7 IO3
A6 IO2
10 Address Lines A5 IO1
A4 IO0
4 Bidirectional Data Lines A3
A2
A1
A0

Fig. 6: SRAM Organization

@MUST 14
 Memory Cell
• The memory cell is the fundamental building block of
computer memory.

• The memory cell is an electronic circuit that stores one bit of

binary information and it must be set to store a logic 1 (high
voltage level) and reset to store a logic 0 (low voltage level).

• Its value is maintained/stored until it is changed by the

set/reset process.

• The value in the memory cell can be accessed by reading it.

@MUST 15
 Memory Addresses
• A memory address is a reference to a specific
memory location used at various levels by
software and hardware.

• The 2 main types of memory addresses are:

i. Physical addresses
ii. Logical addresses

@MUST 16
 Physical Addresses
• The main memory of a microcomputer has many
memory locations.

• Each memory location consists of a physical

address which is a code.

• The CPU (or other device) can use the code to

access the corresponding memory location.

@MUST 17
 Logical Addresses
• A logical address is the address at which a memory
cell appears to reside from the perspective of an
executing application program.

• A logical address may be different from the physical

address due to the operation of an address translator.

• The physical address of computer memory banks may

be mapped to different logical addresses for various
purposes.
@MUST 18
 Memory Bottleneck
• The microprocessor is connected to memory and I/O
unit via buses.

• Whenever the microprocessor needs to process data, it

gives the address of the corresponding memory location
in RAM or address of input port on address bus.

• This is a slow process as the microprocessor has to wait

for data.

• This problem is called memory bottleneck.

@MUST 19
• The problem of memory bottleneck is solved with
the inclusion of registers and cache memory.

i. Registers: are built into the microprocessor to

hold data currently in use.

ii. Cache Memory: This refers to high speed

memory used to hold frequently used data in
order to increase speed of accessing data and
instructions stored in the main memory.

@MUST 20
• When a memory address is generated, cache
is searched first to determine if the address
exists there.

• When the address is not found in cache, the

entire main memory block in which the word
resides is loaded into cache.

@MUST 21
 Types of Cache
i.Level 1 (L1) Cache: Also known as primary cache,
is extremely fast but relatively small, and is usually
embedded in the processor chip as CPU each.

ii.Level 2 (L2) or Secondary Cache: L2 cache may

be embedded on the CPU, or it may be on a
separate chip and have a high-speed alternative
system bus connecting the cache and CPU.
Consequently, it does not get slowed by traffic on
the main system bus.
@MUST 22
iii. Level 3 (L3) Cache:
• This is specialized memory developed to
improve the performance of L1 and L2.

• Though slower than L1 or L2 cache, L3 is usually

double the speed of RAM.

• With multicore processors, each core can have

dedicated L1 and L2 cache, but they can share
an L3 cache.

@MUST 23
 Cache Hit Ratio
• The performance of cache memory is measured
in terms of its hit ratio.

• When the CPU refers to memory and finds the

word in cache it is said to produce a hit.

• If the word is not found in cache, it is in main

memory then it counts as a miss.

@MUST 24
 Hit Ratio
• The ratio of the number of hits to the total CPU
references to memory is called hit ratio.

@MUST 25
 Hit Time
• The time required to access the requested
information in a given level of memory.

@MUST 26
 Read Only Memory
• This refers to memory that performs the read
only operation. It does not have write capability.

• Types of ROM include:

i. Programmable ROM
ii. Erasable Programmable ROM
iii. Electrically Alterable Programmable ROM
iv. Electrically Erasable PROM

@MUST 27
 Read-Only Memories
2764 EPROM 2764 2764
8K x 8 +
VPP
PGM +
VPP
PGM
A12 A12
A11 A11
2764 A10 O7 A10 O7
A9 O6 A9 O6
VPP A8 O5 A8 O5
A7 O4 A7 O4
PGM A6 O3 A6 O3
A12 A5 O2 A5 O2
A4 O1 A4 O1
A11 A3 O0 A3 O0
A2 A2
A10 O7 A1 A1
A0 A0
A9 O6 CS U3 CS U2
A8 OE OE
O5
A7 O4
A13
A6 /OE
O3 A12:A0
A5 O2 D15:D8
A4 D7:D0
O1 2764 2764
A3 O0 + VPP
+
VPP
PGM PGM
A2 A12 A12
A11 A11
A1 A10 O7 A10 O7
A9 O6 A9 O6
A0 A8 O5 A8 O5
CS A7 O4 A7 O4
A6 O3 A6 O3
OE A5 O2 A5 O2
A4 O1 A4 O1
A3 O0 A3 O0
A2 A2
A1 A1
A0 A0
CS U1 CS U0
16K x 16 OE OE
Subsystem
Fig. 7:ROMs
@MUST 28
i. Programmable ROM
This is a ROM that can be programmed to record
information using PROM programmer that
information cannot be changed.

ii. Erasable Programmable ROM: is another type of

ROM that can be erased using ultraviolet light
(UPROM) & Electrically Alterable (EAPROM) and
the chip can be reprogrammed to record different
information using a special PROM-program facility

@MUST 29
iii. Electrically Erasable PROM (EEPROM): This
refers to ROM that can be programmed and erased
by electrical signals.

@MUST 30
 Input/output Devices
• The input and output devices are known as
peripheral or input/output devices in the
microcomputer.

• Examples include Keyboard, mouse, scanner, USB

etc.

• Peripheral interface devices provide the means of

data transfer between the microprocessor and the
peripherals.
@MUST 31
•The process of data transfer between
microprocessor and peripherals is generally
controlled by the microprocessor and in some cases
it is controlled by peripherals.

•Microprocessor communicates with peripherals in

parallel or serial I/O methods.

@MUST 32
i. Parallel Data Transmission
•In parallel methods of communication, data word
are transferred in parallel all at the same time. It is
usually faster than the serial methods.

Fig. 8:Parallel Data Transmission

@MUST 33
 ii. Serial Data Transmission

The data is sent as a stream of bits on a single line

in a serial I/O method.

Fig. 9:Serial Data

Transmission
@MUST 34
 Differences between Serial and Parallel
Transmission
Parallel Transmission Serial Transmission

Requires multiple lines to send Requires a single line to send

data.
There are more errors and noise
Faster since data flows through
multiple lines
half duplex since the data can be
sent or received at a time.
Cables used are larger and more
expensive
reliable and straightforward.
data.
Contain less errors and noise
Slower since data flows through
a single line
full duplex since the sender can
send and receive data.
The cables used in serial
transmission are thinner and
more economical
Unreliable and complicated

@MUST 35
 Parallel I/O Methods
i. Simple I/O
ii. Strobe I/O
iii. Handshake I/O

i. Simple I/O Data Transfer: In a simple I/O, the

microprocessor transfers data byte assuming that the
peripheral is always ready to send or receive the byte.

They are not suitable to transfer data from microprocessor

to slow devices as slow devices do not send or accept data
at the speed of microprocessors.
@MUST 36
ii. Strobe I/O: In this method, the microprocessor transfers
the data only when the peripheral is ready.

Slow devices generate a control signal called strobe along

with valid data. Strobe signal indicates the valid data is
present on the data lines.

The readiness of the microprocessor is communicated

through either polling or interrupt.

In polling method, the strobe line is connected to an input

port line as the microprocessor keeps reading the input port
repeatedly.
@MUST 37
iii. Handshake I/O: In handshake I/O method, the
microprocessor and the peripheral exchange
handshake signals to indicate the readiness of the
peripherals and synchronize the timing of data
transfer.

@MUST 38
 Example of Handshaking

• Suppose a printer is connected to a system. The printer can

print 100 characters/second, but the microprocessor can
send much more information to it at the same time.
• Just when the printer gets enough data to print it places a
logic 1 signal at its Busy pin, indicating it is busy printing.
• The microprocessor now tests the busy bit to decide if the
printer is busy or not.
• When the printer will become free it will change the busy
bit and the microprocessor will again send enough
amounts of data to be printed.
• This process of interrogating the printer is called
handshaking.
@MUST 39
 I/O Mapping
• This describes a technique used to interface
peripheral devices to a microprocessor whose
architecture supports input and output instructions.

• An I/O mapped device is assigned one or more of

the processor's I/O port addresses, and data.

• Status information are transferred between the

processor and the peripheral device using the
processor's input and output instructions.
@MUST 40
 Methods of I/O Mapping
• There are basically 2 methods:
i. I/O Mapped I/O
ii. Memory Mapped I/O

@MUST 41
 I/O mapped I/O (isolated I/O)
1. Different address spaces for memory and I/O
devices.

2. Uses a special class of CPU instructions to access

I/O devices.

3. x86 Intel microprocessors - IN and OUT

instructions.

@MUST 42
 Memory Mapped I/O
1.Same address bus to address memory and I/O
devices

2.Most widely used I/O method

3.Access to the I/O devices using regular

instructions

@MUST 43
Comparison Between Memory Mapping and I/O
Mapping
Memory Mapping
1. The devices are accessed by
memory read or write cycle
2. 16-bit addresses are provided for
I/O devices
3. The I/O ports or peripherals can be
treated as memory locations and so
all instructions related to memory can
be used for data transfer between I/O
device and the microprocessor
4. The data can be transferred from
any register to ports.
5. In memory mapping a large
number of I/O ports can be
interfaced.
I/O Mapping
1. The devices are access by I/O read
or write cycle.
2. 8-bit addresses are provided for I/O
devices
3. In I/O mapping, IN and OUT
instructions are used for data transfer
between I/O device and the
microprocessor.
4. Data transfer can occur only
between the accumulator and the
ports.
5. In I/O Mapping only 28 (256) ports
can be interfaced

@MUST 44
Asynchronous and Synchronous Transmission
Data transmission through a medium can be either asynchronous or
synchronous.

1. Asynchronous Data Transmission:

In asynchronous transmission a special bit called ‘Start Bit’ is sent
before the bits that make up the character and one ‘Stop Bit’ is sent
at the end.
Asynchronous transmission is also known as Start-Stop Transmission.
The start bit alerts the receiving device that a character is about to be
transmitted.
The stop bits inform the receiver that no more bits will be sent for a
while.

@MUST 45
• Data is transmitted character by character as
you go on typing on a keyboard. As a result,
there is irregular gaps between characters.
However, it is cheaper to implement, as the
one is not required to save the data before
sending.

@MUST 46
Fig. 10: Asynchronous Data Transmission

@MUST 47
 2. Synchronous Transmission
In the synchronous data is sent as a continuous stream at a
constant rate making maximum use of available line capacity

The saved data is transmitted block by block. Each block can

contain many characters.

If a bus is synchronous (e.g. Processor-memory), it includes a

clock in the control lines and a fixed protocol for communicating
that is relative to the clock.

Synchronous transmission is well suited for remote

communication between a computer and related devices like card
reader and printers.
@MUST 48
 Fig. 11: Synchronous Transmission

Synchronous transmission is illustrated in Fig. 11.

@MUST 49
 Digital Input/output
• The digital I/O interface allow a computer to
interface with external digital signals.

• Digital I/O can be used for monitoring the status

of digital signals (input), and controlling the
status of digital signals (output), or transferring
digital data at high speed between machines.

@MUST 50
 DIRECT MEMORY ACCESS
•Direct memory access (DMA) is a feature of
computer systems that allows certain hardware
subsystems to access main memory independent of
the CPU.
•Without DMA, when the CPU is using programmed
input/output, it is typically fully occupied for the
entire duration of the read or write operation, and
is thus unavailable to perform other work.

@MUST 51
• With DMA, the CPU first initiates the transfer, then it does other
operations while the transfer is in progress, and it finally receives
an interrupt from the DMA controller when the operation is
done.

• Generally, a specified portion of memory is designated as an

area to be used for direct memory access.

• Many hardware systems use DMA, including disk drive

controllers, graphics cards, network cards and sound cards. DMA
is also used for intra-chip data transfer in multi-core processors.

• Computers that have DMA channels can transfer data to and

from devices with much less CPU overhead than computers
without DMA channels.
@MUST 52
•The task of a DMA-controller (DMAC) is to execute
the copy operation of data from one resource
location to another.

• The copy of data can be performed from:

 I/O-device to memory
 memory to I/O-device
 memory to memory
 I/O-device to I/O-device

@MUST 53
• In the ISA bus standard, about 16 MB of memory
can be addressed for DMA.

• The EISA and Micro Channel Architecture

standards allow access to the full range of
memory addresses.

• Peripheral Component Interconnect completes

DMA by using a bus master with the
microprocessor "delegating" I/O control to the
PCI controller.

@MUST 54
 DMA OPERATION
Fig. 10 shows the DMA operation. Three numbers of
switches are shown in the figure.

Usually, the switch positions are such that the

memory and peripheral devices are connected to
the CPU.

Anytime the DMA operation is carried out, the CPU

is totally isolated and the address lines and control
lines and taken over by the DMA controller circuitry.
@MUST 55
Fig. 12: Functional Block Diagram of a system with DMA
(Theagarajan, 2003)
@MUST 56
• To actuate the DMA operation, the following
sequence is carried out:
1. The device sends DMA request to the DMA
controller.
2. The DMA controller raises the hold request line
and it is connected to the hold signal input of
the microprocessor.
3. The microprocessor, tristates all the address
lines, data lines and control lines and
acknowledges the hold input signal through hold
acknowledge (HLDA) output signal.
@MUST 57
4. The HLDA signal is connected to the DMA
controller. Once it becomes active, the DMA
controller sends acknowledgement signal to the
device which requested for DMA operation to
enable the device for data transfer.

5. DMA operation is carried out by sending suitable

address to the memory and suitable control signals
to transfer a byte of data. The DMA controller
increments its internal address register until the full
block of data is transferred.
@MUST 58
6. Before carrying out DMA operation, the DMA
controller should know:
i. The starting address of the memory location.
ii. Number of bytes to be transferred
iii. Whether the transfer is from memory to I/O or
from I/O to memory.

@MUST 59
 Analog Signals
They are continuously valued signal, such as
temperature or speed, with infinite possible values
in between as shown in fig. 13.

Fig . 13: Analog Signals

@MUST 60
 Digital Signals
•They are discretely valued signal, such as integers, encoded
in binary.
•Digital signals must have a finite set of possible values
usually one of two values – like either 0V or 5V.
• Timing graphs of these signals look like square waves as
shown in Fig. 14.

Fig. 14: Digital Signals

61
@MUST
•A digital signal could also be a discrete representation of
an analogue waveform.

Fig. 15: Digital signal as a discrete representation of an

analogue waveform

@MUST 62
 Analogue to Digital Conversion
• Analogue to Digital Conversion involves conversion
of an analog input signal into a digital output signal
using a device known as Analog-to-Digital
Converter (ADC).

• Most signals in the real world are such as

temperature, pressure, light intensity are analog.

• In order to manipulate the data using a

microprocessor, It should be converted to digital
signals, to enable the microprocessor read,
understand and manipulate the data.
@MUST 63
 ADC Implementation
• The following steps are used in implementing
ADC:
1. Sampling of the signal
2. Quantization of sampled signal
3. Digital coding of quantized signals.

@MUST 64
 1. Sampling
•Sampling is the reduction of a continuous-time signal to a
discrete-time signal, a sequence of real numbers.

•Input signal to sampling process is both continuous in time

and amplitude.

For example: where

• Output from a sampling process is discrete in time

but continuous in amplitude.

•For example: If then

@MUST 65
The continuous signal is represented
with a green coloured line while the
discrete samples are indicated by the
blue vertical lines.

Fig. 16: Signal Sampling Representation

@MUST 66
 Nyquist Theory
• The Sampling (Nyquist) Theorem is required for
signal reconstruction.

• The Nyquist Theorem states that in order to

adequately reproduce a signal it should be
periodically sampled at a rate that is 2X the
highest frequency you wish to record.

@MUST 67
 Sample and Hold Circuit
• Sample & Hold Circuit is used to sample the given
input signal and to hold the sampled value
between clock cycles.

• Sample and hold circuit is used to sample an

analog signal for a short interval of time (1 - 10µS)
and to hold on its last sampled value until the
input signal is sampled again.

@MUST 68
Fig. 17: Block Diagram of Sample and Hold Amplifier

@MUST 69
 2. Quantization of Sampled Signal
•Quantization is the process of taking a continuous voltage
signal and mapping it to a discrete number of voltage levels.

•In quantization we are turning a continuous range of values

into a limited set of values as each real number is replaced
with an approximation.

•Quantizing samples to levels and then sequences of bits

leads to quantization error.

•Output from the quantization process is usually discrete in

both time and amplitude which is called digital signal.

@MUST 70
• Since digital computers are binary in nature, the
number of quantization levels is usually a power
of 2, i.e.,
• where n is the number of
quantization bits.
• The signal may be amplified or attenuated before
going into the ADC, so that the maximum and
minimum voltage levels give the best
compromise between resolution of the signal
levels and minimization of clipping.

@MUST 71
Fig 18: ADC CONVERSION PROCESS
@MUST 72
 3. Encoding

• Encoding is the process of converting the quantized

signals into a digital representation or binary
numbers.

• This encoding is performed by giving each

quantization level a unique label.

• For instance, if four bits are used, the lowest level

may be (in binary) 0000, and the next highest level
0001,
@MUST 73
Fig. 19: Block Diagram of ADC Process
@MUST 74
Types of Analogue to Digital Converters

1. Dual Slope A/D Converter

2. Flash A/D Converter
3. Successive Approximation A/D Converter

@MUST 75
 Dual Slope A/D Converter
•It is a slow speed device comprising an integrator circuit formed
by a resistor, capacitor, and operational amplifier combination.
The integrator circuit generates a comparison voltage.

•By the set value of Vref, this integrator generates a sawtooth

waveform on its output from zero to the value Vref.

•When the integrator waveform is started, the counter starts

counting from 0 to 2n - 1 where n is the number of bits of ADC.

•When the input voltage Vin equal to the voltage of the waveform,
then control circuit captures the counter value which is the digital
value of corresponding analogue input value.
@MUST 76
Fig. 16: Dual Slope A/D Converter
@MUST 77
 Flash A/D Converter
•Also known as parallel ADC, it is a widely used
efficient ADC in terms of its speed though expensive.
•This flash ADC circuit consists of a series of
comparators where each one compares the input
signal with a unique reference voltage.
•At each comparator, the output will be high state
when the analog input voltage exceeds the reference
voltage.
•This output is further given to priority encoder for
generating binary code based on higher order input
activity by ignoring other active inputs.
@MUST 78
Fig. 17: Flash A/D Converter
@MUST 79
 Successive Approximation A/D Converter
• It is the most modern ADC IC and much faster
than dual slope and flash ADCs.

• It uses a digital logic that converges the analog

input voltage to the closest value.

• This circuit consists of a comparator, output

latches, successive approximation register (SAR)
and D/A converter.

@MUST 80
• At the start, SAR is reset and as the LOW to HIGH
transition is introduced, the MSB of the SAR is set.
• Then this output is given to the D/A converter that
produces an analog equivalent of the MSB, further
it is compared with the analog input Vin.
• If comparator output is LOW, then MSB will be
cleared by the SAR, otherwise the MSB will be set
to the next position.
• This process continues till all the bits are tried and
after Q0, the SAR makes the parallel output lines to
contain valid data.

@MUST 81
Fig. 18: Successive Approximation A/D Converter

@MUST 82
 Digital-to-Analog Converter
• A Digital to Analog Converter, or DAC, is an electronic device
that converts a digital code to an analog signal such as a
voltage, current, or electric charge.
• Signals can easily be stored and transmitted in digital form;
• However, for signals to be recognized by the human senses or
non-digital systems, they are converted to analog form using
a DAC.
• Converting a signal from digital to analog can degrade the
signal.
• Digital to analog converters are mostly manufactured on an
integrated circuit (IC).
• The suitability of a digital to analog converter for a particular
application is determined by several attributes such as speed
and resolution. @MUST 83
Scaled Resistors in Summing Junction

@MUST 84
• Description of above circuit:
1. The circuit has an input count from 0 (when all
the inputs are OFF) to 15 (when all the inputs are
HIGH.).
2. The maximum input count is 2n – 1.i.e all bits set
to 1.
3. The circuit generates an output voltage from zero
to (almost) 10 Volts.
4. The total maximum current through the gain
resistor is given by:

@MUST 85
• The circuit generates an output voltage from
zero to

@MUST 86
 R-2R LADDER
• A resistor ladder is an electrical circuit made from
repeating units of resistors.

• An R–2R Ladder is a simple and inexpensive way to

perform DAC, using repetitive arrangements of
precise resistor networks in a ladder-like
configuration.

• A basic R–2R resistor ladder network consists of

digital logic gates which drive the binary inputs.
The bits are from the MSB to the LSB.
@MUST 87
R-2R LADDER

@MUST 88
• Ideally, the bit inputs are switched between V = 0 (logic 0)
and V = Vref (logic 1).

• It uses Kirchhoff’s current law. In the ladder, at each node, the

current is split in half.

• The R–2R network causes these digital bits to be weighted in

their contribution to the output voltage Vout.

• By switching the currents into each node the total current

flowing is binary weighted.

• Using the principle of superposition when you add more current

into a resistance the total voltage appearing is the sum of the
voltages caused by all the individual currents i.e. as each bit is
@MUST 89
activated so the voltage increases at the output.
• The voltage contribution of each bit can be
calculated using the thevenin’s theorem.

• For N= 6 bits

@MUST 90
 References
Mathvanan, N. 2003. Microprocessor PC hardware
and interfacing

Theagarajan, R. Microprocessor and Its Applications

@MUST 91